[U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for rk3229
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
Kever Yang (10): lib: add TPL_OF_LIBFDT option for TPL arm: add option for TPL support in arm 32bit arm: add a separate stack for TPL rockchip: rk322x: enable tpl support sysreset: enable driver support in SPL/TPL spl: add support to booting with OP-TEE rockchip: rk322x: dts: enable uart2 for SPL/TPL rockchip: evb-rk3229: add fit source file for itb rockchip: evb-rk3229: add README file for OP-TEE support rockchip: evb-rk322x: update defconfig with tpl and optee support
arch/arm/Kconfig | 29 ++++++++++ arch/arm/dts/rk3229-evb.dts | 1 + arch/arm/lib/crt0.S | 4 +- arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 66 ++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 81 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 +++++ board/rockchip/evb_rk3229/README | 72 +++++++++++++++++++++++++ board/rockchip/evb_rk3229/fit_spl_optee.its | 48 +++++++++++++++++ common/spl/Kconfig | 7 +++ common/spl/Makefile | 1 + common/spl/spl.c | 5 ++ common/spl/spl_optee.S | 13 +++++ configs/evb-rk3229_defconfig | 28 ++++++++-- drivers/sysreset/Kconfig | 18 +++++++ drivers/sysreset/Makefile | 2 +- include/configs/rk322x_common.h | 12 +++-- include/spl.h | 9 ++++ lib/Kconfig | 10 ++++ 20 files changed, 369 insertions(+), 62 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds create mode 100644 board/rockchip/evb_rk3229/README create mode 100644 board/rockchip/evb_rk3229/fit_spl_optee.its create mode 100644 common/spl/spl_optee.S
TPL may need use libfdt for dt decode, add option for it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
lib/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/lib/Kconfig b/lib/Kconfig index d73052d..d2a6dae 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -204,6 +204,16 @@ config SPL_OF_LIBFDT particular compatible nodes. The library operates on a flattened version of the device tree.
+config TPL_OF_LIBFDT + bool "Enable the FDT library for TPL" + default y if TPL_OF_CONTROL + help + This enables the FDT library (libfdt). It provides functions for + accessing binary device tree images in memory, such as adding and + removing nodes and properties, scanning through the tree and finding + particular compatible nodes. The library operates on a flattened + version of the device tree. + config FDT_FIXUP_PARTITIONS bool "overwrite MTD partitions in DTS through defined in 'mtdparts'" depends on OF_LIBFDT
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
TPL may need use libfdt for dt decode, add option for it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
lib/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
TPL may need use libfdt for dt decode, add option for it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
lib/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
TPL may need use libfdt for dt decode, add option for it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
lib/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf4782c..3404af7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -228,6 +228,17 @@ config SPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC.
+config TPL_SYS_THUMB_BUILD + bool "Build TPL using the Thumb instruction set" + default y if SYS_THUMB_BUILD + depends on TPL && !ARM64 + help + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. + + config SYS_L2CACHE_OFF bool "L2cache off" help @@ -264,6 +275,15 @@ config SPL_USE_ARCH_MEMCPY Such implementation may be faster under some conditions but may increase the binary size.
+config TPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for TPL" + default y if USE_ARCH_MEMCPY + depends on !ARM64 + help + Enable the generation of an optimized version of memcpy. + Such implementation may be faster under some conditions + but may increase the binary size. + config USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset" default y @@ -282,6 +302,15 @@ config SPL_USE_ARCH_MEMSET Such implementation may be faster under some conditions but may increase the binary size.
+config TPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for TPL" + default y if USE_ARCH_MEMSET + depends on !ARM64 + help + Enable the generation of an optimized version of memset. + Such implementation may be faster under some conditions + but may increase the binary size. + config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" default y if ARM64 && !TARGET_THUNDERX_88XX
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index fa81317..3c1c603 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -70,7 +70,9 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) + ldr r0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 66 ++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 81 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 +++++ include/configs/rk322x_common.h | 12 +++-- 6 files changed, 128 insertions(+), 56 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d9b25d5..e1bc947 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -32,9 +32,18 @@ config ROCKCHIP_RK322X bool "Support Rockchip RK3228/RK3229" select CPU_V7 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_DRIVERS_MISC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT select ROCKCHIP_BROM_HELPER select DEBUG_UART_BOARD_INIT + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 79e9704..5ef0938 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -13,10 +13,11 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 4ddb8ba..71e641e 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -5,77 +5,43 @@ */
#include <common.h> -#include <debug_uart.h> #include <dm.h> -#include <ram.h> #include <spl.h> -#include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> + +DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } -DECLARE_GLOBAL_DATA_PTR; - -#define GRF_BASE 0x11000000 -#define SGRF_BASE 0x10140000
-#define DEBUG_UART_BASE 0x11030000 +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +}
void board_debug_uart_init(void) { -static struct rk322x_grf * const grf = (void *)GRF_BASE; - /* Enable early UART2 channel 1 on the RK322x */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); }
-#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { - struct udevice *dev; int ret;
- /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("SPL Init"); - ret = spl_early_init(); if (ret) { - debug("spl_early_init() failed: %d\n", ret); + printf("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); +}
- rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name);
- /* Disable the ddr secure region setting to make it non-secure */ - rk_clrreg(SGRF_DDR_CON0, 0x4000); -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(); -#endif + return 0; } +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c new file mode 100644 index 0000000..5277dd6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/grf_rk322x.h> +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x11000000 +#define SGRF_BASE 0x10140000 + +#define DEBUG_UART_BASE 0x11030000 + +void board_debug_uart_init(void) +{ +static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} + +#define SGRF_DDR_CON0 0x10150000 +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("TPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + printf("timer init done\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) + back_to_bootrom(); +#endif +} diff --git a/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds new file mode 100644 index 0000000..841c803 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2017 Rockchip Electronic Co.,Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../../cpu/u-boot-spl.lds" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 7630bc5..ba207d6 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -22,11 +22,13 @@
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_TEXT_BASE 0x60000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 -#define CONFIG_SPL_STACK 0x10088000 -#define CONFIG_SPL_TEXT_BASE 0x10081004 +#define CONFIG_SYS_TEXT_BASE 0x61000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +#define CONFIG_SYS_LOAD_ADDR 0x61800800 +#define CONFIG_SPL_TEXT_BASE 0x60000000 + +#define CONFIG_TPL_STACK 0x10088000 +#define CONFIG_TPL_TEXT_BASE 0x10081004
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 66 ++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 81 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 +++++ include/configs/rk322x_common.h | 12 +++-- 6 files changed, 128 insertions(+), 56 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds
Reviewed-by: Simon Glass sjg@chromium.org
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 66 ++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 81 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 +++++ include/configs/rk322x_common.h | 12 +++-- 6 files changed, 128 insertions(+), 56 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 66 ++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 81 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 +++++ include/configs/rk322x_common.h | 12 +++-- 6 files changed, 128 insertions(+), 56 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index a6d48e8..a61a7d3 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -13,6 +13,24 @@ config SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called.
+config SPL_SYSRESET + bool "Enable support for system reset drivers in SPL mode" + depends on SYSRESET && SPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + +config TPL_SYSRESET + bool "Enable support for system reset drivers in TPL mode" + depends on SYSRESET && TPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + if SYSRESET
config SYSRESET_PSCI diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 476d361..ce161a7 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-$(CONFIG_SYSRESET) += sysreset-uclass.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
+Tom,
Hi Philipp,
I think this patch is also need to fix the do_reset missing issue in new release
when you apply below patch, sorry for not make it clear.
http://patchwork.ozlabs.org/patch/811306/
Thanks,
- Kever
On 09/11/2017 02:17 PM, Simon Glass wrote:
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
OP-TEE is an open source trusted OS, in armv7, its loading and running are like this: loading: - SPL load both OP-TEE and U-Boot running: - SPL run into OP-TEE in secure mode; - OP-TEE run into U-Boot in non-secure mode;
More detail: https://github.com/OP-TEE/optee_os and search for 'boot arguments' for detail entry parameter in: core/arch/arm/kernel/generic_entry_a32.S
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
common/spl/Kconfig | 7 +++++++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_optee.S | 13 +++++++++++++ include/spl.h | 9 +++++++++ 5 files changed, 35 insertions(+) create mode 100644 common/spl/spl_optee.S
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 582b685..85f8d66 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -700,6 +700,13 @@ config SPL_ATF_TEXT_BASE help This is the base address in memory for ATF BL31 text and entry point.
+config SPL_OPTEE_SUPPORT + bool "Support OP-TEE Trusted OS" + depends on ARM + help + OP-TEE is an open source Trusted OS which is loaded by SPL. + More detail at: https://github.com/OP-TEE/optee_os + config TPL bool depends on SUPPORT_TPL diff --git a/common/spl/Makefile b/common/spl/Makefile index fde0d09..ec37428 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o +obj-$(CONFIG_$(SPL_TPL_)OPTEE_SUPPORT) += spl_optee.o obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..6ff390c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -430,6 +430,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) bl31_entry(); }
+ if (CONFIG_IS_ENABLED(OPTEE_SUPPORT)) { + debug("loaded - jumping to U-Boot via OP-TEE.\n"); + spl_optee_entry(0, 0, 0, (void *)spl_image.entry_point); + } + debug("loaded - jumping to U-Boot...\n"); #ifdef CONFIG_BOOTSTAGE_STASH int ret; diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S new file mode 100644 index 0000000..4f7f8ba --- /dev/null +++ b/common/spl/spl_optee.S @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2017 Rockchip Electronic Co.,Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +ENTRY(spl_optee_entry) + ldr lr, =CONFIG_SYS_TEXT_BASE + mov pc, r3 +ENDPROC(spl_optee_entry) diff --git a/include/spl.h b/include/spl.h index ce4cf0a..13d46ed 100644 --- a/include/spl.h +++ b/include/spl.h @@ -270,6 +270,15 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, void bl31_entry(void);
/** + * spl_optee_entry - entry function for optee + * entry arg0, pagestore + * entry arg1, (ARMv7 standard bootarg #1) + * entry arg2, device tree address, (ARMv7 standard bootarg #2) + * entry arg3, non-secure entry address (ARMv7 bootarg #0) + */ +void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); + +/** * board_return_to_bootrom - allow for boards to continue with the boot ROM * * If a board (e.g. the Rockchip RK3368 boards) provide some
Hi,
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
OP-TEE is an open source trusted OS, in armv7, its loading and running are like this: loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;
More detail: https://github.com/OP-TEE/optee_os and search for 'boot arguments' for detail entry parameter in: core/arch/arm/kernel/generic_entry_a32.S
Signed-off-by: Kever Yang kever.yang@rock-chips.com
common/spl/Kconfig | 7 +++++++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_optee.S | 13 +++++++++++++ include/spl.h | 9 +++++++++ 5 files changed, 35 insertions(+) create mode 100644 common/spl/spl_optee.S
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 582b685..85f8d66 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -700,6 +700,13 @@ config SPL_ATF_TEXT_BASE help This is the base address in memory for ATF BL31 text and entry point.
+config SPL_OPTEE_SUPPORT
Can you drop the _SUPPORT
bool "Support OP-TEE Trusted OS"depends on ARMhelpOP-TEE is an open source Trusted OS which is loaded by SPL.More detail at: https://github.com/OP-TEE/optee_osconfig TPL bool depends on SUPPORT_TPL diff --git a/common/spl/Makefile b/common/spl/Makefile index fde0d09..ec37428 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o +obj-$(CONFIG_$(SPL_TPL_)OPTEE_SUPPORT) += spl_optee.o obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..6ff390c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -430,6 +430,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) bl31_entry(); }
if (CONFIG_IS_ENABLED(OPTEE_SUPPORT)) {debug("loaded - jumping to U-Boot via OP-TEE.\n");spl_optee_entry(0, 0, 0, (void *)spl_image.entry_point);}debug("loaded - jumping to U-Boot...\n");#ifdef CONFIG_BOOTSTAGE_STASH int ret; diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S new file mode 100644 index 0000000..4f7f8ba --- /dev/null +++ b/common/spl/spl_optee.S @@ -0,0 +1,13 @@ +/*
- Copyright (C) 2017 Rockchip Electronic Co.,Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <linux/linkage.h> +#include <asm/assembler.h>
+ENTRY(spl_optee_entry)
ldr lr, =CONFIG_SYS_TEXT_BASEmov pc, r3
This is ARM code so should go in arch/arm I think
+ENDPROC(spl_optee_entry) diff --git a/include/spl.h b/include/spl.h index ce4cf0a..13d46ed 100644 --- a/include/spl.h +++ b/include/spl.h @@ -270,6 +270,15 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, void bl31_entry(void);
/**
- spl_optee_entry - entry function for optee
- entry arg0, pagestore
What does this mean? What exactly needs to be there?
- entry arg1, (ARMv7 standard bootarg #1)
- entry arg2, device tree address, (ARMv7 standard bootarg #2)
- entry arg3, non-secure entry address (ARMv7 bootarg #0)
- */
+void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+/**
- board_return_to_bootrom - allow for boards to continue with the boot ROM
- If a board (e.g. the Rockchip RK3368 boards) provide some
-- 1.9.1
Regards, Simon
OP-TEE is an open source trusted OS, in armv7, its loading and running are like this: loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;
More detail: https://github.com/OP-TEE/optee_os and search for 'boot arguments' for detail entry parameter in: core/arch/arm/kernel/generic_entry_a32.S
Signed-off-by: Kever Yang kever.yang@rock-chips.com
common/spl/Kconfig | 7 +++++++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_optee.S | 13 +++++++++++++ include/spl.h | 9 +++++++++ 5 files changed, 35 insertions(+) create mode 100644 common/spl/spl_optee.S
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Wed, 6 Sep 2017, Kever Yang wrote:
OP-TEE is an open source trusted OS, in armv7, its loading and running are like this: loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;
More detail: https://github.com/OP-TEE/optee_os and search for 'boot arguments' for detail entry parameter in: core/arch/arm/kernel/generic_entry_a32.S
Adding some documentation to U-Boot that documents the binary interface with OPTEE would be helpful.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
common/spl/Kconfig | 7 +++++++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_optee.S | 13 +++++++++++++ include/spl.h | 9 +++++++++ 5 files changed, 35 insertions(+) create mode 100644 common/spl/spl_optee.S
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 582b685..85f8d66 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -700,6 +700,13 @@ config SPL_ATF_TEXT_BASE help This is the base address in memory for ATF BL31 text and entry point.
+config SPL_OPTEE_SUPPORT
- bool "Support OP-TEE Trusted OS"
- depends on ARM
- help
OP-TEE is an open source Trusted OS which is loaded by SPL.More detail at: https://github.com/OP-TEE/optee_osconfig TPL bool depends on SUPPORT_TPL diff --git a/common/spl/Makefile b/common/spl/Makefile index fde0d09..ec37428 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o +obj-$(CONFIG_$(SPL_TPL_)OPTEE_SUPPORT) += spl_optee.o obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index d245cfc..6ff390c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -430,6 +430,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) bl31_entry(); }
- if (CONFIG_IS_ENABLED(OPTEE_SUPPORT)) {
debug("loaded - jumping to U-Boot via OP-TEE.\n");spl_optee_entry(0, 0, 0, (void *)spl_image.entry_point);- }
Shouldn't the fact that we will boot through the OPTEE tracked through spl_image->os and shouldn't there be a IH_OS_... constant that indicates that we are going to jump to an OPTEE? This would allow the above switch statement to be extended for OPTEE.
debug("loaded - jumping to U-Boot...\n"); #ifdef CONFIG_BOOTSTAGE_STASH int ret; diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S new file mode 100644 index 0000000..4f7f8ba --- /dev/null +++ b/common/spl/spl_optee.S @@ -0,0 +1,13 @@ +/*
- Copyright (C) 2017 Rockchip Electronic Co.,Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <linux/linkage.h> +#include <asm/assembler.h>
+ENTRY(spl_optee_entry)
- ldr lr, =CONFIG_SYS_TEXT_BASE
- mov pc, r3
+ENDPROC(spl_optee_entry)
This looks ARM-specific and shouldn't be in common/spl.
Please note that the next OS image will not always be a CONFIG_SYS_TEXT_BASE. So the address of the "next image to boot" should be an argument to this function (we will need to solve this cleanly anyway, as I am currently trying to address the same issue with booting through ATF where I have an entry address into the ATF and need to keep track of the next image's entry address as well).
diff --git a/include/spl.h b/include/spl.h index ce4cf0a..13d46ed 100644 --- a/include/spl.h +++ b/include/spl.h @@ -270,6 +270,15 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, void bl31_entry(void);
/**
- spl_optee_entry - entry function for optee
- entry arg0, pagestore
- entry arg1, (ARMv7 standard bootarg #1)
- entry arg2, device tree address, (ARMv7 standard bootarg #2)
- entry arg3, non-secure entry address (ARMv7 bootarg #0)
- */
+void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+/**
- board_return_to_bootrom - allow for boards to continue with the boot ROM
- If a board (e.g. the Rockchip RK3368 boards) provide some
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ae0b0a4..fe4abe9 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -83,6 +83,7 @@ };
&uart2 { + u-boot,dm-pre-reloc; status = "okay"; };
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
board/rockchip/evb_rk3229/fit_spl_optee.its | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 board/rockchip/evb_rk3229/fit_spl_optee.its
diff --git a/board/rockchip/evb_rk3229/fit_spl_optee.its b/board/rockchip/evb_rk3229/fit_spl_optee.its new file mode 100644 index 0000000..ed93d44 --- /dev/null +++ b/board/rockchip/evb_rk3229/fit_spl_optee.its @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 Rockchip Electronic Co.,Ltd + * + * Simple U-boot fit source file containing U-Boot, dtb and optee + */ + +/dts-v1/; + +/ { + description = "Simple image with OP-TEE support"; + #address-cells = <1>; + + images { + uboot@1 { + description = "U-Boot"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm"; + compression = "none"; + load = <0x61000000>; + }; + optee@1 { + description = "ARM Trusted Firmware"; + data = /incbin/("../../../tee.bin"); + type = "firmware"; + arch = "arm"; + compression = "none"; + load = <0x68400000>; + entry = <0x68400000>; + }; + fdt@1 { + description = "rk3229 dtb"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; + }; + + configurations { + default = "conf@1"; + conf@1 { + description = "RK3399 evb"; + firmware = "uboot@1"; + loadables = "optee@1"; + fdt = "fdt@1"; + }; + }; +};
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
board/rockchip/evb_rk3229/fit_spl_optee.its | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 board/rockchip/evb_rk3229/fit_spl_optee.its
diff --git a/board/rockchip/evb_rk3229/fit_spl_optee.its b/board/rockchip/evb_rk3229/fit_spl_optee.its new file mode 100644 index 0000000..ed93d44 --- /dev/null +++ b/board/rockchip/evb_rk3229/fit_spl_optee.its @@ -0,0 +1,48 @@ +/*
- Copyright (C) 2017 Rockchip Electronic Co.,Ltd
- Simple U-boot fit source file containing U-Boot, dtb and optee
U-Boot
otherwise:
Reviewed-by: Simon Glass sjg@chromium.org
- */
+/dts-v1/;
+/ {
description = "Simple image with OP-TEE support";#address-cells = <1>;images {uboot@1 {description = "U-Boot";data = /incbin/("../../../u-boot-nodtb.bin");type = "standalone";arch = "arm";compression = "none";load = <0x61000000>;};optee@1 {description = "ARM Trusted Firmware";data = /incbin/("../../../tee.bin");type = "firmware";arch = "arm";compression = "none";load = <0x68400000>;entry = <0x68400000>;};fdt@1 {description = "rk3229 dtb";data = /incbin/("../../../u-boot.dtb");type = "flat_dt";compression = "none";};};configurations {default = "conf@1";conf@1 {description = "RK3399 evb";firmware = "uboot@1";loadables = "optee@1";fdt = "fdt@1";};};+};
1.9.1
We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
board/rockchip/evb_rk3229/fit_spl_optee.its | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 board/rockchip/evb_rk3229/fit_spl_optee.its
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
board/rockchip/evb_rk3229/fit_spl_optee.its | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 board/rockchip/evb_rk3229/fit_spl_optee.its
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Detail of step by step to bring up the board with OP-TEE support.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
board/rockchip/evb_rk3229/README | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 board/rockchip/evb_rk3229/README
diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README new file mode 100644 index 0000000..93328c7 --- /dev/null +++ b/board/rockchip/evb_rk3229/README @@ -0,0 +1,72 @@ +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3229 + > cd ~/evb_rk3229 + > git clone git://git.denx.de/u-boot.git + > git clone https://github.com/OP-TEE/optee_os.git + > git clone https://github.com/rockchip-linux/rkbin.git + > git clone https://github.com/rockchip-linux/rkdeveloptool.git + +Compile the OP-TEE +=============== + + > cd optee_os + > make clean + > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + +Compile the U-Boot +================== + + > cd ../u-boot + > export CROSS_COMPILE=arm-linux-gnueabihf- + > export ARCH=arm + > make evb-rk3229_defconfig + > make + > make u-boot.itb + + Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + +Compile the rkdeveloptool +======================= + Follow instructions in latest README + > cd ../rkflashtool + > autoreconf -i + > ./configure + > make + > sudo make install + + Get rkdeveloptool in you Host in this step. + +Both origin binaries and Tool are ready now, choose either option 1 or +option 2 to deploy U-Boot. + +Package the image +================= + + > cd ../u-boot + > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img + > cat spl/u-boot-spl.bin >> idbloader.img + + Get idbloader.img in this step. + +Flash the image to eMMC +======================= +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > cd .. + > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool wl 64 u-boot/idbloader.img + > rkdeveloptool wl 0x4000 u-boot/u-boot.itb + > rkdeveloptool rd + +Flash the image to SD card +========================== + > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 + > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + +You should be able to get U-Boot log message with OP-TEE boot info. + +For more detail, please reference to: +http://opensource.rock-chips.com/wiki_Boot_option
Hi Kever,
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
Detail of step by step to bring up the board with OP-TEE support.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
board/rockchip/evb_rk3229/README | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 board/rockchip/evb_rk3229/README
diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README new file mode 100644 index 0000000..93328c7 --- /dev/null +++ b/board/rockchip/evb_rk3229/README @@ -0,0 +1,72 @@
Can you add an overall header at the top of the file?
- what is OP-TEE - what is the point of all this - what pieces are needed - what the tools are for (rkdeveloptool, rkbin)
nit: I think it is better to use============= for the top header and -------------- for the subheaders (which are below)
+Get the Source and prebuild binary +==================================
+Compile the OP-TEE +===============
- Get tee.bin in this step, copy it to U-Boot root dir:
+Compile the U-Boot
Build U-Boot
(since it compiles but also does other steps)
+==================
- Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
+Compile the rkdeveloptool +=======================
- Follow instructions in latest README
- Get rkdeveloptool in you Host in this step.
How about: Install rkdeveloptool on your host as follows
(above you could put that at the top of this section)
+Both origin binaries and Tool are ready now, choose either option 1 or +option 2 to deploy U-Boot.
Where are the two options. If they are below, please number them 1 and 2.
+Package the image +=================
- Get idbloader.img in this step.
Put at top under 'Package the image'
+Flash the image to eMMC +======================= +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+Flash the image to SD card +==========================
+You should be able to get U-Boot log message with OP-TEE boot info.
s/log/console/
Can you please add an example console message here?
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
1.9.1
Regards, Simon
Detail of step by step to bring up the board with OP-TEE support.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
board/rockchip/evb_rk3229/README | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 board/rockchip/evb_rk3229/README
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Enable all the options for TPL/SPL and OPTEE.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
configs/evb-rk3229_defconfig | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index bf5baf5..2fe2061 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -4,15 +4,27 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ROCKCHIP_RK322X=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds" +CONFIG_TPL_TEXT_BASE=0x10081004 +CONFIG_TPL_MAX_SIZE=28672 +CONFIG_TPL_STACK=0x10088000 +CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TARGET_EVB_RK3229=y -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x60600000 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" CONFIG_DEBUG_UART=y -CONFIG_ENV_IS_IN_MMC=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3229/fit_spl_optee.its" # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x4000 +CONFIG_SPL_OPTEE_SUPPORT=y CONFIG_FASTBOOT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_CMD_FASTBOOT=y @@ -29,13 +41,19 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_TPL_DM=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -44,12 +62,14 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y
On 5 September 2017 at 20:14, Kever Yang kever.yang@rock-chips.com wrote:
Enable all the options for TPL/SPL and OPTEE.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
configs/evb-rk3229_defconfig | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Enable all the options for TPL/SPL and OPTEE.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org
configs/evb-rk3229_defconfig | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Enable all the options for TPL/SPL and OPTEE.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
configs/evb-rk3229_defconfig | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
On 11/20/2017 03:25 PM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
make clean; git clean -fx..; then try again
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
I've been here plenty of times when brining up OP-TEE on TI platforms, for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure about the Rockchip arch, are the extra cores brought up with PSCI? Anyway can you get JTAG on this device, see where the other cores are stuck.
在 2017/11/21 23:43, Andrew F. Davis 写道:
On 11/20/2017 03:25 PM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
make clean; git clean -fx..; then try again
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
I've been here plenty of times when brining up OP-TEE on TI platforms, for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure about the Rockchip arch, are the extra cores brought up with PSCI? Anyway can you get JTAG on this device, see where the other cores are stuck.
If your OP-TEE is from Tony Xie's repository, I think the reason maybe that cntfrq register is not been initialized. core0 stucks at udelay() in the OP-TEE when it tries to bring up core1. So can you try to initialize cntfrq as 24000000 in the SPL/TPL ? maybe it helps.
Am Mittwoch, 22. November 2017, 17:10:19 CET schrieb Joseph Chen:
在 2017/11/21 23:43, Andrew F. Davis 写道:
On 11/20/2017 03:25 PM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
make clean; git clean -fx..; then try again
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
I've been here plenty of times when brining up OP-TEE on TI platforms, for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure about the Rockchip arch, are the extra cores brought up with PSCI? Anyway can you get JTAG on this device, see where the other cores are stuck.
If your OP-TEE is from Tony Xie's repository, I think the reason maybe that cntfrq register is not been initialized. core0 stucks at udelay() in the OP-TEE when it tries to bring up core1. So can you try to initialize cntfrq as 24000000 in the SPL/TPL ? maybe it helps.
That might be a good lead, as yesterday evening I noticed similar issues with the architected timer when starting the linux kernel, which hangs at some point and only manages to continue once I disable the arch-timer in the devicetree.
I tried Tony's repository directly and also the official op-tee where his patches got merged to.
Am Dienstag, 21. November 2017, 09:43:57 CET schrieb Andrew F. Davis:
On 11/20/2017 03:25 PM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
make clean; git clean -fx..; then try again
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
I've been here plenty of times when brining up OP-TEE on TI platforms, for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure about the Rockchip arch, are the extra cores brought up with PSCI?
Yep, the rk3229 is the first 32bit Rockchip soc using PSCI (implemented in OP-TEE). As Joseph indicated in the other mail, it might be a timer-issue after all.
Anyway can you get JTAG on this device, see where the other cores are stuck.
There is no easy JTAG on TV box I'm using right now, as there exists no real widely available dev-board for the rk3229 right now.
So I'm still hoping for some insights from Kever though ;-)
Heiko,
I test with Rockchip op-tee from rkbin and it works fine, let me test with
upstream op-tee again and get back to you.
Thanks, - Kever On 11/22/2017 06:00 PM, Heiko Stuebner wrote:
Am Dienstag, 21. November 2017, 09:43:57 CET schrieb Andrew F. Davis:
On 11/20/2017 03:25 PM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1]. When compiling the most-recent optee it fails with [2].
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
make clean; git clean -fx..; then try again
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
I've been here plenty of times when brining up OP-TEE on TI platforms, for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure about the Rockchip arch, are the extra cores brought up with PSCI?
Yep, the rk3229 is the first 32bit Rockchip soc using PSCI (implemented in OP-TEE). As Joseph indicated in the other mail, it might be a timer-issue after all.
Anyway can you get JTAG on this device, see where the other cores are stuck.
There is no easy JTAG on TV box I'm using right now, as there exists no real widely available dev-board for the rk3229 right now.
So I'm still hoping for some insights from Kever though ;-)
Heiko,
On 11/21/2017 05:25 AM, Heiko Stübner wrote:
Hi Kever,
Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:
Add some generic options for TPL support for arm 32bit, and then and TPL support for rk3229(cortex-A7), and then add OPTEE support in SPL.
I was now finally able to test this series and I'm getting mixed results. I was following the instructions in the evb-rk3229 README file.
On the uboot side it seems to work nicely when applied against 2017.09.
But when I try to rebase it on top of the next branch of u-boot-rockchip I end up with the TPL claiming a "Missing DTB", so it looks like it needs a respin to follow the recent changes.
On the optee-side I also seem to do something wrong or so. When using the binaries from the rkbin github repository I end up with [0] and [1].
the U-Boot proper update the text_base to 0x61000000 instead of 0x60000000, but I guess the optee rkbin using fixed 0x60000000;
When compiling the most-recent optee it fails with [2].
I met the same problem, remove the 'out' folder and make again, it will success.
With some intermediate optee or the one from Tony Xie's repository it compiles and uboot seems to start, but then fails when the kernel tries to bring up the secondary cpus [3]. And interestingly while it seems to go through optee, I don't see any optee-messages.
If you could point me into the right direction, I would be very grateful :-)
Thanks Heiko
[0] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm) INF TEE-CORE:init_primary_helper:320: Release version: 1.9 INF TEE-CORE:init_teecore:79: teecore inits done [hangs here]
[1] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1 INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm) INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6 INF [0x0] TEE-CORE:init_teecore:83: teecore inits done [hangs here]
[2] make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x CHK out/arm-plat-rockchip/conf.mk UPD out/arm-plat-rockchip/conf.mk CHK out/arm-plat-rockchip/include/generated/conf.h UPD out/arm-plat-rockchip/include/generated/conf.h CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.
[3] TPL Inittimer init done Returning to boot ROM...
U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42) Trying to boot from MMC1
U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)
Model: Nexbox A95X R1 DRAM: 1022 MiB [...] Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1 [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '') [ 0.000000] bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x9c000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] random: fast init done [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096 [...] [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0 [ 0.000000] Hierarchical SRCU implementation. [ 0.000000] EFI services will not be available. [ 0.000000] smp: Bringing up secondary CPUs ... [hangs here]
participants (7)
-
Andrew F. Davis -
Heiko Stuebner -
Heiko Stübner
-
Joseph Chen -
Kever Yang -
Philipp Tomsich -
Simon Glass