[U-Boot] [PATCH v3 1/4] ftahbc020s: Faraday FTAHBC020s AHB Bus Controller
ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- Changes for v1-v3: No Change.
include/faraday/ftahbc020s.h | 94 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 include/faraday/ftahbc020s.h
diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h new file mode 100644 index 0000000..da85582 --- /dev/null +++ b/include/faraday/ftahbc020s.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ +#ifndef __FTAHBC020S_H +#define __FTAHBC202S_H + +/* Registers Offsets */ + +/* + * AHB Slave BSR, n * 4, n=0~31 + */ +#ifdef __ASSEMBLY__ +/* this section is used by lowlevel_init.S */ +#define FTAHBC020S_SLAVE_BSR_0 0x00 /* Slave n Base/Size Reg */ +#define FTAHBC020S_SLAVE_BSR_1 0x04 +#define FTAHBC020S_SLAVE_BSR_2 0x08 +#define FTAHBC020S_SLAVE_BSR_3 0x0C +#define FTAHBC020S_SLAVE_BSR_4 0x10 +#define FTAHBC020S_SLAVE_BSR_5 0x14 +#define FTAHBC020S_SLAVE_BSR_6 0x18 +#define FTAHBC020S_SLAVE_BSR_7 0x1C +#define FTAHBC020S_SLAVE_BSR_8 0x20 +#define FTAHBC020S_SLAVE_BSR_9 0x24 +#define FTAHBC020S_SLAVE_BSR_10 0x28 + +#define FTAHBC020S_PCR 0x80 /* Priority Ctrl Reg */ +#define FTAHBC020S_TCRG 0x84 /* Transfer Ctrl Reg */ +#define FTAHBC020S_CR 0x88 /* Ctrl Reg */ +#endif /* __ASSEMBLY__ */ + +/* + * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register + */ +#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xFFF) << 20) +#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xF) << 16) + +#define FTAHBC020S_SLAVE_BSR_SIZE_1M 0x0 +#define FTAHBC020S_SLAVE_BSR_SIZE_2M 0x1 +#define FTAHBC020S_SLAVE_BSR_SIZE_4M 0x2 +#define FTAHBC020S_SLAVE_BSR_SIZE_8M 0x3 +#define FTAHBC020S_SLAVE_BSR_SIZE_16M 0x4 +#define FTAHBC020S_SLAVE_BSR_SIZE_32M 0x5 +#define FTAHBC020S_SLAVE_BSR_SIZE_64M 0x6 +#define FTAHBC020S_SLAVE_BSR_SIZE_128M 0x7 +#define FTAHBC020S_SLAVE_BSR_SIZE_256M 0x8 +#define FTAHBC020S_SLAVE_BSR_SIZE_512M 0x9 +#define FTAHBC020S_SLAVE_BSR_SIZE_1G 0xA +#define FTAHBC020S_SLAVE_BSR_SIZE_2G 0xB + +/* + * FTAHBC020S_PCR - Priority Control Register + */ +#define FTAHBC020S_PCR_PLEVEL_15 (1 << 15) +#define FTAHBC020S_PCR_PLEVEL_14 (1 << 14) +#define FTAHBC020S_PCR_PLEVEL_13 (1 << 13) +#define FTAHBC020S_PCR_PLEVEL_12 (1 << 12) +#define FTAHBC020S_PCR_PLEVEL_11 (1 << 11) +#define FTAHBC020S_PCR_PLEVEL_10 (1 << 10) +#define FTAHBC020S_PCR_PLEVEL_09 (1 << 9) +#define FTAHBC020S_PCR_PLEVEL_08 (1 << 8) +#define FTAHBC020S_PCR_PLEVEL_07 (1 << 7) +#define FTAHBC020S_PCR_PLEVEL_06 (1 << 6) +#define FTAHBC020S_PCR_PLEVEL_05 (1 << 5) +#define FTAHBC020S_PCR_PLEVEL_04 (1 << 4) +#define FTAHBC020S_PCR_PLEVEL_03 (1 << 3) +#define FTAHBC020S_PCR_PLEVEL_02 (1 << 2) +#define FTAHBC020S_PCR_PLEVEL_01 (1 << 1) + +/* + * FTAHBC020S_CR - Interrupt Control Register + */ +#define FTAHBC020S_CR_INTSTS (1 << 24) +#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) +#define FTAHBC020S_CR_INTSMASK (1 << 16) +#define FTAHBC020S_CR_REMAP (1 << 0) + +#endif /* __FTAHBC020S_H */
Support registers definitions of ftsdmc021 SDRAM controller.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- Changes for v1-v3: No Change.
include/faraday/ftsdmc021.h | 154 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 154 insertions(+), 0 deletions(-) create mode 100644 include/faraday/ftsdmc021.h
diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h new file mode 100644 index 0000000..3ed535a --- /dev/null +++ b/include/faraday/ftsdmc021.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang ratbert@faraday-tech.com + * + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * FTSDMC021 - SDRAM Controller + */ +#ifndef __FTSDMC021_H +#define __FTSDMC021_H + +#ifdef __ASSEMBLY__ +#define FTSDMC021_OFFSET_TP1 0x00 /* SDRAM Timing Parameter 1 */ +#define FTSDMC021_OFFSET_TP2 0x04 /* SDRAM Timing Parameter 2 */ +#define FTSDMC021_OFFSET_CR1 0x08 /* SDRAM Configuration Reg 1 */ +#define FTSDMC021_OFFSET_CR2 0x0C /* SDRAM Configuration Reg 2 */ +#define FTSDMC021_OFFSET_BANK0_BSR 0x10 /* External Bank Base/Size Reg 0 */ +#define FTSDMC021_OFFSET_BANK1_BSR 0x14 /* External Bank Base/Size Reg 1 */ +#define FTSDMC021_OFFSET_BANK2_BSR 0x18 /* External Bank Base/Size Reg 2 */ +#define FTSDMC021_OFFSET_BANK3_BSR 0x1C /* External Bank Base/Size Reg 3 */ +#define FTSDMC021_OFFSET_BANK4_BSR 0x20 /* External Bank Base/Size Reg 4 */ +#define FTSDMC021_OFFSET_BANK5_BSR 0x24 /* External Bank Base/Size Reg 5 */ +#define FTSDMC021_OFFSET_BANK6_BSR 0x28 /* External Bank Base/Size Reg 6 */ +#define FTSDMC021_OFFSET_BANK7_BSR 0x2C /* External Bank Base/Size Reg 7 */ +#define FTSDMC021_OFFSET_RAGR 0x30 /* Read Arbitration Group Reg */ +#define FTSDMC021_OFFSET_FRR 0x34 /* Flush Request Register */ +#define FTSDMC021_OFFSET_EBISR 0x38 /* EBI Support Register */ +#define FTSDMC021_OFFSET_CRR 0x100 /* Controller Revision Reg */ +#define FTSDMC021_OFFSET_CFR 0x104 /* Controller Feature Reg */ +#endif /* __ASSEMBLY__ */ + +/* + * Timing Parameter 1 Register + */ +#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) +#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parameter 2 Register + */ +#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register 1 + */ +#define FTSDMC021_CR1_BNKSIZEF(x) ((x) & 0xf) +#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) +#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) +#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) +#define FTSDMC021_CR1_MA2T(x) (1 << 16) /* Double Memory Address Cycle Enable */ + +/* + * Configuration Register 2 + */ +#define FTSDMC021_CR2_SREF (1 << 0) +#define FTSDMC021_CR2_PWDN (1 << 1) +#define FTSDMC021_CR2_ISMR (1 << 2) +#define FTSDMC021_CR2_IREF (1 << 3) +#define FTSDMC021_CR2_IPREC (1 << 4) +#define FTSDMC021_CR2_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC021_BANK_ENABLE (1 << 12) + +/* 12-bit base address of external bank. + * Default value is 0x800. + * The 12-bit equals to the haddr[31:20] of AHB address bus. */ +#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) + +#define FTSDMC021_BANK_SIZE_1M 0x0 +#define FTSDMC021_BANK_SIZE_2M 0x1 +#define FTSDMC021_BANK_SIZE_4M 0x2 +#define FTSDMC021_BANK_SIZE_8M 0x3 +#define FTSDMC021_BANK_SIZE_16M 0x4 +#define FTSDMC021_BANK_SIZE_32M 0x5 +#define FTSDMC021_BANK_SIZE_64M 0x6 +#define FTSDMC021_BANK_SIZE_128M 0x7 +#define FTSDMC021_BANK_SIZE_256M 0x8 +#define FTSDMC021_BANK_SIZE_512M 0x9 + +/* + * Read Arbitration Grant Window Register + */ +#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) +#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) +#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) +#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) +#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) +#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) +#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) +#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) + +/* + * Flush Request Register + */ +#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) +#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) + +/* + * External Bus Interface Support Register (EBISR) + */ +#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) +#define FTSDMC021_EBISR_PRSMR (1 << 12) +#define FTSDMC021_EBISR_POPREC (1 << 13) +#define FTSDMC021_EBISR_POSMR (1 << 14) + +/* + * Controller Revision Register (CRR, Read Only) + */ +#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) +#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) +#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) + +/* + * Controller Feature Register (CFR, Read Only) + */ +#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) +#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) +#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) +#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) +#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) +#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) +#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) +#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) +#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) +#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) +#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) + +#endif /* __FTSDMC021_H */
Le 16/04/2011 09:37, Macpaul Lin a écrit :
Support registers definitions of ftsdmc021 SDRAM controller.
Signed-off-by: Macpaul Linmacpaul@andestech.com
Changes for v1-v3: No Change.
include/faraday/ftsdmc021.h | 154 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 154 insertions(+), 0 deletions(-) create mode 100644 include/faraday/ftsdmc021.h
Hi MacPaul,
As previously discussed, NAK: header file addition is dead code.
Amicalement,
Move the header file "ftsdmc020.h" (SDRAM Controller) to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020 could share the same header file.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- Changes for v2: - Fix the include path of ftsdmc020 for a320evb. - v1 of this patch /patch/71953/ in patchworks has been marked as superseded. Changes for v3: - format patch by -M option.
board/faraday/a320evb/lowlevel_init.S | 2 +- .../asm/arch-a320 => include/faraday}/ftsdmc020.h | 0 2 files changed, 1 insertions(+), 1 deletions(-) rename {arch/arm/include/asm/arch-a320 => include/faraday}/ftsdmc020.h (100%)
diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S index 97718c0..4262c11 100644 --- a/board/faraday/a320evb/lowlevel_init.S +++ b/board/faraday/a320evb/lowlevel_init.S @@ -21,7 +21,7 @@ #include <version.h>
#include <asm/macro.h> -#include <asm/arch/ftsdmc020.h> +#include <faraday/ftsdmc020.h>
/* * parameters for the SDRAM controller diff --git a/arch/arm/include/asm/arch-a320/ftsdmc020.h b/include/faraday/ftsdmc020.h similarity index 100% rename from arch/arm/include/asm/arch-a320/ftsdmc020.h rename to include/faraday/ftsdmc020.h
Hi MacPaul,
Le 16/04/2011 09:37, Macpaul Lin a écrit :
Move the header file "ftsdmc020.h" (SDRAM Controller) to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020 could share the same header file.
Signed-off-by: Macpaul Linmacpaul@andestech.com
Applied to u-boot-arm/master, thanks.
Amicalement,
Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder.
This change will let other SoC which also use ftsmc020 could share the same header file.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- Changes for v2: - Move the header file of ftsmc020.h to include/faraday. - Fix the include path of ftsmc020 for a320evb. - v1 of this patch /patch/71957/ in patchworks has been marked as superseded.
Changes for V3: - format patch by using -M option.
arch/arm/cpu/arm920t/a320/Makefile | 1 - board/faraday/a320evb/a320evb.c | 2 +- drivers/mtd/Makefile | 1 + .../cpu/arm920t/a320 => drivers/mtd}/ftsmc020.c | 2 +- include/configs/a320evb.h | 4 +++- .../asm/arch-a320 => include/faraday}/ftsmc020.h | 0 6 files changed, 6 insertions(+), 4 deletions(-) rename {arch/arm/cpu/arm920t/a320 => drivers/mtd}/ftsmc020.c (97%) rename {arch/arm/include/asm/arch-a320 => include/faraday}/ftsmc020.h (100%)
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile index 31da706..50eb265 100644 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ b/arch/arm/cpu/arm920t/a320/Makefile @@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).o
SOBJS += reset.o COBJS += timer.o -COBJS += ftsmc020.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index b9343e4..2578be4 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -21,7 +21,7 @@ #include <netdev.h> #include <asm/io.h>
-#include <asm/arch/ftsmc020.h> +#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 999431c..5a5ecdf 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o +COBJS-$(CONFIG_FTSMC020) += ftsmc020.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o COBJS-$(CONFIG_SPEARSMI) += spr_smi.o diff --git a/arch/arm/cpu/arm920t/a320/ftsmc020.c b/drivers/mtd/ftsmc020.c similarity index 97% rename from arch/arm/cpu/arm920t/a320/ftsmc020.c rename to drivers/mtd/ftsmc020.c index 7646537..b027685 100644 --- a/arch/arm/cpu/arm920t/a320/ftsmc020.c +++ b/drivers/mtd/ftsmc020.c @@ -20,7 +20,7 @@ #include <config.h> #include <common.h> #include <asm/io.h> -#include <asm/arch/ftsmc020.h> +#include <faraday/ftsmc020.h>
struct ftsmc020_config { unsigned int config; diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 5373bcb..4b297f0 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -163,7 +163,8 @@ * Static memory controller configuration */
-#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020 +#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ @@ -196,6 +197,7 @@ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } +#endif /* CONFIG_FTSMC020 */
/*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/arch/arm/include/asm/arch-a320/ftsmc020.h b/include/faraday/ftsmc020.h similarity index 100% rename from arch/arm/include/asm/arch-a320/ftsmc020.h rename to include/faraday/ftsmc020.h
Hi MacPaul,
Le 16/04/2011 09:37, Macpaul Lin a écrit :
Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder.
This change will let other SoC which also use ftsmc020 could share the same header file.
Signed-off-by: Macpaul Linmacpaul@andestech.com
Applied to u-boot-arm/master, thanks.
Amicalement,
Hi Macpaul,
On Sat, Apr 16, 2011 at 3:37 PM, Macpaul Lin macpaul@andestech.com wrote:
Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder.
This change will let other SoC which also use ftsmc020 could share the same header file.
Signed-off-by: Macpaul Lin macpaul@andestech.com
This patch makes a320evb failed to build.
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 5373bcb..4b297f0 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -163,7 +163,8 @@ * Static memory controller configuration */
-#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020 +#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ @@ -196,6 +197,7 @@ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } +#endif /* CONFIG_FTSMC020 */
Looks like this #endif is unnecessary?
best regards, Po-Yu Chuang
Hi Po-Yu,
2011/4/28 Po-Yu Chuang ratbert.chuang@gmail.com:
Hi Macpaul,
-#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020 +#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ @@ -196,6 +197,7 @@ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } +#endif /* CONFIG_FTSMC020 */
Looks like this #endif is unnecessary?
best regards, Po-Yu Chuang
At the time the patch has been generated, I could bulid a320evb. I'm not in the office in these 2 days. Could I check it and reply to you later?
According to your reply, I guess I was meant to support #define CONFIG_FTSMC020 in board's config file.
I'll check it later after 10:00 in Taiwan time. Sorry.
Hi Macpaul,
On Thu, Apr 28, 2011 at 3:33 PM, Macpaul Lin macpaul@gmail.com wrote:
Hi Po-Yu,
2011/4/28 Po-Yu Chuang ratbert.chuang@gmail.com:
Hi Macpaul,
-#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020
This is for drivers/mtd/Makefile.
+#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ @@ -196,6 +197,7 @@ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } +#endif /* CONFIG_FTSMC020 */
Looks like this #endif is unnecessary?
At the time the patch has been generated, I could bulid a320evb. I'm not in the office in these 2 days. Could I check it and reply to you later?
According to your reply, I guess I was meant to support #define CONFIG_FTSMC020 in board's config file.
I'll check it later after 10:00 in Taiwan time. Sorry.
After removed the #endif line, it builds again. I will submit a simple patch. Please check it later.
Thanks, :-) Po-Yu Chuang
Hi Po-Yu,
2011/4/28 Po-Yu Chuang ratbert.chuang@gmail.com:
Hi Macpaul,
According to your reply, I guess I was meant to support #define CONFIG_FTSMC020 in board's config file.
I think it might be a problem when I'm clean up about the following redundant code #ifndef CONFIG_FTSMC020 #define CONFIG_FTSMC020 ..... #endif
After removed the #endif line, it builds again. I will submit a simple patch. Please check it later.
Thanks, :-) Po-Yu Chuang
Sorry to make you a problem here. Thanks!
Le 16/04/2011 09:37, Macpaul Lin a écrit :
ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.
Signed-off-by: Macpaul Linmacpaul@andestech.com
Changes for v1-v3: No Change.
include/faraday/ftahbc020s.h | 94 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 include/faraday/ftahbc020s.h
Hi MacPaul,
As previously discussed, NAK: header file addition is dead code.
Amicalement,
participants (4)
-
Albert ARIBAUD -
Macpaul Lin -
Macpaul Lin -
Po-Yu Chuang