Reserved memory for OP-TEE is located at end of DDR for STM32MP1 SoC only (STM32MP13 and STM32MP15) and the OP-TEE reserved memory is located at the beginning of DDR for STM32MP25 SoC, before CONFIG_TEXT_BASE and with reserved memory for companion coprocessor. So the ram_top is limited by OP-TEE reserved memory only for STM32MP1 SoC.

This patch solves an issue for ram_top value on STM32MP25 SoC because the generic reserved memory management, based on LMB, is no more used before relocation.

Fixes: 8242f14a3e6f ("stm32mp: compute ram_top based on the optee base address") Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

arch/arm/mach-stm32mp/dram_init.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 198785353f13..58290105d127 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -62,7 +62,6 @@ int dram_init(void)

phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - int ret; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -75,10 +74,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * if the effective available memory is bigger */ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + + /* add 8M for U-Boot reserved memory: display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);

- ret = optee_get_reserved_memory(&optee_start, &optee_size); - reg = (!ret ? optee_start : gd->ram_top) - size; + reg = gd->ram_top - size; + + /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ + if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { + if (!optee_get_reserved_memory(&optee_start, &optee_size)) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + }

/* before relocation, mark the U-Boot memory as cacheable by default */ if (!(gd->flags & GD_FLG_RELOC))

Move the stm32mp1 data cache reconfiguration after the lmb init call board_r::initr_lmb to allow parsing of the reserved region with no-map tag.

After this patch the DDR is not fully mapped up to arch_early_init_r() call, only the relocation region is mapped, but it is enough for the first board_r initialization phases; later, when arch_early_init_r() is called, the LMB is already initialized and the function lmb_is_reserved_flags() function is functional, this LMB function is called in the weak function dram_bank_mmu_setup() when dcache_enable() is executed.

Without this change, as LMB is not initialized when it is used in dram_bank_mmu_setup, the OP-TEE region is mapped cache-able by U-Boot and we have some firewall violation since "LMB memory map global and persistent" series.

Fixes: ed17a33fed29 ("lmb: make LMB memory map persistent and global") Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

arch/arm/mach-stm32mp/Kconfig | 2 ++ arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +++++++ 2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index d5934a927717..25663a99464d 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -39,6 +39,7 @@ choice

config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" + select ARCH_EARLY_INIT_R select ARM_SMCCC select CPU_V7A select CPU_V7_HAS_NONSEC @@ -57,6 +58,7 @@ config STM32MP13X

config STM32MP15X bool "Support STMicroelectronics STM32MP15x Soc" + select ARCH_EARLY_INIT_R select ARCH_SUPPORT_PSCI select BINMAN select CPU_V7A diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 64480da9f8d8..0b60e27a804d 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -143,6 +143,11 @@ void enable_caches(void) { /* I-cache is already enabled in start.S: icache_enable() not needed */

+ /* keep D-cache configuration done before relocation, wait arch_early_init_r*/ +} + +int arch_early_init_r(void) +{ /* deactivate the data cache, early enabled in arch_cpu_init() */ dcache_disable(); /* @@ -150,6 +155,8 @@ void enable_caches(void) * warning: the TLB location udpated in board_f.c::reserve_mmu */ dcache_enable(); + + return 0; }

static void setup_boot_mode(void)

Clarify the usage of SCMI specific device tree to use with stm32mp15_defconfig and with OP-TEE.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

doc/board/st/stm32mp1.rst | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 63b44776ffc1..8cf712992336 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -180,22 +180,41 @@ Each STMicroelectronics board is only configured with the associated device tree

STM32MP15x device Tree Selection ```````````````````````````````` -The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig) are: +The supported device trees for STM32MP15x (**stm32mp15_defconfig** for TF-A_ +with FIP support) are:

+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)

+ + **stm32mp157c-ev1-scmi** + stm32mp157c-ev1

+ ed1: daughter board with pmic stpmic1

+ + **stm32mp157c-ed1-scmi** + stm32mp157c-ed1

+ dk1: Discovery board

+ + **stm32mp157a-dk1-scmi** + stm32mp157a-dk1

+ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel

+ + **stm32mp157c-dk2-scmi** + + stm32mp157c-dk2 + +The scmi variant of each device tree is only supported with OP-TEE as secure +monitor and it is the configuration **recommended** by STMicroelectronics for +product, with secured system resources (RCC_TZCR.TZEN=1). + +The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig +TF-A without FIP support and stm32mp15_basic_defconfig with SPL) are: + ++ the same STMicroelectronics boards with the no scmi device tree files: + + + stm32mp157c-ev1 + + stm32mp157c-ed1 + + stm32mp157a-dk1 + stm32mp157c-dk2

+ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM @@ -204,11 +223,11 @@ The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32

STM32MP13x device Tree Selection ```````````````````````````````` -The supported device trees for STM32MP13x (stm32mp13_defconfig) are: +The supported device trees for STM32MP13x (**stm32mp13_defconfig**) are:

+ dk: Discovery board

- + stm32mp135f-dk + + **stm32mp135f-dk**

Build Procedure

In OP-TEE, the "optee_core@" node is reserved, appended in non secure device tree (see mark_tzdram_as_reserved() function under CFG_DT) so this name must be checked in optee_get_reserved_memory(). We keep the check on /reserved-memory/optee@ node to have backward compatibility with STMT32Image booting, when the reserved node is already present in U-Boot or SPL device tree with name "optee@".

This patch solves a boot issue on board with OP-TEE for U-Boot compiled with stm32mp15_defconfig and without secure configuration device tree (stm32mp157c-dk2.dts for example).

Fixes: 5fe9e0deabb1 ("stm32mp: allow calling optee_get_reserved_memory() from U-Boot") Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 58290105d127..6a36aecf5cd3 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -25,8 +25,11 @@ int optee_get_reserved_memory(u32 *start, u32 *size) ofnode node;

node = ofnode_path("/reserved-memory/optee"); - if (!ofnode_valid(node)) - return -ENOENT; + if (!ofnode_valid(node)) { + node = ofnode_path("/reserved-memory/optee_core"); + if (!ofnode_valid(node)) + return -ENOENT; + }

fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); *start = fdt_start;