From: Jonas Karlman jonas@kwiboo.se Date: Sat, 17 Feb 2024 12:34:04 +0000

FIT checksum validation is very slow in SPL due to D-cache not being enabled.

Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation, from seconds to milliseconds.

This change enables caches in SPL on all Rockchip ARM64 boards, the Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to disable caches for a specific board or SoC if needed.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

Changes in v4:

• Include cpu_func.h to fix build on armv7
• Remove common.h include

Changes in v3:

• Limit to ARM64 SoCs
• Fix build with SPL_SYS_ICACHE_OFF or SPL_SYS_DCACHE_OFF enabled
• Use cleanup_before_linux() in spl_board_prepare_for_boot() to disable caches before jumping from SPL to next stage
• Collect r-b tag

Changes in v2:

• None

This has been tested on multiple RK3328, RK3399, RK356x and RK3588 boards without any issues, vendor U-Boot also enables caches in SPL for all SoCs.

This only worked on RK3288 because the default enable_caches() that does not enable caches was being used. Trying to enable caches on my RK3288 froze my boards in mmu_setup(). So v3 limits the enable_caches() call to only include ARM64 SoCs.

FYI, enabling caches on 32-bit ARM SoCs is generally problematic because of the presence of non-architected caches. This poses a problem for an OS since it can't easily do cache-management in early boot code before SoC specific drivers attach.

So I agree that this is the right choice.

Link to RFC: https://patchwork.ozlabs.org/patch/1802303/ Link to v2: https://patchwork.ozlabs.org/patch/1889319/ Link to v3: https://patchwork.ozlabs.org/patch/1891025/

---

arch/arm/mach-rockchip/spl.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 87280e2ba7cc..1586a093fc37 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,7 +3,7 @@

• (C) Copyright 2019 Rockchip Electronics Co., Ltd

*/

-#include <common.h> +#include <cpu_func.h> #include <debug_uart.h> #include <dm.h> #include <hang.h> @@ -136,6 +136,20 @@ void board_init_f(ulong dummy) } gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size);

• if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {

• gd->relocaddr = gd->ram_top;
  

• arch_reserve_mmu();
  

• enable_caches();
  

• }

#endif preloader_console_init(); }

+void spl_board_prepare_for_boot(void) +{

• if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))

• return;
  

• cleanup_before_linux();

+}

2.43.0