[PATCH 0/4] board: beagle: Enable 32k and debounce configuration
Hi,
This is a follow up from [1] - Without the 32k crystal configuration, wlan does'nt work. Debounce is needed for HDMI hpd gpio interrupt.
At least the 32k configuration has been done for toradex and phytec boards, follow similar model of programming.
This series is based on master commit e8f2404e093d + the findfdt series[2].
Nishanth Menon (4): board: beagle: beagleplay: Enable 32k crystal configs: am62x_beagleplay_r5_defconfig: Enable SPL_BOARD_INIT arm: mach-k3: am62: Add Debounce configuration register definitions board: beagle: beagleplay: Configure debounce registers
arch/arm/mach-k3/include/mach/am62_hardware.h | 3 + board/beagle/beagleplay/beagleplay.c | 61 +++++++++++++++++++ configs/am62x_beagleplay_r5_defconfig | 1 + 3 files changed, 65 insertions(+)
[1] https://lore.kernel.org/u-boot/20230725185253.2123433-4-nm@ti.com/ [2] https://lore.kernel.org/all/20240130130615.670783-1-nm@ti.com/
Enable the external 32k crystal similar to that found on other production AM62X board. The trim settings for the crystal is board dependent, so the sequences tend to be board specific. Since this is a configuration that needs to be done prior to DM managing the system and all other muxes get set, do the same from R5 context.
Signed-off-by: Nishanth Menon nm@ti.com --- board/beagle/beagleplay/beagleplay.c | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 20819ecf45b4..a75b3145fa37 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -11,6 +11,8 @@ #include <fdt_support.h> #include <spl.h>
+#include <asm/arch/hardware.h> + DECLARE_GLOBAL_DATA_PTR;
int board_init(void) @@ -28,6 +30,41 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); }
+#ifdef CONFIG_SPL_BOARD_INIT + +/* + * Enable the 32k Crystal: needed for accurate 32k clock + * and external clock sources such as wlan 32k input clock + * supplied from the SoC to the wlan chip. + * + * The trim setup can be very highly board type specific choice of the crystal + * So this is done in the board file, though, in this case, no specific trim + * is necessary. + */ +static void crystal_32k_enable(void) +{ + /* Only mess with 32k at the start of boot from R5 */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * We have external 32k crystal, so lets enable it (0x0) + * and disable bypass (0x0) + */ + writel(0x0, MCU_CTRL_LFXOSC_CTRL); + + /* Add any crystal specific TRIM needed here.. */ + + /* Make sure to mux the SoC 32k from the crystal */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + } +} + +void spl_board_init(void) +{ + crystal_32k_enable(); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) {
On Mon, Feb 12, 2024 at 9:53 AM Nishanth Menon nm@ti.com wrote:
Enable the external 32k crystal similar to that found on other production AM62X board. The trim settings for the crystal is board dependent, so the sequences tend to be board specific. Since this is a configuration that needs to be done prior to DM managing the system and all other muxes get set, do the same from R5 context.
Signed-off-by: Nishanth Menon nm@ti.com
Tested-by: Robert Nelson robertcnelson@gmail.com
Yay, WiFi (wl18xx) now works on the BeaglePay with these 4 patches on top of v2024.01-rc1
debian@BeaglePlay-57:~$ dmesg | grep wl [ 1.892839] wlan_en: supplied by vdd_3v3 [ 8.437425] systemd[1]: Expecting device sys-subsystem-net-devices-wlan0.device - /sys/subsystem/net/devices/wlan0... [ 13.241739] wlcore: wl18xx HW: 183x or 180x, PG 2.2 (ROM 0x11) [ 13.246116] wlcore: WARNING Detected unconfigured mac address in nvs, derive from fuse instead. [ 13.246155] wlcore: WARNING This default nvs file can be removed from the file system [ 13.253088] wlcore: loaded [ 13.788451] wlcore: using inverted interrupt logic: 2 [ 13.842464] wlcore: PHY firmware version: Rev 8.2.0.0.243 [ 13.938371] wlcore: firmware booted (Rev 8.9.0.0.83)
Regards,
Enable CONFIG_SPL_BOARD_INIT to configure the 32k crystal.
Signed-off-by: Nishanth Menon nm@ti.com --- configs/am62x_beagleplay_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 2f3264b7ede6..9413c859870f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
Add the Debounce configuration registers that need to be configured one time for the platform for the entire SoC.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e161..06fcab01a5b7 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -75,6 +75,9 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 4080 + (index * 4)) + #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
On 09:53-20240212, Nishanth Menon wrote:
Add the Debounce configuration registers that need to be configured one time for the platform for the entire SoC.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e161..06fcab01a5b7 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -75,6 +75,9 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 4080 + (index * 4))
Grrr.. missed the fixup for 0x4080 here. will wait a couple of days for any other review comments.
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
2.43.0
Configure the debounce configuration that makes sense for BeaglePlay usage model.
Signed-off-by: Nishanth Menon nm@ti.com --- board/beagle/beagleplay/beagleplay.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index a75b3145fa37..5640fdf41ed3 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -59,9 +59,33 @@ static void crystal_32k_enable(void) } }
+static void debounce_configure(void) +{ + /* Configure debounce one time from R5 */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Setup debounce time registers. + * arbitrary values. Times are approx + */ + /* 1.9ms debounce @ 32k */ + writel(0x1, CTRLMMR_DBOUNCE_CFG(1)); + /* 5ms debounce @ 32k */ + writel(0x5, CTRLMMR_DBOUNCE_CFG(2)); + /* 20ms debounce @ 32k */ + writel(0x14, CTRLMMR_DBOUNCE_CFG(3)); + /* 46ms debounce @ 32k */ + writel(0x18, CTRLMMR_DBOUNCE_CFG(4)); + /* 100ms debounce @ 32k */ + writel(0x1c, CTRLMMR_DBOUNCE_CFG(5)); + /* 156ms debounce @ 32k */ + writel(0x1f, CTRLMMR_DBOUNCE_CFG(6)); + } +} + void spl_board_init(void) { crystal_32k_enable(); + debounce_configure(); } #endif
participants (2)
-
Nishanth Menon -
Robert Nelson