[U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
Icenowy Zheng (12): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code sunxi: Add selective DRAM type and timing sunxi: enable dual rank detection in DesignWare-like DRAM code sunxi: add support for the DDR2 in V3s SoC sunxi: add support for V3s DRAM controller sunxi: enable DRAM initialization and SPL for V3s SoC sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller sunxi: add LPDDR3 timing from stock boot0 sunxi: add a defconfig for SoPine w/ official baseboard
arch/arm/include/asm/arch-sunxi/dram.h | 6 +- .../{dram_sun8i_h3.h => dram_sunxi_dw.h} | 36 +++- arch/arm/mach-sunxi/Makefile | 5 +- .../{dram_sun8i_h3.c => dram_sunxi_dw.c} | 187 +++++++-------------- arch/arm/mach-sunxi/dram_timings/Makefile | 3 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 84 +++++++++ arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 87 ++++++++++ arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84 +++++++++ board/sunxi/Kconfig | 75 ++++++++- configs/sopine_baseboard_defconfig | 22 +++ 10 files changed, 454 insertions(+), 135 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c create mode 100644 configs/sopine_baseboard_defconfig
From: Icenowy Zheng icenowy@aosc.xyz
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz Acked-by: Maxime Ripard maxime.ripard@free-electrons.com --- arch/arm/include/asm/arch-sunxi/dram.h | 6 ++---- .../asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} | 0 arch/arm/mach-sunxi/Makefile | 4 +--- arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} | 0 board/sunxi/Kconfig | 10 ++++++++++ 5 files changed, 13 insertions(+), 7 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (100%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (100%)
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index f452f889f9..80abac95b8 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,10 +24,8 @@ #include <asm/arch/dram_sun8i_a33.h> #elif defined(CONFIG_MACH_SUN8I_A83T) #include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \ - defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN50I) -#include <asm/arch/dram_sun8i_h3.h> +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include <asm/arch/dram_sunxi_dw.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/dram_sun9i.h> #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h similarity index 100% rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 5510aa5435..41cee26765 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,8 +48,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o -obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o -obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c similarity index 100% rename from arch/arm/mach-sunxi/dram_sun8i_h3.c rename to arch/arm/mach-sunxi/dram_sunxi_dw.c diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b47034f417..f1338dd539 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -55,10 +55,18 @@ config SUNXI_GEN_SUN6I separate ahb reset control registers, custom pmic bus, new style watchdog, etc.
+config SUNXI_DRAM_DW + bool + ---help--- + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code.
config MACH_SUNXI_H3_H5 bool select SUNXI_DE2 + select SUNXI_DRAM_DW select SUNXI_GEN_SUN6I select SUPPORT_SPL
@@ -143,6 +151,7 @@ config MACH_SUN8I_R40 select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_DRAM_DW
config MACH_SUN8I_V3S bool "sun8i (Allwinner V3s)" @@ -167,6 +176,7 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM select SUPPORT_SPL + select SUNXI_DRAM_DW
config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)"
From: Icenowy Zheng icenowy@aosc.xyz
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to identify whether the DRAM is half-width.
As H3 itself come with 32-bit DRAM, the two modes of the bit used to be named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM they're really 8-bit and 16-bit.
Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c.
This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 6 +++--- arch/arm/mach-sunxi/dram_sunxi_dw.c | 11 ++++++----- 2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 2770986b61..d301ac95c3 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -53,9 +53,9 @@ struct sunxi_mctl_com_reg { #define MCTL_CR_SEQUENTIAL (0x1 << 15) #define MCTL_CR_INTERLEAVED (0x0 << 15)
-#define MCTL_CR_32BIT (0x1 << 12) -#define MCTL_CR_16BIT (0x0 << 12) -#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) +#define MCTL_CR_FULL_WIDTH (0x1 << 12) +#define MCTL_CR_HALF_WIDTH (0x0 << 12) +#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12)
#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) #define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 2d12661a14..77fa6c2889 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -28,7 +28,7 @@ #define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) struct dram_para { u16 page_size; - u8 bus_width; + u8 bus_full_width; u8 dual_rank; u8 row_bits; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; @@ -440,7 +440,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + MCTL_CR_EIGHT_BANKS | + MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); @@ -578,7 +579,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) }
/* set half DQ */ - if (para->bus_width != 32) { + if (!para->bus_full_width) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); } @@ -622,7 +623,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); - para->bus_width = 16; + para->bus_full_width = 0; }
mctl_set_cr(socid, para); @@ -758,7 +759,7 @@ unsigned long sunxi_dram_init(void)
struct dram_para para = { .dual_rank = 0, - .bus_width = 32, + .bus_full_width = 1, .row_bits = 15, .page_size = 4096,
From: Icenowy Zheng icenowy@aosc.xyz
Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 33 +++++++++++++++++++++++++++++---- board/sunxi/Kconfig | 17 +++++++++++++++++ 2 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 77fa6c2889..de683a1b63 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -380,6 +380,13 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int zq_count; + +#if defined CONFIG_SUNXI_DRAM_DW_16BIT + zq_count = 4; +#else + zq_count = 6; +#endif
if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { @@ -408,7 +415,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
- for (i = 0; i < 6; i++) { + for (i = 0; i < zq_count; i++) { u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
writel((zq << 20) | (zq << 16) | (zq << 12) | @@ -430,7 +437,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + if (zq_count > 4) + writel((zq_val[5] << 16) | zq_val[4], + &mctl_ctl->zqdr[2]); } }
@@ -580,8 +589,14 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
/* set half DQ */ if (!para->bus_full_width) { +#if defined CONFIG_SUNXI_DRAM_DW_32BIT writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + writel(0x0, &mctl_ctl->dx[1].gcr); +#else +#error Unsupported DRAM bus width! +#endif }
/* data training configuration */ @@ -612,19 +627,29 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* detect ranks and bus width */ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { /* only one rank */ - if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) || - ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) { + if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) +#if defined CONFIG_SUNXI_DRAM_DW_32BIT + || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2) +#endif + ) { clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); para->dual_rank = 0; }
/* only half DQ width */ +#if defined CONFIG_SUNXI_DRAM_DW_32BIT if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) || ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); para->bus_full_width = 0; } +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) { + writel(0x0, &mctl_ctl->dx[1].gcr); + para->bus_full_width = 0; + } +#endif
mctl_set_cr(socid, para); udelay(20); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f1338dd539..f6da8958c5 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -63,10 +63,25 @@ config SUNXI_DRAM_DW not have official open-source DRAM initialization code, but can use modified H3 DRAM initialization code.
+if SUNXI_DRAM_DW +config SUNXI_DRAM_DW_16BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller and + have only 16-bit memory buswidth. + +config SUNXI_DRAM_DW_32BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller with + 32-bit memory buswidth. +endif + config MACH_SUNXI_H3_H5 bool select SUNXI_DE2 select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT select SUNXI_GEN_SUN6I select SUPPORT_SPL
@@ -152,6 +167,7 @@ config MACH_SUN8I_R40 select SUNXI_GEN_SUN6I select SUPPORT_SPL select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT
config MACH_SUN8I_V3S bool "sun8i (Allwinner V3s)" @@ -177,6 +193,7 @@ config MACH_SUN50I select SUNXI_HIGH_SRAM select SUPPORT_SPL select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT
config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)"
From: Icenowy Zheng icenowy@aosc.xyz
Some DDR2 DRAM have only four banks, not eight.
Add code to detect this situation.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index de683a1b63..3f54c8ee09 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -31,6 +31,7 @@ struct dram_para { u8 bus_full_width; u8 dual_rank; u8 row_bits; + u8 bank_bits; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 ac_delays[31]; @@ -449,7 +450,7 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | + (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | @@ -689,10 +690,19 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) /* detect row address bits */ para->page_size = 512; para->row_bits = 16; + para->bank_bits = 2; mctl_set_cr(socid, para);
for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) - if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) + break; + + /* detect bank address bits */ + para->bank_bits = 3; + mctl_set_cr(socid, para); + + for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) + if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) break;
/* detect page size */ @@ -786,6 +796,7 @@ unsigned long sunxi_dram_init(void) .dual_rank = 0, .bus_full_width = 1, .row_bits = 15, + .bank_bits = 3, .page_size = 4096,
#if defined(CONFIG_MACH_SUN8I_H3) @@ -850,6 +861,6 @@ unsigned long sunxi_dram_init(void) mctl_auto_detect_dram_size(socid, ¶); mctl_set_cr(socid, ¶);
- return (1UL << (para.row_bits + 3)) * para.page_size * - (para.dual_rank ? 2 : 1); + return (1UL << (para.row_bits + para.bank_bits)) * para.page_size * + (para.dual_rank ? 2 : 1); }
From: Icenowy Zheng icenowy@aosc.xyz
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sunxi_dw.c | 119 ++---------------------- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 87 +++++++++++++++++ board/sunxi/Kconfig | 18 ++++ 6 files changed, 143 insertions(+), 113 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index d301ac95c3..03fd46b724 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -205,4 +205,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0)
+/* + * The delay parameters below allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +struct dram_para { + u16 page_size; + u8 bus_full_width; + u8 dual_rank; + u8 row_bits; + u8 bank_bits; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 41cee26765..2a3c379b72 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o endif diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 3f54c8ee09..a5706423cb 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,34 +16,6 @@ #include <asm/arch/cpu.h> #include <linux/kconfig.h>
-/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define BITS_PER_BYTE 8 -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para { - u16 page_size; - u8 bus_full_width; - u8 dual_rank; - u8 row_bits; - u8 bank_bits; - const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 ac_delays[31]; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - static void mctl_phy_init(u32 val) { struct sunxi_mctl_ctl_reg * const mctl_ctl = @@ -269,90 +241,6 @@ static void mctl_set_master_priority(uint16_t socid) } }
-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - u16 trefi = ns_to_t(7800) / 32; - u16 trfc = ns_to_t(350); - - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 4; - u8 trasmax = 24; - - u8 tcl = 6; /* CL 12 */ - u8 tcwl = 4; /* CWL 8 */ - u8 t_rdata_en = 4; - u8 wr_latency = 2; - - u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ - u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ - u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ - - /* set mode register */ - writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ - writel(0x40, &mctl_ctl->mr[1]); - writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ - writel(0x0, &mctl_ctl->mr[3]); - - if (socid == SOCID_R40) - writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ - - /* set DRAM timing */ - writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | - DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), - &mctl_ctl->dramtmg[0]); - writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), - &mctl_ctl->dramtmg[1]); - writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | - DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), - &mctl_ctl->dramtmg[2]); - writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), - &mctl_ctl->dramtmg[3]); - writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | - DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); - writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | - DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), - &mctl_ctl->dramtmg[5]); - - /* set two rank timing */ - clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), - ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); - - /* set PHY interface timing, write latency and read latency configure */ - writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | - (wr_latency << 0), &mctl_ctl->pitmg[0]); - - /* set PHY timing, PTR0-2 use default */ - writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); - writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); - - /* set refresh timing */ - writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); -} - static u32 bin_to_mgray(int val) { static const u8 lookup_table[32] = { @@ -449,7 +337,12 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | + writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED | +#if defined CONFIG_SUNXI_DRAM_DDR3 + MCTL_CR_DDR3 | MCTL_CR_2T | +#else +#error Unsupported DRAM type! +#endif (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile new file mode 100644 index 0000000000..7e71c76a5c --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c new file mode 100644 index 0000000000..0471e8a49e --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -0,0 +1,87 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ + writel(0x40, &mctl_ctl->mr[1]); + writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ + writel(0x0, &mctl_ctl->mr[3]); + + if (socid == SOCID_R40) + writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f6da8958c5..06b52c91ea 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -236,6 +236,24 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed.
+if SUNXI_DRAM_DW +config SUNXI_DRAM_DDR3 + bool + +choice + prompt "DRAM Type and Timing" + default SUNXI_DRAM_DDR3_1333 + +config SUNXI_DRAM_DDR3_1333 + bool "DDR3 1333" + select SUNXI_DRAM_DDR3 + ---help--- + This option is the original only supported memory type, which suits + many H3/H5/A64 boards available now. + +endchoice +endif + config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T
On 26/04/17 15:50, Icenowy Zheng wrote:
From: Icenowy Zheng icenowy@aosc.xyz
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Confirmed that this just moves the code, no changes in the actual parameters. Given that the code doesn't change upstream meanwhile:
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz
Reviewed-by: Andre Przywara andre.przywara@arm.com
Thanks! Andre
arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sunxi_dw.c | 119 ++---------------------- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 87 +++++++++++++++++ board/sunxi/Kconfig | 18 ++++ 6 files changed, 143 insertions(+), 113 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index d301ac95c3..03fd46b724 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -205,4 +205,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0)
+/*
- The delay parameters below allow to allegedly specify delay times of some
- unknown unit for each individual bit trace in each of the four data bytes
- the 32-bit wide access consists of. Also three control signals can be
- adjusted individually.
- */
+#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +struct dram_para {
- u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
- u8 row_bits;
- u8 bank_bits;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 ac_delays[31];
+};
+static inline int ns_to_t(int nanoseconds) +{
- const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
- return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 41cee26765..2a3c379b72 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o endif diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 3f54c8ee09..a5706423cb 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,34 +16,6 @@ #include <asm/arch/cpu.h> #include <linux/kconfig.h>
-/*
- The delay parameters below allow to allegedly specify delay times of some
- unknown unit for each individual bit trace in each of the four data bytes
- the 32-bit wide access consists of. Also three control signals can be
- adjusted individually.
- */
-#define BITS_PER_BYTE 8 -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para {
- u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
- u8 row_bits;
- u8 bank_bits;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 ac_delays[31];
-};
-static inline int ns_to_t(int nanoseconds) -{
- const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
- return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
-}
static void mctl_phy_init(u32 val) { struct sunxi_mctl_ctl_reg * const mctl_ctl = @@ -269,90 +241,6 @@ static void mctl_set_master_priority(uint16_t socid) } }
-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) -{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
- /* set mode register */
- writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
- writel(0x40, &mctl_ctl->mr[1]);
- writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
- writel(0x0, &mctl_ctl->mr[3]);
- if (socid == SOCID_R40)
writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),&mctl_ctl->dramtmg[0]);- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
&mctl_ctl->dramtmg[1]);- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),&mctl_ctl->dramtmg[2]);- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
&mctl_ctl->dramtmg[3]);- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),&mctl_ctl->dramtmg[5]);- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
(wr_latency << 0), &mctl_ctl->pitmg[0]);- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
-}
static u32 bin_to_mgray(int val) { static const u8 lookup_table[32] = { @@ -449,7 +337,12 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
- writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
+#if defined CONFIG_SUNXI_DRAM_DDR3
MCTL_CR_DDR3 | MCTL_CR_2T |+#else +#error Unsupported DRAM type! +#endif (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile new file mode 100644 index 0000000000..7e71c76a5c --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c new file mode 100644 index 0000000000..0471e8a49e --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -0,0 +1,87 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h>
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
- /* set mode register */
- writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
- writel(0x40, &mctl_ctl->mr[1]);
- writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
- writel(0x0, &mctl_ctl->mr[3]);
- if (socid == SOCID_R40)
writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),&mctl_ctl->dramtmg[0]);- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
&mctl_ctl->dramtmg[1]);- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),&mctl_ctl->dramtmg[2]);- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
&mctl_ctl->dramtmg[3]);- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),&mctl_ctl->dramtmg[5]);- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
(wr_latency << 0), &mctl_ctl->pitmg[0]);- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f6da8958c5..06b52c91ea 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -236,6 +236,24 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed.
+if SUNXI_DRAM_DW +config SUNXI_DRAM_DDR3
- bool
+choice
- prompt "DRAM Type and Timing"
- default SUNXI_DRAM_DDR3_1333
+config SUNXI_DRAM_DDR3_1333
- bool "DDR3 1333"
- select SUNXI_DRAM_DDR3
- ---help---
- This option is the original only supported memory type, which suits
- many H3/H5/A64 boards available now.
+endchoice +endif
config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T
From: Icenowy Zheng icenowy@aosc.xyz
The DesignWare-like DRAM code used to set the controller defaultly to single rank mode, which makes it not able to detect the second rank.
Set the default value to dual rank, thus the rank detection code can work and finally the rank setting will be the correct value.
Currently we know little about the dual-rank on R40, and the usage of A15 address line seems to be breaking dual-rank support. The only R40 board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather than dual-rank, thus we cannot do research for it. So dual rank detection is temporarily disabled on R40.
This change is tested on a Orange Pi One (H3, single rank), a Pine64+ 2GiB version (A64, single rank) , a Pinebook early prototype with DDR3 (A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins on one chip).
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index a5706423cb..bd606ccc65 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -686,7 +686,7 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct dram_para para = { - .dual_rank = 0, + .dual_rank = 1, .bus_full_width = 1, .row_bits = 15, .bank_bits = 3, @@ -719,6 +719,8 @@ unsigned long sunxi_dram_init(void) uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN8I_R40) uint16_t socid = SOCID_R40; + /* Currently we cannot support R40 with dual rank memory */ + para.dual_rank = 0; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; #elif defined(CONFIG_MACH_SUN50I_H5)
From: Icenowy Zheng icenowy@aosc.xyz
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param.
Add support for it.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 + arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 84 +++++++++++++++++++++++++++++ board/sunxi/Kconfig | 10 ++++ 4 files changed, 97 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index bd606ccc65..438b4740cd 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -340,6 +340,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED | #if defined CONFIG_SUNXI_DRAM_DDR3 MCTL_CR_DDR3 | MCTL_CR_2T | +#elif defined CONFIG_SUNXI_DRAM_DDR2 + MCTL_CR_DDR2 | MCTL_CR_2T | #else #error Unsupported DRAM type! #endif diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 7e71c76a5c..a4c9dc556c 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c new file mode 100644 index 0000000000..9077f86a8b --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 1; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = ns_to_t(20); + u8 trc = ns_to_t(65); + u8 txp = 2; + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(45); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(328); + + u8 tmrw = 0; + u8 tmrd = 2; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 27; + + u8 tcl = 3; /* CL 6 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = 1; + u8 wr_latency = 1; + + u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ + u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x263, &mctl_ctl->mr[0]); + writel(0x4, &mctl_ctl->mr[1]); + writel(0x0, &mctl_ctl->mr[2]); + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 06b52c91ea..907ec157f9 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -240,6 +240,9 @@ if SUNXI_DRAM_DW config SUNXI_DRAM_DDR3 bool
+config SUNXI_DRAM_DDR2 + bool + choice prompt "DRAM Type and Timing" default SUNXI_DRAM_DDR3_1333 @@ -251,6 +254,13 @@ config SUNXI_DRAM_DDR3_1333 This option is the original only supported memory type, which suits many H3/H5/A64 boards available now.
+config SUNXI_DRAM_DDR2_V3S + bool "DDR2 found in V3s chip" + select SUNXI_DRAM_DDR2 + ---help--- + This option is only for the DDR2 memory chip which is co-packaged in + Allwinner V3s SoC. + endchoice endif
From: Icenowy Zheng icenowy@aosc.xyz
Allwinner V3s features a DRAM controller like the on in H3, but with a DDR2 DRAM.
Add support for it.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++ board/sunxi/Kconfig | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 438b4740cd..20c3055b7a 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -723,6 +723,9 @@ unsigned long sunxi_dram_init(void) uint16_t socid = SOCID_R40; /* Currently we cannot support R40 with dual rank memory */ para.dual_rank = 0; +#elif defined(CONFIG_MACH_SUN8I_V3S) + /* TODO: set delays and mbus priority for V3s */ + uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; #elif defined(CONFIG_MACH_SUN50I_H5) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 907ec157f9..485901fea5 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -245,11 +245,13 @@ config SUNXI_DRAM_DDR2
choice prompt "DRAM Type and Timing" - default SUNXI_DRAM_DDR3_1333 + default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S + default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 + depends on !MACH_SUN8I_V3S ---help--- This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. @@ -257,6 +259,7 @@ config SUNXI_DRAM_DDR3_1333 config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 + depends on MACH_SUN8I_V3S ---help--- This option is only for the DDR2 memory chip which is co-packaged in Allwinner V3s SoC.
As we have already support for the DesignWare DRAM controller and the integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This patch also contains the default DRAM configuration for V3s.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- board/sunxi/Kconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 485901fea5..08df738f94 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -176,6 +176,9 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_16BIT + select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN9I @@ -279,7 +282,8 @@ config DRAM_CLK default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 default 312 if MACH_SUN6I || MACH_SUN8I - default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ + MACH_SUN8I_V3S default 672 if MACH_SUN50I ---help--- Set the dram clock speed, valid range 240 - 480 (prior to sun9i), @@ -299,6 +303,7 @@ config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I + default 14779 if MACH_SUN8I_V3S default 3881979 if MACH_SUN8I_R40 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I
From: Icenowy Zheng icenowy@aosc.xyz
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM chips.
Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.
Real LPDDR3 chips' support is not added yet in this commit.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 ++ board/sunxi/Kconfig | 3 +++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 20c3055b7a..78b4ffb9c3 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -342,6 +342,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) MCTL_CR_DDR3 | MCTL_CR_2T | #elif defined CONFIG_SUNXI_DRAM_DDR2 MCTL_CR_DDR2 | MCTL_CR_2T | +#elif defined CONFIG_SUNXI_DRAM_LPDDR3 + MCTL_CR_LPDDR3 | MCTL_CR_1T | #else #error Unsupported DRAM type! #endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 08df738f94..8be75048d1 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -246,6 +246,9 @@ config SUNXI_DRAM_DDR3 config SUNXI_DRAM_DDR2 bool
+config SUNXI_DRAM_LPDDR3 + bool + choice prompt "DRAM Type and Timing" default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
From: Icenowy Zheng icenowy@aosc.xyz
As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz --- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84 +++++++++++++++++++++++++ board/sunxi/Kconfig | 7 +++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index a4c9dc556c..278a8a14cc 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c new file mode 100644 index 0000000000..1085efe48e --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = max(ns_to_t(50), 4); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = max(ns_to_t(24), 2); + u8 trc = ns_to_t(70); + u8 txp = max(ns_to_t(8), 2); + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 3); + u8 trp = max(ns_to_t(27), 2); + u8 tras = ns_to_t(42); + u16 trefi = ns_to_t(3900) / 32; + u16 trfc = ns_to_t(210); + + u8 tmrw = 5; + u8 tmrd = 5; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 5; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = 5; + u8 wr_latency = 2; + + u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ + u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 4 + twr + 1; + u8 twr2rd = tcwl + 4 + 1 + twtr; + u8 trd2wr = tcl + 4 + 5 - tcwl + 1; + + /* set mode register */ + writel(0, &mctl_ctl->mr[0]); + writel(0xc3, &mctl_ctl->mr[1]); + writel(0xa, &mctl_ctl->mr[2]); /* CWL=6 */ + writel(0x2, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 8be75048d1..7ad00bb162 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -262,6 +262,13 @@ config SUNXI_DRAM_DDR3_1333 This option is the original only supported memory type, which suits many H3/H5/A64 boards available now.
+config SUNXI_DRAM_LPDDR3_STOCK + bool "LPDDR3 with Allwinner stock configuration" + select SUNXI_DRAM_LPDDR3 + ---help--- + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2
On 26/04/17 15:50, Icenowy Zheng wrote:
From: Icenowy Zheng icenowy@aosc.xyz
As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it.
Add the timing info used by stock boot0.
When I checked the disassembly/decompile for the Pine64 libdram, I found some more registers differing when DRAM type is 7 (LPDDR3), mostly in mctl_channel_init(). I can send patches on top of this series to set those bits. Does it work reliably for you with this series?
More below ...
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz
arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84 +++++++++++++++++++++++++ board/sunxi/Kconfig | 7 +++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index a4c9dc556c..278a8a14cc 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c new file mode 100644 index 0000000000..1085efe48e --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h>
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;- u8 tccd = 2;
- u8 tfaw = max(ns_to_t(50), 4);
- u8 trrd = max(ns_to_t(10), 2);
- u8 trcd = max(ns_to_t(24), 2);
- u8 trc = ns_to_t(70);
- u8 txp = max(ns_to_t(8), 2);
- u8 twtr = max(ns_to_t(8), 2);
- u8 trtp = max(ns_to_t(8), 2);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = max(ns_to_t(27), 2);
- u8 tras = ns_to_t(42);
- u16 trefi = ns_to_t(3900) / 32;
- u16 trfc = ns_to_t(210);
Where do those values come from?
- u8 tmrw = 5;
- u8 tmrd = 5;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 5;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 3; /* CWL 6 */
- u8 t_rdata_en = 5;
- u8 wr_latency = 2;
- u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
- u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
- u8 twtp = tcwl + 4 + twr + 1;
- u8 twr2rd = tcwl + 4 + 1 + twtr;
- u8 trd2wr = tcl + 4 + 5 - tcwl + 1;
- /* set mode register */
I found explanations for the mode registers in the datasheet for the PineBook DRAM, so:
- writel(0, &mctl_ctl->mr[0]);
According to the datasheet (and generic LPDDR3 docs) this register is read-only, so we don't need to write this at all.
- writel(0xc3, &mctl_ctl->mr[1]);
Can you add: /* nWR=8, BL8 */ to document the magic value?
- writel(0xa, &mctl_ctl->mr[2]); /* CWL=6 */
Can you change this comment to: /* RL=12, WL=6 */ ? Also according to the datasheet for 533 MHz we can go with RL=8 and WL=4, which would encode as "0x6". Maybe worth experimenting with, or adding as a TODO.
- writel(0x2, &mctl_ctl->mr[3]);
Can you add: /* 40 Ohms PD/PU */ ?
- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),&mctl_ctl->dramtmg[0]);- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
&mctl_ctl->dramtmg[1]);- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),&mctl_ctl->dramtmg[2]);- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
&mctl_ctl->dramtmg[3]);- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),&mctl_ctl->dramtmg[5]);
As this block is the same as for DDR3, I wonder if it's worth factoring this out. But this may be part of a future rework.
Cheers, Andre
- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
(0x66 << 8) | (0x10 << 0));- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
(wr_latency << 0), &mctl_ctl->pitmg[0]);- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 8be75048d1..7ad00bb162 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -262,6 +262,13 @@ config SUNXI_DRAM_DDR3_1333 This option is the original only supported memory type, which suits many H3/H5/A64 boards available now.
+config SUNXI_DRAM_LPDDR3_STOCK
- bool "LPDDR3 with Allwinner stock configuration"
- select SUNXI_DRAM_LPDDR3
- ---help---
- This option is the LPDDR3 timing used by the stock boot0 by
- Allwinner.
config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2
于 2017年5月10日 GMT+08:00 上午7:44:21, "André Przywara" andre.przywara@arm.com 写到:
On 26/04/17 15:50, Icenowy Zheng wrote:
From: Icenowy Zheng icenowy@aosc.xyz
As we added LPDDR3 support in the former patch, we need a set of
timing
info to really enable it.
Add the timing info used by stock boot0.
When I checked the disassembly/decompile for the Pine64 libdram, I found some more registers differing when DRAM type is 7 (LPDDR3), mostly in mctl_channel_init(). I can send patches on top of this series to set those bits. Does it work reliably for you with this series?
Yes, tested on a SoPine w/ baseboard and a Pinebook.
More below ...
Signed-off-by: Icenowy Zheng icenowy@aosc.xyz
arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84
+++++++++++++++++++++++++
board/sunxi/Kconfig | 7 +++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile
b/arch/arm/mach-sunxi/dram_timings/Makefile
index a4c9dc556c..278a8a14cc 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
new file mode 100644 index 0000000000..1085efe48e --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h>
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;- u8 tccd = 2;
- u8 tfaw = max(ns_to_t(50), 4);
- u8 trrd = max(ns_to_t(10), 2);
- u8 trcd = max(ns_to_t(24), 2);
- u8 trc = ns_to_t(70);
- u8 txp = max(ns_to_t(8), 2);
- u8 twtr = max(ns_to_t(8), 2);
- u8 trtp = max(ns_to_t(8), 2);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = max(ns_to_t(27), 2);
- u8 tras = ns_to_t(42);
- u16 trefi = ns_to_t(3900) / 32;
- u16 trfc = ns_to_t(210);
Where do those values come from?
- u8 tmrw = 5;
- u8 tmrd = 5;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 5;
- u8 trasmax = 24;
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 3; /* CWL 6 */
- u8 t_rdata_en = 5;
- u8 wr_latency = 2;
- u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
- u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
- u8 twtp = tcwl + 4 + twr + 1;
- u8 twr2rd = tcwl + 4 + 1 + twtr;
- u8 trd2wr = tcl + 4 + 5 - tcwl + 1;
- /* set mode register */
I found explanations for the mode registers in the datasheet for the PineBook DRAM, so:
- writel(0, &mctl_ctl->mr[0]);
According to the datasheet (and generic LPDDR3 docs) this register is read-only, so we don't need to write this at all.
- writel(0xc3, &mctl_ctl->mr[1]);
Can you add: /* nWR=8, BL8 */ to document the magic value?
- writel(0xa, &mctl_ctl->mr[2]); /* CWL=6 */
Can you change this comment to: /* RL=12, WL=6 */ ? Also according to the datasheet for 533 MHz we can go with RL=8 and WL=4, which would encode as "0x6". Maybe worth experimenting with, or adding as a TODO.
- writel(0x2, &mctl_ctl->mr[3]);
Can you add: /* 40 Ohms PD/PU */ ?
- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),&mctl_ctl->dramtmg[0]);- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
&mctl_ctl->dramtmg[1]);- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),&mctl_ctl->dramtmg[2]);- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) |
DRAMTMG3_TMOD(tmod),
&mctl_ctl->dramtmg[3]);- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) |
DRAMTMG4_TRRD(trrd) |
DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),&mctl_ctl->dramtmg[5]);As this block is the same as for DDR3, I wonder if it's worth factoring this out. But this may be part of a future rework.
Cheers, Andre
- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
(0x66 << 8) | (0x10 << 0));- /* set PHY interface timing, write latency and read latency
configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
(wr_latency << 0), &mctl_ctl->pitmg[0]);- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1),
&mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3),
&mctl_ctl->ptr[4]);
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc),
&mctl_ctl->rfshtmg);
+} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 8be75048d1..7ad00bb162 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -262,6 +262,13 @@ config SUNXI_DRAM_DDR3_1333 This option is the original only supported memory type, which suits many H3/H5/A64 boards available now.
+config SUNXI_DRAM_LPDDR3_STOCK
- bool "LPDDR3 with Allwinner stock configuration"
- select SUNXI_DRAM_LPDDR3
- ---help---
- This option is the LPDDR3 timing used by the stock boot0 by
- Allwinner.
config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig new file mode 100644 index 0000000000..02ffb43d54 --- /dev/null +++ b/configs/sopine_baseboard_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y
On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng icenowy@aosc.io wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig
Can't this be simply sopine_defconfig
Please add MAINTAINERS entry as well
thanks!
Hi,
On 02/06/17 19:32, Jagan Teki wrote:
On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng icenowy@aosc.io wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig
Can't this be simply sopine_defconfig
No, because the SoPine module itself is not complete and the system's DT may be much different between using different baseboards. So using the term "baseboard" in there is correct. Question is whether we want to have a separate sopine.dtsi, which just describes the module, then (multiple) baseboard .dts files including this sopine.dtsi. But this is a bit premature until we actually see a second baseboard, at which point we could still split this up then.
Cheers, Andre.
On 03/06/17 00:59, André Przywara wrote:
Hi,
On 02/06/17 19:32, Jagan Teki wrote:
On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng icenowy@aosc.io wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig
Can't this be simply sopine_defconfig
No, because the SoPine module itself is not complete and the system's DT
may be much different between using different baseboards. So using the term "baseboard" in there is correct. Question is whether we want to have a separate sopine.dtsi, which just describes the module, then (multiple) baseboard .dts files including this sopine.dtsi. But this is a bit premature until we actually see a second baseboard, at which point we could still split this up then.
Argh, just saw that I misread defconfig for DT here, sorry. But the argument still stands: the SoPine module itself has only a bit of functionality and is not usable on its own, so any board configuration must be considered as being together with some kind of base board. For instance the eMMC, HDMI socket and Ethernet PHY is not on the SoPine module.
Cheers, Andre.
Hi,
On 26/04/17 15:50, Icenowy Zheng wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
There is some point in this, but I wonder if we actually need to wait for Linux. In fact since the SoPine has SPI flash, we don't desperately need a DT in the Linux source tree, since it could just come with the device - as in U-Boot's DT passed through to the kernel.
So can we have a separate DT, probably including -pine64.dts and at least adding the eMMC? Could be copy&paste version of the BPi-M64, for instance.
One more below ....
Signed-off-by: Icenowy Zheng icenowy@aosc.io
configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig new file mode 100644 index 0000000000..02ffb43d54 --- /dev/null +++ b/configs/sopine_baseboard_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y
Can you add the SPL SPI flash options here? This allows loading U-Boot from SPI flash and makes this much more useful.
Cheers, Andre.
在 2017-06-03 09:19，André Przywara 写道：
Hi,
On 26/04/17 15:50, Icenowy Zheng wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).
The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.
Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.
There is some point in this, but I wonder if we actually need to wait for Linux. In fact since the SoPine has SPI flash, we don't desperately need a DT in the Linux source tree, since it could just come with the device - as in U-Boot's DT passed through to the kernel.
So can we have a separate DT, probably including -pine64.dts and at least adding the eMMC? Could be copy&paste version of the BPi-M64, for instance.
In fact changing the defconfig is now enough to initialize the MMC2 controller.
See "CONFIG_MMC_SUNXI_SLOT_EXTRA=2" below.
One more below ....
Signed-off-by: Icenowy Zheng icenowy@aosc.io
configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 configs/sopine_baseboard_defconfig
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig new file mode 100644 index 0000000000..02ffb43d54 --- /dev/null +++ b/configs/sopine_baseboard_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y
Can you add the SPL SPI flash options here? This allows loading U-Boot from SPI flash and makes this much more useful.
Yes, seems useful...
Cheers, Andre.
Hi,
On Wed, Apr 26, 2017 at 10:49:55PM +0800, Icenowy Zheng wrote:
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
All those changes looks good to me. I'll wait for Jens' review however, since he knows that part much more than I do.
Thanks! Maxime
在 2017-04-27 15:09，Maxime Ripard 写道：
Hi,
On Wed, Apr 26, 2017 at 10:49:55PM +0800, Icenowy Zheng wrote:
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
All those changes looks good to me. I'll wait for Jens' review however, since he knows that part much more than I do.
It seems that Jens haven't appeared for several months...
I grep'ed my local IRC log, and his latest appearance is in March.
After then he's still in the people list, however he haven't said anything since March.
The IRC client of him seems to be running on a VPS, so it's always online.
Jens, can you see this?
Thanks! Maxime
-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
On Sat, May 27, 2017 at 12:50:03AM +0800, icenowy@aosc.io wrote:
在 2017-04-27 15:09，Maxime Ripard 写道：
Hi,
On Wed, Apr 26, 2017 at 10:49:55PM +0800, Icenowy Zheng wrote:
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
All those changes looks good to me. I'll wait for Jens' review however, since he knows that part much more than I do.
It seems that Jens haven't appeared for several months...
I grep'ed my local IRC log, and his latest appearance is in March.
After then he's still in the people list, however he haven't said anything since March.
The IRC client of him seems to be running on a VPS, so it's always online.
Since he hasn't replied for quite some time, let's merge it, this is always something we can fix later on.
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Jagan, can you apply this serie?
Thanks! Maxime
On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng icenowy@aosc.io wrote:
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
Icenowy Zheng (12): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code sunxi: Add selective DRAM type and timing sunxi: enable dual rank detection in DesignWare-like DRAM code sunxi: add support for the DDR2 in V3s SoC sunxi: add support for V3s DRAM controller sunxi: enable DRAM initialization and SPL for V3s SoC sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller sunxi: add LPDDR3 timing from stock boot0 sunxi: add a defconfig for SoPine w/ official baseboard
Can you rebase on master and sen it again, difficult to fix the things while applying.
thanks!
On 02/06/17 19:34, Jagan Teki wrote:
On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng icenowy@aosc.io wrote:
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
Icenowy Zheng (12): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code sunxi: Add selective DRAM type and timing sunxi: enable dual rank detection in DesignWare-like DRAM code sunxi: add support for the DDR2 in V3s SoC sunxi: add support for V3s DRAM controller sunxi: enable DRAM initialization and SPL for V3s SoC sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller sunxi: add LPDDR3 timing from stock boot0 sunxi: add a defconfig for SoPine w/ official baseboard
Can you rebase on master and sen it again, difficult to fix the things while applying.
... maybe on the way fix the minor things I mentioned in the lower part of my reply to 11/12? https://lists.denx.de/pipermail/u-boot/2017-May/290436.html
Cheers, Andre.
participants (5)
-
André Przywara -
Icenowy Zheng -
icenowy＠aosc.io
-
Jagan Teki -
Maxime Ripard