Because stgen is initialized with HSI clock, we need to recalculate the counter when changing frequency.

Signed-off-by: Lionel Debieve lionel.debieve@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

drivers/clk/clk_stm32mp1.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 5f2b2f1..ca98e0b 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -1471,10 +1471,15 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) rate = stm32mp1_clk_get(priv, p);

if (cntfid0 != rate) { + u64 counter; + pr_debug("System Generic Counter (STGEN) update\n"); clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); - writel(0x0, stgenc + STGENC_CNTCVL); - writel(0x0, stgenc + STGENC_CNTCVU); + counter = (u64)readl(stgenc + STGENC_CNTCVL); + counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; + counter = lldiv(counter * (u64)rate, cntfid0); + writel((u32)counter, stgenc + STGENC_CNTCVL); + writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); writel(rate, stgenc + STGENC_CNTFID0); setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);

Add support of clk dump command and display information during probe (under CONFIG_DISPLAY_CPUINFO).

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + drivers/clk/clk_stm32mp1.c | 83 +++++++++++++++++++++++++++++++++++-- 3 files changed, 81 insertions(+), 4 deletions(-)

diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 304688e..d20b2ab 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index e905ae1..62ab010 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index ca98e0b..76b7b5a 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -668,8 +668,8 @@ static const u8 stm32mp1_axi_div[8] = { 1, 2, 3, 4, 4, 4, 4, 4 };

-#ifdef DEBUG -static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_HSI] = "HSI", [_HSE] = "HSE", [_CSI] = "CSI", @@ -707,7 +707,8 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_DSI_PHY] = "DSI_PHY_PLL", };

-static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_I2C12_SEL] = "I2C12", [_I2C35_SEL] = "I2C35", [_I2C46_SEL] = "I2C46", @@ -726,7 +727,6 @@ static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_DSI_SEL] = "DSI", [_ADC12_SEL] = "ADC12", }; -#endif

static const struct stm32mp1_clk_data stm32mp1_data = { .gate = stm32mp1_clk_gate, @@ -1872,6 +1872,54 @@ static void stm32mp1_osc_init(struct udevice *dev) } }

+static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) +{ + char buf[32]; + int i, s, p; + + printf("Clocks:\n"); + for (i = 0; i < _PARENT_NB; i++) { + printf("- %s : %s MHz\n", + stm32mp1_clk_parent_name[i], + strmhz(buf, stm32mp1_clk_get(priv, i))); + } + printf("Source Clocks:\n"); + for (i = 0; i < _PARENT_SEL_NB; i++) { + p = (readl(priv->base + priv->data->sel[i].offset) >> + priv->data->sel[i].src) & priv->data->sel[i].msk; + if (p < priv->data->sel[i].nb_parent) { + s = priv->data->sel[i].parent[p]; + printf("- %s(%d) => parent %s(%d)\n", + stm32mp1_clk_parent_sel_name[i], i, + stm32mp1_clk_parent_name[s], s); + } else { + printf("- %s(%d) => parent index %d is invalid\n", + stm32mp1_clk_parent_sel_name[i], i, p); + } + } +} + +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ + struct udevice *dev; + struct stm32mp1_clk_priv *priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(stm32mp1_clock), + &dev); + if (ret) + return ret; + + priv = dev_get_priv(dev); + + stm32mp1_clk_dump(priv); + + return 0; +} +#endif + static int stm32mp1_clk_probe(struct udevice *dev) { int result = 0; @@ -1895,6 +1943,33 @@ static int stm32mp1_clk_probe(struct udevice *dev) result = stm32mp1_clktree(dev); #endif

+#ifndef CONFIG_SPL_BUILD +#if defined(DEBUG) + /* display debug information for probe after relocation */ + if (gd->flags & GD_FLG_RELOC) + stm32mp1_clk_dump(priv); +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) + if (gd->flags & GD_FLG_RELOC) { + char buf[32]; + + printf("Clocks:\n"); + printf("- MPU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU))); + printf("- MCU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); + printf("- AXI : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _ACLK))); + printf("- PER : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); + /* DDRPHYC father */ + printf("- DDR : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R))); + } +#endif /* CONFIG_DISPLAY_CPUINFO */ +#endif + return result; }

- Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 27 +++++++++++++++------------ include/dt-bindings/clock/stm32mp1-clks.h | 3 --- 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 4898483..70bbf66 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -39,6 +39,10 @@ }; };

+&clk_hse { + st,digbypass; +}; + &uart4_pins_a { u-boot,dm-pre-reloc; pins1 { @@ -68,7 +72,6 @@ u-boot,dm-pre-reloc; };

-/* CLOCK init */ &rcc { st,clksrc = < CLK_MPU_PLL1P @@ -101,7 +104,7 @@ CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED - CLK_SDMMC12_PLL3R + CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE @@ -110,7 +113,7 @@ CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI - CLK_SDMMC3_PLL3R + CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE @@ -121,17 +124,17 @@ CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI - CLK_SPDIF_PLL3Q + CLK_SPDIF_PLL4P CLK_FDCAN_PLL4Q CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q - CLK_RNG1_CSI - CLK_RNG2_CSI + CLK_RNG1_LSI + CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 - CLK_LPTIM45_PCLK3 + CLK_LPTIM45_LSE >;

/* VCO = 1300.0 MHz => P = 650 (CPU) */ @@ -148,16 +151,16 @@ u-boot,dm-pre-reloc; };

- /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { - cfg = < 2 97 3 15 7 PQR(1,1,1) >; - frac = < 0x9ba >; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; u-boot,dm-pre-reloc; };

- /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { - cfg = < 5 126 8 8 8 PQR(1,1,1) >; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 90ec780..4cdaf13 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,7 +248,4 @@

#define STM32MP1_LAST_CLK 232

-#define LTDC_K LTDC_PX -#define ETHMAC_K ETHCK_K - #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable.

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 +++++----- drivers/clk/clk_stm32mp1.c | 8 +++++++- 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e..ffcf8cd 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -132,15 +132,15 @@ Optional Properties: frac = < 0x810 >; }; st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; }; st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; }; st,pll@3 { - cfg = < 2 78 4 7 9 3>; + cfg = < 2 78 4 7 9 3 >; }; st,pkcs = < CLK_STGEN_HSE diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 76b7b5a..24859fd 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -167,6 +167,7 @@ /* used for ALL PLLNCR registers */ #define RCC_PLLNCR_PLLON BIT(0) #define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) #define RCC_PLLNCR_DIVPEN BIT(4) #define RCC_PLLNCR_DIVQEN BIT(5) #define RCC_PLLNCR_DIVREN BIT(6) @@ -1321,7 +1322,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) { const struct stm32mp1_clk_pll *pll = priv->data->pll;

- writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); + clrsetbits_le32(priv->base + pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); }

static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) @@ -1440,6 +1444,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) RCC_PLLNCSGR_SSCG_MODE_MASK);

writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); + + setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); }

static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)