[U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 09337a1..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -220,11 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31)
-#if defined CONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ -#endif
#define AXI_GATE_OFFSET_DRAM 0
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com
I suppose you've tested this on at least one such board? In that case: Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 09337a1..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -220,11 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31)
-#if defined CONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ -#endif
#define AXI_GATE_OFFSET_DRAM 0
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell ijc+uboot@hellion.org.uk wrote:
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com
I suppose you've tested this on at least one such board? In that case: Acked-by: Ian Campbell ijc@hellion.org.uk
I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which I haven't looked into yet.
ChenYu
Hi,
On 22-11-15 15:14, Chen-Yu Tsai wrote:
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell ijc+uboot@hellion.org.uk wrote:
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com
I suppose you've tested this on at least one such board? In that case: Acked-by: Ian Campbell ijc@hellion.org.uk
I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which I haven't looked into yet.
Works for me on a q8 A33 tablet. But lets investigate your oops before including this in the next pull-req. Thanks for the testing!
Regards,
Hans
Hi,
On Sun, Nov 22, 2015 at 11:40 PM, Hans de Goede hdegoede@redhat.com wrote:
Hi,
On 22-11-15 15:14, Chen-Yu Tsai wrote:
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell ijc+uboot@hellion.org.uk wrote:
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com
I suppose you've tested this on at least one such board? In that case: Acked-by: Ian Campbell ijc@hellion.org.uk
I've tested this on some of my boards. It works fine on my Hummingbird A31 and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which I haven't looked into yet.
Works for me on a q8 A33 tablet. But lets investigate your oops before including this in the next pull-req. Thanks for the testing!
I retested it with a proper clean build, and it works now. No idea what the oops was about.
Also tested on my Sinlinx SinA31s. So it now works on all my sun6i generation boards.
Tested-by: Chen-Yu Tsai wens@csie.org
On Mon, 2015-11-23 at 14:47 +0800, Chen-Yu Tsai wrote:
Hi,
On Sun, Nov 22, 2015 at 11:40 PM, Hans de Goede hdegoede@redhat.com wrote:
Hi,
On 22-11-15 15:14, Chen-Yu Tsai wrote:
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <
ijc+uboot@hellion.org.uk>
wrote:
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com
I suppose you've tested this on at least one such board? In that
case:
Acked-by: Ian Campbell ijc@hellion.org.uk
I've tested this on some of my boards. It works fine on my
Hummingbird A31
and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel
Oops
which I haven't looked into yet.
Works for me on a q8 A33 tablet. But lets investigate your oops
before
including this in the next pull-req. Thanks for the testing!
I retested it with a proper clean build, and it works now. No idea what the oops was about.
Also tested on my Sinlinx SinA31s. So it now works on all my sun6i generation boards.
Tested-by: Chen-Yu Tsai wens@csie.org
Good enough for me, my original Ack stands...
participants (3)
-
Chen-Yu Tsai -
Hans de Goede -
Ian Campbell