[PATCH 1/2] clk: stm32f: fix setting of division factor for LCD_CLK
The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com ---
drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef0..4c1864193357 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate; }
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple of the pixel clock rate. Otherwise, we search through all combinations of pllsaidivr * pllsair and use the one which gives the rate closest to requested one.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com
---
drivers/clk/stm32/clk-stm32f.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index 4c1864193357..d68c75ed2013 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
/* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); - best_div = pllsair_rate / rate; - - /* look into pllsaidivr_table if this divider is available*/ - for (i = 0 ; i < sizeof(pllsaidivr_table); i++) - if (best_div == pllsaidivr_table[i]) { - /* set pll_saidivr with found value */ - clrsetbits_le32(®s->dckcfgr, - RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i] << - RCC_DCKCFGR_PLLSAIDIVR_SHIFT); - return rate; - } + if ((pllsair_rate % rate) == 0) { + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available */ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + return rate; + } + }
/* * As no pllsaidivr value is suitable to obtain requested freq,
On 11/11/23 11:46, Dario Binacchi wrote:
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple of the pixel clock rate. Otherwise, we search through all combinations of pllsaidivr * pllsair and use the one which gives the rate closest to requested one.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com
drivers/clk/stm32/clk-stm32f.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index 4c1864193357..d68c75ed2013 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
/* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
- best_div = pllsair_rate / rate;
- /* look into pllsaidivr_table if this divider is available*/
- for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
if (best_div == pllsaidivr_table[i]) {/* set pll_saidivr with found value */clrsetbits_le32(®s->dckcfgr,RCC_DCKCFGR_PLLSAIDIVR_MASK,pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT);return rate;}
if ((pllsair_rate % rate) == 0) {
best_div = pllsair_rate / rate;/* look into pllsaidivr_table if this divider is available */for (i = 0 ; i < sizeof(pllsaidivr_table); i++)if (best_div == pllsaidivr_table[i]) {/* set pll_saidivr with found value */clrsetbits_le32(®s->dckcfgr,RCC_DCKCFGR_PLLSAIDIVR_MASK,pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT);return rate;}}
/*
- As no pllsaidivr value is suitable to obtain requested freq,
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com Thanks Patrice
On 11/11/23 11:46, Dario Binacchi wrote:
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple of the pixel clock rate. Otherwise, we search through all combinations of pllsaidivr * pllsair and use the one which gives the rate closest to requested one.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com
drivers/clk/stm32/clk-stm32f.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index 4c1864193357..d68c75ed2013 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
/* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
- best_div = pllsair_rate / rate;
- /* look into pllsaidivr_table if this divider is available*/
- for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
if (best_div == pllsaidivr_table[i]) {/* set pll_saidivr with found value */clrsetbits_le32(®s->dckcfgr,RCC_DCKCFGR_PLLSAIDIVR_MASK,pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT);return rate;}
if ((pllsair_rate % rate) == 0) {
best_div = pllsair_rate / rate;/* look into pllsaidivr_table if this divider is available */for (i = 0 ; i < sizeof(pllsaidivr_table); i++)if (best_div == pllsaidivr_table[i]) {/* set pll_saidivr with found value */clrsetbits_le32(®s->dckcfgr,RCC_DCKCFGR_PLLSAIDIVR_MASK,pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT);return rate;}}
/*
- As no pllsaidivr value is suitable to obtain requested freq,
Applied to u-boot-stm32/next
Thanks Patrice
On 11/11/23 11:46, Dario Binacchi wrote:
The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com
drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef0..4c1864193357 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
pllsaidivr_table[i]);
pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate;
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 11/11/23 11:46, Dario Binacchi wrote:
The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com
drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef0..4c1864193357 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
pllsaidivr_table[i]);
pllsaidivr_table[i] <<RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate;
Applied to u-boot-stm32/next
Thanks Patrice
participants (2)
-
Dario Binacchi -
Patrice CHOTARD