On Thu, 24 Jun 2010 19:00:54 -0500 Kim Phillips kim.phillips@freescale.com wrote:

On Thu, 24 Jun 2010 23:36:49 +0400 Ilya Yanok yanok@emcraft.com wrote:

...

Hi Kim,

On 24.06.2010 22:00, Kim Phillips wrote:

...

...

I've enabled icache and now the board sometimes resets twice after U-Boot 'reset' command:

...

(It doesn't always stop at "DRAM:" line but that position is most frequent) Maybe you have some ideas on this subject?

hmm, if it's only on soft-resets, can you try adding HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to _FINAL? Some cache state is preserved over a soft-reset...

Thanks for your advice but this doesn't help...

turning icache on early causes a different pattern of bus accesses when fetching code, and this might trigger bus accesses that interfere with code that sets bus configuration registers, such as the acr. Can you test this patch please?:

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 15e2c18..613625d 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -36,6 +36,7 @@ COBJS-y += speed.o COBJS-y += interrupts.o COBJS-y += spd_sdram.o COBJS-y += ecc.o +COBJS-y += acr.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_FSL_SERDES) += serdes.o COBJS-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc83xx/acr.c b/arch/powerpc/cpu/mpc83xx/acr.c new file mode 100644 index 0000000..20315fc --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/acr.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +void single_cline_write(volatile void *addr, __be32 val) +{ + out_be32(addr, val); +} diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 83cba93..237fa48 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -30,6 +30,8 @@

DECLARE_GLOBAL_DATA_PTR;

+extern void single_cline_write(volatile void *addr, __be32 val); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -63,6 +65,7 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { + __be32 val; __be32 acr_mask = #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ ACR_PIPE_DEP | @@ -213,7 +216,8 @@ void cpu_init_f (volatile immap_t * im) memset ((void *) gd, 0, sizeof (gd_t));

/* system performance tweaking */ - clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); + val = __raw_readl(&im->arbiter.acr); + single_cline_write(&im->arbiter.acr, acr_val & (val & ~acr_mask));

clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);

diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 0b74a13..f01c462 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -51,6 +51,8 @@ SECTIONS .text : { arch/powerpc/cpu/mpc83xx/start.o (.text) + . = ALIGN(32); + arch/powerpc/cpu/mpc83xx/acr.o (.text) *(.text) *(.got1) . = ALIGN(16);

Thanks,

Kim