[PATCH 0/6] J2700: Enable various peripherals
Enable USB, HyperFlasha and CPSW on J7200 SoC
Based on top of https://patchwork.ozlabs.org/project/uboot/list/?series=194305
Vignesh Raghavendra (6): arm: dts: k3-j7200: Add USB related DT entries board: ti: j721e: Add support for HyperFlash detection ARM: dts: k3-j7200: Add wkup gpio node ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
.../k3-j7200-common-proc-board-u-boot.dtsi | 29 ++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 72 ++++++++ arch/arm/dts/k3-j7200-main.dtsi | 30 ++++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 155 ++++++++++++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 18 ++ arch/arm/dts/k3-j7200-som-p0.dtsi | 33 ++++ arch/arm/dts/k3-j7200.dtsi | 6 +- board/ti/j721e/evm.c | 30 ++++ 8 files changed, 371 insertions(+), 2 deletions(-)
Add USB related DT entries to enable USB device mode.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- .../k3-j7200-common-proc-board-u-boot.dtsi | 14 +++++++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 18 +++++++++++ arch/arm/dts/k3-j7200-main.dtsi | 30 +++++++++++++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 18 +++++++++++ 4 files changed, 80 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 10bb069492..4dca59cefa 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -102,3 +102,17 @@ &exp2 { u-boot,dm-spl; }; + +&main_usbss0_pins_default { + u-boot,dm-spl; +}; + +&usbss0 { + u-boot,dm-spl; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "peripheral"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 537ef2a79d..969881fb83 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -30,6 +30,12 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + >; + }; };
&wkup_uart0 { @@ -121,3 +127,15 @@ #gpio-cells = <2>; }; }; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index f3df5d8f10..aaa1fdd5a3 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -310,4 +310,34 @@ clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; }; + + usbss0: cdns_usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; + clock-names = "usb2_refclk", "lpm_clk"; + assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index ffd0d09ece..f5e4166926 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -129,6 +129,12 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + >; + }; };
&wkup_uart0 { @@ -196,4 +202,16 @@ }; };
+&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + #include "k3-j7200-common-proc-board-u-boot.dtsi"
On J7200 SoC OSPI0 and HypeFlash are muxed at HW level and only one of them can be used at any time. J7200 EVM has both HyperFlash and OSPI flash on board. There is a user switch (SW3.1) that can be toggled to select OSPI flash vs HyperFlash. Read the state of this switch via wkup_gpio0_6 line and fixup the DT nodes to select OSPI0 vs HyperFlash
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- board/ti/j721e/evm.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 87cdbf9798..66ed3750e3 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -89,6 +89,34 @@ int board_fit_config_name_match(const char *name) } #endif
+#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_LIBFDT) +/* Returns 1, if onboard mux is set to hyperflash */ +static void __maybe_unused detect_enable_hyperflash(void *blob) +{ + struct gpio_desc desc = {0}; + + if (dm_gpio_lookup_name("6", &desc)) + return; + + if (dm_gpio_request(&desc, "6")) + return; + + if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) + return; + + if (dm_gpio_get_value(&desc)) { + int offset; + + do_fixup_by_compat(blob, "ti,am654-hbmc", "status", + "okay", sizeof("okay"), 0); + offset = fdt_node_offset_by_compatible(blob, -1, + "ti,j721e-ospi"); + fdt_setprop(blob, offset, "status", "disabled", + sizeof("disabled")); + } +} +#endif + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { @@ -101,6 +129,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (ret) printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+ detect_enable_hyperflash(blob); + return ret; } #endif
Add wkup_gpio0 node required for detecting whether board mux is set HyperFlash.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/dts/k3-j7200-common-proc-board.dts | 11 +++++++++++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 12 ++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 969881fb83..15ac3cb6b3 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -21,6 +21,12 @@ J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; };
&main_pmx0 { @@ -139,3 +145,8 @@ dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 4bcb65aace..d590079382 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -114,4 +114,16 @@ clocks = <&k3_clks 195 1>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; }; + + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x0 0x42110000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + ti,ngpio = <84>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; };
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT entries for the same.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 27 ++++++++++++++++++++++ arch/arm/dts/k3-j7200-som-p0.dtsi | 33 +++++++++++++++++++++++++++ arch/arm/dts/k3-j7200.dtsi | 6 +++-- 3 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index d590079382..8ea25dea88 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -93,6 +93,33 @@ clock-names = "fclk"; };
+ fss: system-controller@47000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x47000000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hbmc_mux: hbmc-mux { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x0 0x47034000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + clocks = <&k3_clks 102 5>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + }; + }; + mcu_i2c0: i2c@40b00000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x0 0x40b00000 0x0 0x100>; diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi index 22fc50bd5c..ea5280ded7 100644 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi @@ -27,3 +27,36 @@ }; }; }; + +&wkup_pmx0 { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; +}; + +&hbmc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi index 7b2313dcab..126c31bac7 100644 --- a/arch/arm/dts/k3-j7200.dtsi +++ b/arch/arm/dts/k3-j7200.dtsi @@ -149,7 +149,8 @@ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 { compatible = "simple-bus"; @@ -165,7 +166,8 @@ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; /* FSS OSPI0/1 data region 0 */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */ }; }; };
Add MCU NAVSS, UDMA and CPSW2G DT nodes.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 116 ++++++++++++++++++++++++++ 1 file changed, 116 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 8ea25dea88..4c899c8aca 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -142,6 +142,49 @@ power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; };
+ cbass_mcu_navss: mcu-navss { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; + wkup_gpio0: gpio@42110000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x0 0x42110000 0x0 0x100>; @@ -153,4 +196,77 @@ clocks = <&k3_clks 113 0>; clock-names = "gpio"; }; + + mcu_conf: scm_conf@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-cpsw-phy-sel"; + reg = <0x4040 0x4>; + reg-names = "gmii-sel"; + #phy-cells = <1>; + }; + }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges; + dma-coherent; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + ti,label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts { + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; };
Enable CPSW2G port to support networking in U-Boot
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- .../k3-j7200-common-proc-board-u-boot.dtsi | 15 +++++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 43 +++++++++++++++++++ 2 files changed, 58 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 4dca59cefa..4972a7559f 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -9,6 +9,9 @@ tick-timer = &timer1; };
+ aliases { + ethernet0 = &cpsw_port1; + }; };
&chipid { @@ -103,6 +106,18 @@ u-boot,dm-spl; };
+&mcu_cpsw { + reg = <0x0 0x46000000 0x0 0x200000>, + <0x0 0x40f00200 0x0 0x8>; + reg-names = "cpsw_nuss", "mac_efuse"; + + cpsw-phy-sel@40f04040 { + compatible = "ti,am654-cpsw-phy-sel"; + reg= <0x0 0x40f04040 0x0 0x4>; + reg-names = "gmii-sel"; + }; +}; + &main_usbss0_pins_default { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 15ac3cb6b3..3f1d03c960 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/net/ti-dp83867.h> #include "k3-j7200-som-p0.dtsi"
/ { @@ -27,6 +28,30 @@ J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; }; + + mcu_cpsw_pins_default: mcu_cpsw_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu_mdio1_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; };
&main_pmx0 { @@ -150,3 +175,21 @@ pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};
On 06/08/2020 21:56, Vignesh Raghavendra wrote:
Enable USB, HyperFlasha and CPSW on J7200 SoC
Based on top of https://patchwork.ozlabs.org/project/uboot/list/?series=194305
Vignesh Raghavendra (6): arm: dts: k3-j7200: Add USB related DT entries board: ti: j721e: Add support for HyperFlash detection ARM: dts: k3-j7200: Add wkup gpio node ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
.../k3-j7200-common-proc-board-u-boot.dtsi | 29 ++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 72 ++++++++ arch/arm/dts/k3-j7200-main.dtsi | 30 ++++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 155 ++++++++++++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 18 ++ arch/arm/dts/k3-j7200-som-p0.dtsi | 33 ++++ arch/arm/dts/k3-j7200.dtsi | 6 +- board/ti/j721e/evm.c | 30 ++++ 8 files changed, 371 insertions(+), 2 deletions(-)
Reviewed-by: Grygorii Strashko grygorii.strashko@ti.com
On 07/08/20 12:26 am, Vignesh Raghavendra wrote:
Enable USB, HyperFlasha and CPSW on J7200 SoC
$subject: s/J2700/J7200 :)
Thanks and regards, Lokesh
Based on top of https://patchwork.ozlabs.org/project/uboot/list/?series=194305
Vignesh Raghavendra (6): arm: dts: k3-j7200: Add USB related DT entries board: ti: j721e: Add support for HyperFlash detection ARM: dts: k3-j7200: Add wkup gpio node ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G support arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
.../k3-j7200-common-proc-board-u-boot.dtsi | 29 ++++ arch/arm/dts/k3-j7200-common-proc-board.dts | 72 ++++++++ arch/arm/dts/k3-j7200-main.dtsi | 30 ++++ arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 155 ++++++++++++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 18 ++ arch/arm/dts/k3-j7200-som-p0.dtsi | 33 ++++ arch/arm/dts/k3-j7200.dtsi | 6 +- board/ti/j721e/evm.c | 30 ++++ 8 files changed, 371 insertions(+), 2 deletions(-)
On 07/08/20 12:26 am, Vignesh Raghavendra wrote:
Enable USB, HyperFlasha and CPSW on J7200 SoC
Based on top of https://patchwork.ozlabs.org/project/uboot/list/?series=194305
Applied to u-boot-ti
Thanks and regards, Lokesh
participants (3)
-
Grygorii Strashko -
Lokesh Vutla -
Vignesh Raghavendra