[U-Boot] [PATCH 1/8] MX28: Fix a typo in mx28_reg_8 macro

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[U-Boot] [PATCH 1/3] m28evk: use...

Otavio Salvador

11 May 2012 11 May '12

5:37 p.m.

The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Marek Vasut marex@denx.de --- arch/arm/include/asm/arch-mx28/regs-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 94b512d..d2e1953 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -70,7 +70,7 @@ struct mx28_register_32 { #define mx28_reg_8(name) \ union { \ struct { __mx28_reg_8(name) }; \ - struct mx28_register_32 name##_reg; \ + struct mx28_register_8 name##_reg; \ };

#define mx28_reg_32(name) \

-- 1.7.10

Show replies by date

Otavio Salvador

11 May 11 May

5:38 p.m.

New subject: [U-Boot] [PATCH 2/8] m28evk: use same notation to alloc the 128kB stack

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- include/configs/m28evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index c62f4d0..7472ddc 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -88,7 +88,7 @@ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */

-- 1.7.10

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 3/8] m28evk: use "M28EVK U-Boot =>" as prompt

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- include/configs/m28evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 7472ddc..ebf7e39 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -114,7 +114,7 @@ * U-Boot general configurations */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PROMPT "M28EVK U-Boot => " #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

-- 1.7.10

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 4/8] mx28evk: ensure command definition is in alphabetic order

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- include/configs/mx28evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 0c18e50..5ccfe70 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -54,11 +54,11 @@ #include <config_cmd_default.h> #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT

#define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_MII #define CONFIG_CMD_MMC

-- 1.7.10

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 5/8] mxsboot: stop referring to i.MX28 as this ought to work for all i.MXS SoCs

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- tools/mxsboot.c | 110 +++++++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 55 deletions(-)

diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 6c05aa4..9661a48 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -1,5 +1,5 @@ /* - * Freescale i.MX28 image generator + * Freescale i.MXS image generator * * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com * on behalf of DENX Software Engineering GmbH @@ -60,13 +60,13 @@ uint32_t sd_sector = 2048; */ #define MAX_BOOTSTREAM_SIZE (1 * 1024 * 1024)

-/* i.MX28 NAND controller-specific constants. DO NOT TWEAK! */ +/* i.MXS NAND controller-specific constants. DO NOT TWEAK! */ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 #define MXS_NAND_METADATA_SIZE 10 #define MXS_NAND_COMMAND_BUFFER_SIZE 32

-struct mx28_nand_fcb { +struct mxs_nand_fcb { uint32_t checksum; uint32_t fingerprint; uint32_t version; @@ -111,7 +111,7 @@ struct mx28_nand_fcb { uint32_t bb_marker_physical_offset; };

-struct mx28_nand_dbbt { +struct mxs_nand_dbbt { uint32_t checksum; uint32_t fingerprint; uint32_t version; @@ -119,13 +119,13 @@ struct mx28_nand_dbbt { uint32_t number_2k_pages_bb; };

-struct mx28_nand_bbt { +struct mxs_nand_bbt { uint32_t nand; uint32_t number_bb; uint32_t badblock[510]; };

-struct mx28_sd_drive_info { +struct mxs_sd_drive_info { uint32_t chip_num; uint32_t drive_type; uint32_t tag; @@ -133,20 +133,20 @@ struct mx28_sd_drive_info { uint32_t sector_count; };

-struct mx28_sd_config_block { +struct mxs_sd_config_block { uint32_t signature; uint32_t primary_boot_tag; uint32_t secondary_boot_tag; uint32_t num_copies; - struct mx28_sd_drive_info drv_info[1]; + struct mxs_sd_drive_info drv_info[1]; };

-static inline uint32_t mx28_nand_ecc_size_in_bits(uint32_t ecc_strength) +static inline uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) { return ecc_strength * 13; }

-static inline uint32_t mx28_nand_get_ecc_strength(uint32_t page_data_size, +static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { if (page_data_size == 2048) @@ -163,7 +163,7 @@ static inline uint32_t mx28_nand_get_ecc_strength(uint32_t page_data_size, return 0; }

-static inline uint32_t mx28_nand_get_mark_offset(uint32_t page_data_size, +static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, uint32_t ecc_strength) { uint32_t chunk_data_size_in_bits; @@ -174,7 +174,7 @@ static inline uint32_t mx28_nand_get_mark_offset(uint32_t page_data_size, uint32_t block_mark_bit_offset;

chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8; - chunk_ecc_size_in_bits = mx28_nand_ecc_size_in_bits(ecc_strength); + chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);

chunk_total_size_in_bits = chunk_data_size_in_bits + chunk_ecc_size_in_bits; @@ -212,21 +212,21 @@ static inline uint32_t mx28_nand_get_mark_offset(uint32_t page_data_size, return block_mark_bit_offset; }

-static inline uint32_t mx28_nand_mark_byte_offset(void) +static inline uint32_t mxs_nand_mark_byte_offset(void) { uint32_t ecc_strength; - ecc_strength = mx28_nand_get_ecc_strength(nand_writesize, nand_oobsize); - return mx28_nand_get_mark_offset(nand_writesize, ecc_strength) >> 3; + ecc_strength = mxs_nand_get_ecc_strength(nand_writesize, nand_oobsize); + return mxs_nand_get_mark_offset(nand_writesize, ecc_strength) >> 3; }

-static inline uint32_t mx28_nand_mark_bit_offset(void) +static inline uint32_t mxs_nand_mark_bit_offset(void) { uint32_t ecc_strength; - ecc_strength = mx28_nand_get_ecc_strength(nand_writesize, nand_oobsize); - return mx28_nand_get_mark_offset(nand_writesize, ecc_strength) & 0x7; + ecc_strength = mxs_nand_get_ecc_strength(nand_writesize, nand_oobsize); + return mxs_nand_get_mark_offset(nand_writesize, ecc_strength) & 0x7; }

-static uint32_t mx28_nand_block_csum(uint8_t *block, uint32_t size) +static uint32_t mxs_nand_block_csum(uint8_t *block, uint32_t size) { uint32_t csum = 0; int i; @@ -237,9 +237,9 @@ static uint32_t mx28_nand_block_csum(uint8_t *block, uint32_t size) return csum ^ 0xffffffff; }

-static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size) +static struct mxs_nand_fcb *mxs_nand_get_fcb(uint32_t size) { - struct mx28_nand_fcb *fcb; + struct mxs_nand_fcb *fcb; uint32_t bcb_size_bytes; uint32_t stride_size_bytes; uint32_t bootstream_size_pages; @@ -248,7 +248,7 @@ static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size)

fcb = malloc(nand_writesize); if (!fcb) { - printf("MX28 NAND: Unable to allocate FCB\n"); + printf("MXS NAND: Unable to allocate FCB\n"); return NULL; }

@@ -289,15 +289,15 @@ static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size) }

if (fcb->ecc_block_n_ecc_type == 0) { - printf("MX28 NAND: Unsupported NAND geometry\n"); + printf("MXS NAND: Unsupported NAND geometry\n"); goto err; }

fcb->boot_patch = 0; fcb->patch_sectors = 0;

- fcb->badblock_marker_byte = mx28_nand_mark_byte_offset(); - fcb->badblock_marker_start_bit = mx28_nand_mark_bit_offset(); + fcb->badblock_marker_byte = mxs_nand_mark_byte_offset(); + fcb->badblock_marker_start_bit = mxs_nand_mark_bit_offset(); fcb->bb_marker_physical_offset = nand_writesize;

stride_size_bytes = STRIDE_PAGES * nand_writesize; @@ -324,13 +324,13 @@ err: return NULL; }

-static struct mx28_nand_dbbt *mx28_nand_get_dbbt(void) +static struct mxs_nand_dbbt *mxs_nand_get_dbbt(void) { - struct mx28_nand_dbbt *dbbt; + struct mxs_nand_dbbt *dbbt;

dbbt = malloc(nand_writesize); if (!dbbt) { - printf("MX28 NAND: Unable to allocate DBBT\n"); + printf("MXS NAND: Unable to allocate DBBT\n"); return NULL; }

@@ -342,7 +342,7 @@ static struct mx28_nand_dbbt *mx28_nand_get_dbbt(void) return dbbt; }

-static inline uint8_t mx28_nand_parity_13_8(const uint8_t b) +static inline uint8_t mxs_nand_parity_13_8(const uint8_t b) { uint32_t parity = 0, tmp;

@@ -365,7 +365,7 @@ static inline uint8_t mx28_nand_parity_13_8(const uint8_t b) return parity; }

-static uint8_t *mx28_nand_fcb_block(struct mx28_nand_fcb *fcb) +static uint8_t *mxs_nand_fcb_block(struct mxs_nand_fcb *fcb) { uint8_t *block; uint8_t *ecc; @@ -373,36 +373,36 @@ static uint8_t *mx28_nand_fcb_block(struct mx28_nand_fcb *fcb)

block = malloc(nand_writesize + nand_oobsize); if (!block) { - printf("MX28 NAND: Unable to allocate FCB block\n"); + printf("MXS NAND: Unable to allocate FCB block\n"); return NULL; }

memset(block, 0, nand_writesize + nand_oobsize);

/* Update the FCB checksum */ - fcb->checksum = mx28_nand_block_csum(((uint8_t *)fcb) + 4, 508); + fcb->checksum = mxs_nand_block_csum(((uint8_t *)fcb) + 4, 508);

- /* Figure 12-11. in iMX28RM, rev. 1, says FCB is at offset 12 */ - memcpy(block + 12, fcb, sizeof(struct mx28_nand_fcb)); + /* Figure 12-11. in iMXSRM, rev. 1, says FCB is at offset 12 */ + memcpy(block + 12, fcb, sizeof(struct mxs_nand_fcb));

/* ECC is at offset 12 + 512 */ ecc = block + 12 + 512;

/* Compute the ECC parity */ - for (i = 0; i < sizeof(struct mx28_nand_fcb); i++) - ecc[i] = mx28_nand_parity_13_8(block[i + 12]); + for (i = 0; i < sizeof(struct mxs_nand_fcb); i++) + ecc[i] = mxs_nand_parity_13_8(block[i + 12]);

return block; }

-static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) +static int mxs_nand_write_fcb(struct mxs_nand_fcb *fcb, char *buf) { uint32_t offset; uint8_t *fcbblock; int ret = 0; int i;

- fcbblock = mx28_nand_fcb_block(fcb); + fcbblock = mxs_nand_fcb_block(fcb); if (!fcbblock) return -1;

@@ -415,20 +415,20 @@ static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) return ret; }

-static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf) +static int mxs_nand_write_dbbt(struct mxs_nand_dbbt *dbbt, char *buf) { uint32_t offset; int i = STRIDE_PAGES * STRIDE_COUNT;

for (; i < 2 * STRIDE_PAGES * STRIDE_COUNT; i += STRIDE_PAGES) { offset = i * nand_writesize; - memcpy(buf + offset, dbbt, sizeof(struct mx28_nand_dbbt)); + memcpy(buf + offset, dbbt, sizeof(struct mxs_nand_dbbt)); }

return 0; }

-static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, +static int mxs_nand_write_firmware(struct mxs_nand_fcb *fcb, int infd, char *buf) { int ret; @@ -454,7 +454,7 @@ void usage(void) { printf( "Usage: mxsboot [ops] <type> <infile> <outfile>\n" - "Augment BootStream file with a proper header for i.MX28 boot\n" + "Augment BootStream file with a proper header for i.MXS boot\n" "\n" " <type> type of image:\n" " "nand" for NAND image\n" @@ -473,10 +473,10 @@ void usage(void) ); }

-static int mx28_create_nand_image(int infd, int outfd) +static int mxs_create_nand_image(int infd, int outfd) { - struct mx28_nand_fcb *fcb; - struct mx28_nand_dbbt *dbbt; + struct mxs_nand_fcb *fcb; + struct mxs_nand_dbbt *dbbt; int ret = -1; char *buf; int size; @@ -492,31 +492,31 @@ static int mx28_create_nand_image(int infd, int outfd)

memset(buf, 0, size);

- fcb = mx28_nand_get_fcb(MAX_BOOTSTREAM_SIZE); + fcb = mxs_nand_get_fcb(MAX_BOOTSTREAM_SIZE); if (!fcb) { printf("Unable to compile FCB\n"); goto err1; }

- dbbt = mx28_nand_get_dbbt(); + dbbt = mxs_nand_get_dbbt(); if (!dbbt) { printf("Unable to compile DBBT\n"); goto err2; }

- ret = mx28_nand_write_fcb(fcb, buf); + ret = mxs_nand_write_fcb(fcb, buf); if (ret) { printf("Unable to write FCB to buffer\n"); goto err3; }

- ret = mx28_nand_write_dbbt(dbbt, buf); + ret = mxs_nand_write_dbbt(dbbt, buf); if (ret) { printf("Unable to write DBBT to buffer\n"); goto err3; }

- ret = mx28_nand_write_firmware(fcb, infd, buf); + ret = mxs_nand_write_firmware(fcb, infd, buf); if (ret) { printf("Unable to write firmware to buffer\n"); goto err3; @@ -540,14 +540,14 @@ err0: return ret; }

-static int mx28_create_sd_image(int infd, int outfd) +static int mxs_create_sd_image(int infd, int outfd) { int ret = -1; uint32_t *buf; int size; off_t fsize; ssize_t wr_size; - struct mx28_sd_config_block *cb; + struct mxs_sd_config_block *cb;

fsize = lseek(infd, 0, SEEK_END); lseek(infd, 0, SEEK_SET); @@ -565,7 +565,7 @@ static int mx28_create_sd_image(int infd, int outfd) goto err1; }

- cb = (struct mx28_sd_config_block *)buf; + cb = (struct mxs_sd_config_block *)buf;

cb->signature = 0x00112233; cb->primary_boot_tag = 0x1; @@ -675,9 +675,9 @@ int main(int argc, char **argv) }

if (!strcmp(argv[offset], "sd")) - ret = mx28_create_sd_image(infd, outfd); + ret = mxs_create_sd_image(infd, outfd); else if (!strcmp(argv[offset], "nand")) - ret = mx28_create_nand_image(infd, outfd); + ret = mxs_create_nand_image(infd, outfd);

close(outfd); err2:

-- 1.7.10

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 6/8] mxs: reorganize source directory for easy sharing of code among i.MXS SoCs

Most code can be shared amount i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- arch/arm/cpu/arm926ejs/mx28/Makefile | 50 - arch/arm/cpu/arm926ejs/mx28/clock.c | 339 ------- arch/arm/cpu/arm926ejs/mx28/iomux.c | 109 --- arch/arm/cpu/arm926ejs/mx28/mx28.c | 310 ------ arch/arm/cpu/arm926ejs/mx28/mx28_init.h | 45 - arch/arm/cpu/arm926ejs/mx28/spl_boot.c | 135 --- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 242 ----- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 1007 ------------------- arch/arm/cpu/arm926ejs/mx28/start.S | 247 ----- arch/arm/cpu/arm926ejs/mx28/timer.c | 156 --- arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds | 87 -- arch/arm/cpu/arm926ejs/mxs/Makefile | 50 + arch/arm/cpu/arm926ejs/mxs/clock.c | 339 +++++++ arch/arm/cpu/arm926ejs/mxs/iomux.c | 109 +++ arch/arm/cpu/arm926ejs/mxs/mx28.c | 310 ++++++ arch/arm/cpu/arm926ejs/mxs/mx28_init.h | 45 + arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 135 +++ arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 242 +++++ arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 1007 +++++++++++++++++++ arch/arm/cpu/arm926ejs/mxs/start.S | 247 +++++ arch/arm/cpu/arm926ejs/mxs/timer.c | 156 +++ arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 87 ++ arch/arm/include/asm/arch-mx28/clock.h | 61 -- arch/arm/include/asm/arch-mx28/dma.h | 147 --- arch/arm/include/asm/arch-mx28/gpio.h | 32 - arch/arm/include/asm/arch-mx28/imx-regs.h | 42 - arch/arm/include/asm/arch-mx28/iomux-mx28.h | 537 ----------- arch/arm/include/asm/arch-mx28/iomux.h | 168 ---- arch/arm/include/asm/arch-mx28/regs-apbh.h | 466 --------- arch/arm/include/asm/arch-mx28/regs-base.h | 88 -- arch/arm/include/asm/arch-mx28/regs-bch.h | 230 ----- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 294 ------ arch/arm/include/asm/arch-mx28/regs-common.h | 82 -- arch/arm/include/asm/arch-mx28/regs-digctl.h | 155 --- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 222 ----- arch/arm/include/asm/arch-mx28/regs-i2c.h | 207 ---- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 173 ---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 1284 ------------------------- arch/arm/include/asm/arch-mx28/regs-power.h | 413 -------- arch/arm/include/asm/arch-mx28/regs-rtc.h | 147 --- arch/arm/include/asm/arch-mx28/regs-ssp.h | 349 ------- arch/arm/include/asm/arch-mx28/regs-timrot.h | 171 ---- arch/arm/include/asm/arch-mx28/regs-usb.h | 178 ---- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 151 --- arch/arm/include/asm/arch-mx28/sys_proto.h | 74 -- arch/arm/include/asm/arch-mxs/clock.h | 61 ++ arch/arm/include/asm/arch-mxs/dma.h | 147 +++ arch/arm/include/asm/arch-mxs/gpio.h | 32 + arch/arm/include/asm/arch-mxs/imx-regs.h | 42 + arch/arm/include/asm/arch-mxs/iomux-mx28.h | 537 +++++++++++ arch/arm/include/asm/arch-mxs/iomux.h | 168 ++++ arch/arm/include/asm/arch-mxs/regs-apbh.h | 466 +++++++++ arch/arm/include/asm/arch-mxs/regs-base.h | 88 ++ arch/arm/include/asm/arch-mxs/regs-bch.h | 230 +++++ arch/arm/include/asm/arch-mxs/regs-clkctrl.h | 294 ++++++ arch/arm/include/asm/arch-mxs/regs-common.h | 82 ++ arch/arm/include/asm/arch-mxs/regs-digctl.h | 155 +++ arch/arm/include/asm/arch-mxs/regs-gpmi.h | 222 +++++ arch/arm/include/asm/arch-mxs/regs-i2c.h | 207 ++++ arch/arm/include/asm/arch-mxs/regs-ocotp.h | 173 ++++ arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 1284 +++++++++++++++++++++++++ arch/arm/include/asm/arch-mxs/regs-power.h | 413 ++++++++ arch/arm/include/asm/arch-mxs/regs-rtc.h | 147 +++ arch/arm/include/asm/arch-mxs/regs-ssp.h | 349 +++++++ arch/arm/include/asm/arch-mxs/regs-timrot.h | 171 ++++ arch/arm/include/asm/arch-mxs/regs-usb.h | 178 ++++ arch/arm/include/asm/arch-mxs/regs-usbphy.h | 151 +++ arch/arm/include/asm/arch-mxs/sys_proto.h | 74 ++ boards.cfg | 4 +- doc/README.m28 | 2 +- doc/README.mx28evk | 6 +- include/configs/m28evk.h | 4 +- include/configs/mx28evk.h | 4 +- 73 files changed, 8408 insertions(+), 8408 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mx28/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/mx28/clock.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/iomux.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/mx28.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/mx28_init.h delete mode 100644 arch/arm/cpu/arm926ejs/mx28/spl_boot.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/spl_power_init.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/start.S delete mode 100644 arch/arm/cpu/arm926ejs/mx28/timer.c delete mode 100644 arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds create mode 100644 arch/arm/cpu/arm926ejs/mxs/Makefile create mode 100644 arch/arm/cpu/arm926ejs/mxs/clock.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/iomux.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/mx28.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/mx28_init.h create mode 100644 arch/arm/cpu/arm926ejs/mxs/spl_boot.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/spl_power_init.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/start.S create mode 100644 arch/arm/cpu/arm926ejs/mxs/timer.c create mode 100644 arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds delete mode 100644 arch/arm/include/asm/arch-mx28/clock.h delete mode 100644 arch/arm/include/asm/arch-mx28/dma.h delete mode 100644 arch/arm/include/asm/arch-mx28/gpio.h delete mode 100644 arch/arm/include/asm/arch-mx28/imx-regs.h delete mode 100644 arch/arm/include/asm/arch-mx28/iomux-mx28.h delete mode 100644 arch/arm/include/asm/arch-mx28/iomux.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-apbh.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-base.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-bch.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-clkctrl.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-common.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-digctl.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-gpmi.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-i2c.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-ocotp.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-pinctrl.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-power.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-rtc.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-ssp.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-timrot.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-usb.h delete mode 100644 arch/arm/include/asm/arch-mx28/regs-usbphy.h delete mode 100644 arch/arm/include/asm/arch-mx28/sys_proto.h create mode 100644 arch/arm/include/asm/arch-mxs/clock.h create mode 100644 arch/arm/include/asm/arch-mxs/dma.h create mode 100644 arch/arm/include/asm/arch-mxs/gpio.h create mode 100644 arch/arm/include/asm/arch-mxs/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mxs/iomux-mx28.h create mode 100644 arch/arm/include/asm/arch-mxs/iomux.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-apbh.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-base.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-bch.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-common.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-digctl.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-gpmi.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-i2c.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-ocotp.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-pinctrl.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-power.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-rtc.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-ssp.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-timrot.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-usb.h create mode 100644 arch/arm/include/asm/arch-mxs/regs-usbphy.h create mode 100644 arch/arm/include/asm/arch-mxs/sys_proto.h

diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile deleted file mode 100644 index 674a3af..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = clock.o mx28.o iomux.o timer.o - -ifdef CONFIG_SPL_BUILD -COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o -endif - -SRCS := $(START:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c deleted file mode 100644 index 0439f9c..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/clock.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Freescale i.MX28 clock setup code - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> - -/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */ -#define PLL_FREQ_KHZ 480000 -#define PLL_FREQ_COEF 18 -/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */ -#define XTAL_FREQ_KHZ 24000 - -#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) -#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) - -static uint32_t mx28_get_pclk(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); - - /* No support of fractional divider calculation */ - if (clkctrl & - (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) { - return 0; - } - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) { - div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> - CLKCTRL_CPU_DIV_XTAL_OFFSET; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -static uint32_t mx28_get_hclk(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t div; - uint32_t clkctrl; - - clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); - - /* No support of fractional divider calculation */ - if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) - return 0; - - div = clkctrl & CLKCTRL_HBUS_DIV_MASK; - return mx28_get_pclk() / div; -} - -static uint32_t mx28_get_emiclk(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) { - div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> - CLKCTRL_EMI_DIV_XTAL_OFFSET; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -static uint32_t mx28_get_gpmiclk(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) { - div = clkctrl & CLKCTRL_GPMI_DIV_MASK; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_GPMI_DIV_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -/* - * Set IO clock frequency, in kHz - */ -void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t div; - int io_reg; - - if (freq == 0) - return; - - if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) - return; - - div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; - - if (div < 18) - div = 18; - - if (div > 35) - div = 35; - - io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); - writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[io_reg]); - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); -} - -/* - * Get IO clock, returns IO clock in kHz - */ -static uint32_t mx28_get_ioclk(enum mxs_ioclock io) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint8_t ret; - int io_reg; - - if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) - return 0; - - io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - - ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & - CLKCTRL_FRAC_FRAC_MASK; - - return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; -} - -/* - * Configure SSP clock frequency, in kHz - */ -void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clk, clkreg; - - if (ssp > MXC_SSPCLK3) - return; - - clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); - - clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); - while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) - ; - - if (xtal) - clk = XTAL_FREQ_KHZ; - else - clk = mx28_get_ioclk(ssp >> 1); - - if (freq > clk) - return; - - /* Calculate the divider and cap it if necessary */ - clk /= freq; - if (clk > CLKCTRL_SSP_DIV_MASK) - clk = CLKCTRL_SSP_DIV_MASK; - - clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk); - while (readl(clkreg) & CLKCTRL_SSP_BUSY) - ; - - if (xtal) - writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, - &clkctrl_regs->hw_clkctrl_clkseq_set); - else - writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} - -/* - * Return SSP frequency, in kHz - */ -static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkreg; - uint32_t clk, tmp; - - if (ssp > MXC_SSPCLK3) - return 0; - - tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); - if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp)) - return XTAL_FREQ_KHZ; - - clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); - - tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; - - if (tmp == 0) - return 0; - - clk = mx28_get_ioclk(ssp >> 1); - - return clk / tmp; -} - -/* - * Set SSP/MMC bus frequency, in kHz) - */ -void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq) -{ - struct mx28_ssp_regs *ssp_regs; - const uint32_t sspclk = mx28_get_sspclk(bus); - uint32_t reg; - uint32_t divide, rate, tgtclk; - - ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000)); - - /* - * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), - * CLOCK_DIVIDE has to be an even value from 2 to 254, and - * CLOCK_RATE could be any integer from 0 to 255. - */ - for (divide = 2; divide < 254; divide += 2) { - rate = sspclk / freq / divide; - if (rate <= 256) - break; - } - - tgtclk = sspclk / divide / rate; - while (tgtclk > freq) { - rate++; - tgtclk = sspclk / divide / rate; - } - if (rate > 256) - rate = 256; - - /* Always set timeout the maximum */ - reg = SSP_TIMING_TIMEOUT_MASK | - (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) | - ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET); - writel(reg, &ssp_regs->hw_ssp_timing); - - debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n", - bus, tgtclk, freq); -} - -uint32_t mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return mx28_get_pclk() * 1000000; - case MXC_GPMI_CLK: - return mx28_get_gpmiclk() * 1000000; - case MXC_AHB_CLK: - case MXC_IPG_CLK: - return mx28_get_hclk() * 1000000; - case MXC_EMI_CLK: - return mx28_get_emiclk(); - case MXC_IO0_CLK: - return mx28_get_ioclk(MXC_IOCLK0); - case MXC_IO1_CLK: - return mx28_get_ioclk(MXC_IOCLK1); - case MXC_SSP0_CLK: - return mx28_get_sspclk(MXC_SSPCLK0); - case MXC_SSP1_CLK: - return mx28_get_sspclk(MXC_SSPCLK1); - case MXC_SSP2_CLK: - return mx28_get_sspclk(MXC_SSPCLK2); - case MXC_SSP3_CLK: - return mx28_get_sspclk(MXC_SSPCLK3); - } - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c deleted file mode 100644 index 12916b6..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/iomux.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer kernel@pengutronix.de - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * armlinux@phytec.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> - -#if defined(CONFIG_MX23) -#define DRIVE_OFFSET 0x200 -#define PULL_OFFSET 0x400 -#elif defined(CONFIG_MX28) -#define DRIVE_OFFSET 0x300 -#define PULL_OFFSET 0x600 -#else -#error "Please select CONFIG_MX23 or CONFIG_MX28" -#endif - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad) -{ - u32 reg, ofs, bp, bm; - void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register_32 *mxs_reg; - - /* muxsel */ - ofs = 0x100; - ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; - bp = PAD_PIN(pad) % 16 * 2; - bm = 0x3 << bp; - reg = readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MUXSEL(pad) << bp; - writel(reg, iomux_base + ofs); - - /* drive */ - ofs = DRIVE_OFFSET; - ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; - /* mA */ - if (PAD_MA_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4; - bm = 0x3 << bp; - reg = readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MA(pad) << bp; - writel(reg, iomux_base + ofs); - } - /* vol */ - if (PAD_VOL_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); - if (PAD_VOL(pad)) - writel(1 << bp, &mxs_reg->reg_set); - else - writel(1 << bp, &mxs_reg->reg_clr); - } - - /* pull */ - if (PAD_PULL_VALID(pad)) { - ofs = PULL_OFFSET; - ofs += PAD_BANK(pad) * 0x10; - bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); - if (PAD_PULL(pad)) - writel(1 << bp, &mxs_reg->reg_set); - else - writel(1 << bp, &mxs_reg->reg_clr); - } - - return 0; -} - -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) -{ - const iomux_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxs_iomux_setup_pad(*p); - if (ret) - return ret; - p++; - } - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c deleted file mode 100644 index a82ff25..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Freescale i.MX28 common code - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/dma.h> -#include <asm/arch/gpio.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* 1 second delay should be plenty of time for block reset. */ -#define RESET_MAX_TIMEOUT 1000000 - -#define MX28_BLOCK_SFTRST (1 << 31) -#define MX28_BLOCK_CLKGATE (1 << 30) - -/* Lowlevel init isn't used on i.MX28, so just have a dummy here */ -inline void lowlevel_init(void) {} - -void reset_cpu(ulong ignored) __attribute__((noreturn)); - -void reset_cpu(ulong ignored) -{ - struct mx28_rtc_regs *rtc_regs = - (struct mx28_rtc_regs *)MXS_RTC_BASE; - struct mx28_lcdif_regs *lcdif_regs = - (struct mx28_lcdif_regs *)MXS_LCDIF_BASE; - - /* - * Shut down the LCD controller as it interferes with BootROM boot mode - * pads sampling. - */ - writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); - - /* Wait 1 uS before doing the actual watchdog reset */ - writel(1, &rtc_regs->hw_rtc_watchdog); - writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); - - /* Endless loop, reset will exit from here */ - for (;;) - ; -} - -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - -int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) -{ - while (--timeout) { - if ((readl(&reg->reg) & mask) == mask) - break; - udelay(1); - } - - return !timeout; -} - -int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) -{ - while (--timeout) { - if ((readl(&reg->reg) & mask) == 0) - break; - udelay(1); - } - - return !timeout; -} - -int mx28_reset_block(struct mx28_register_32 *reg) -{ - /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, &reg->reg_clr); - - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) - return 1; - - /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); - - /* Set SFTRST */ - writel(MX28_BLOCK_SFTRST, &reg->reg_set); - - /* Wait for CLKGATE being set */ - if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) - return 1; - - /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, &reg->reg_clr); - - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) - return 1; - - /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); - - if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) - return 1; - - return 0; -} - -void mx28_fixup_vt(uint32_t start_addr) -{ - uint32_t *vt = (uint32_t *)0x20; - int i; - - for (i = 0; i < 8; i++) - vt[i] = start_addr + (4 * i); -} - -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - mx28_fixup_vt(gd->relocaddr); - return 0; -} -#endif - -#ifdef CONFIG_ARCH_CPU_INIT -int arch_cpu_init(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - extern uint32_t _start; - - mx28_fixup_vt((uint32_t)&_start); - - /* - * Enable NAND clock - */ - /* Clear bypass bit */ - writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, - &clkctrl_regs->hw_clkctrl_clkseq_set); - - /* Set GPMI clock to ref_gpmi / 12 */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); - - udelay(1000); - - /* - * Configure GPIO unit - */ - mxs_gpio_init(); - -#ifdef CONFIG_APBH_DMA - /* Start APBH DMA */ - mxs_dma_init(); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); - - printf("Freescale i.MX28 family at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); - return 0; -} -#endif - -int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); - printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); - printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); - return 0; -} - -/* - * Initializes on-chip ethernet controllers. - */ -#ifdef CONFIG_CMD_NET -int cpu_eth_init(bd_t *bis) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Turn on ENET clocks */ - clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); - - /* Set up ENET PLL for 50 MHz */ - /* Power on ENET PLL */ - writel(CLKCTRL_PLL2CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); - - udelay(10); - - /* Gate on ENET PLL */ - writel(CLKCTRL_PLL2CTRL0_CLKGATE, - &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); - - /* Enable pad output */ - setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); - - return 0; -} -#endif - -static void __mx28_adjust_mac(int dev_id, unsigned char *mac) -{ - mac[0] = 0x00; - mac[1] = 0x04; /* Use FSL vendor MAC address by default */ - - if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ - mac[5] += 1; -} - -void mx28_adjust_mac(int dev_id, unsigned char *mac) - __attribute__((weak, alias("__mx28_adjust_mac"))); - -#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP - -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - struct mx28_ocotp_regs *ocotp_regs = - (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; - uint32_t data; - - memset(mac, 0, 6); - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS FEC: Can't get MAC from OCOTP\n"); - return; - } - - data = readl(&ocotp_regs->hw_ocotp_cust0); - - mac[2] = (data >> 24) & 0xff; - mac[3] = (data >> 16) & 0xff; - mac[4] = (data >> 8) & 0xff; - mac[5] = data & 0xff; - mx28_adjust_mac(dev_id, mac); -} -#else -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - memset(mac, 0, 6); -} -#endif - -int mx28_dram_init(void) -{ - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); - - if (data->mem_dram_size == 0) { - printf("MX28:\n" - "Error, the RAM size passed up from SPL is 0!\n"); - hang(); - } - - gd->ram_size = data->mem_dram_size; - return 0; -} - -U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, - "display clocks", - "" -); diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h deleted file mode 100644 index e3a4493..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Freescale i.MX28 SPL functions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M28_INIT_H__ -#define __M28_INIT_H__ - -void early_delay(int delay); - -void mx28_power_init(void); - -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT -void mx28_power_wait_pswitch(void); -#else -static inline void mx28_power_wait_pswitch(void) { } -#endif - -void mx28_mem_init(void); -uint32_t mx28_mem_get_size(void); - -void mx28_lradc_init(void); -void mx28_lradc_enable_batt_measurement(void); - -#endif /* __M28_INIT_H__ */ diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c deleted file mode 100644 index a6dfca3..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Freescale i.MX28 Boot setup - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> - -#include "mx28_init.h" - -/* - * This delay function is intended to be used only in early stage of boot, where - * clock are not set up yet. The timer used here is reset on every boot and - * takes a few seconds to roll. The boot doesn't take that long, so to keep the - * code simple, it doesn't take rolling into consideration. - */ -#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 -void early_delay(int delay) -{ - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); - st += delay; - while (st > readl(HW_DIGCTRL_MICROSECONDS)) - ; -} - -#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -const iomux_cfg_t iomux_boot[] = { - MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -}; - -uint8_t mx28_get_bootmode_index(void) -{ - uint8_t bootmode = 0; - int i; - uint8_t masked; - - /* Setup IOMUX of bootmode pads to GPIO */ - mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); - - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); - gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; - - for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { - masked = bootmode & mx28_boot_modes[i].boot_mask; - if (masked == mx28_boot_modes[i].boot_pads) - break; - } - - return i; -} - -void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size) -{ - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); - uint8_t bootmode = mx28_get_bootmode_index(); - - mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); - mx28_power_init(); - - mx28_mem_init(); - data->mem_dram_size = mx28_mem_get_size(); - - data->boot_mode_idx = bootmode; - - mx28_power_wait_pswitch(); -} - -/* Support aparatus */ -inline void board_init_f(unsigned long bootflag) -{ - for (;;) - ; -} - -inline void board_init_r(gd_t *id, ulong dest_addr) -{ - for (;;) - ; -} - -#ifndef CONFIG_SPL_SERIAL_SUPPORT -void serial_putc(const char c) {} -void serial_puts(const char *s) {} -#endif -void hang(void) __attribute__ ((noreturn)); -void hang(void) -{ - for (;;) - ; -} diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c deleted file mode 100644 index 9fa5d29..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Freescale i.MX28 RAM init - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> - -#include "mx28_init.h" - -uint32_t dram_vals[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010101, 0x01010101, - 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, - 0x00000100, 0x00000100, 0x00000000, 0x00000002, - 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, - 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, - 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, - 0x00000003, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000612, 0x01000F02, - 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, - 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, - 0x07000300, 0x07000300, 0x07000300, 0x00000006, - 0x00000000, 0x00000000, 0x01000000, 0x01020408, - 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00020304, - 0x00000004, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x01010000, - 0x01000000, 0x03030000, 0x00010303, 0x01020202, - 0x00000000, 0x02040303, 0x21002103, 0x00061200, - 0x06120612, 0x04320432, 0x04320432, 0x00040004, - 0x00040004, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010001 -}; - -void init_m28_200mhz_ddr2(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); -} - -void mx28_mem_init_clock(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Gate EMI clock */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - - /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ - writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); - - /* Ungate EMI clock */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); - - early_delay(11000); - - /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ - writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | - (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), - &clkctrl_regs->hw_clkctrl_emi); - - /* Unbypass EMI */ - writel(CLKCTRL_CLKSEQ_BYPASS_EMI, - &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(10000); -} - -void mx28_mem_setup_cpu_and_hbus(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz - * and ungate CPU clock */ - writeb(19 & CLKCTRL_FRAC_FRAC_MASK, - (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - - /* Set CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); - - /* HBUS = 151MHz */ - writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); - writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, - &clkctrl_regs->hw_clkctrl_hbus_clr); - - early_delay(10000); - - /* CPU clock divider = 1 */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, - CLKCTRL_CPU_DIV_CPU_MASK, 1); - - /* Disable CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(15000); -} - -void mx28_mem_setup_vdda(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); -} - -void mx28_mem_setup_vddd(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | - (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vdddctrl); -} - -uint32_t mx28_mem_get_size(void) -{ - uint32_t sz, da; - uint32_t *vt = (uint32_t *)0x20; - /* The following is "subs pc, r14, #4", used as return from DABT. */ - const uint32_t data_abort_memdetect_handler = 0xe25ef004; - - /* Replace the DABT handler. */ - da = vt[4]; - vt[4] = data_abort_memdetect_handler; - - sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - /* Restore the old DABT handler. */ - vt[4] = da; - - return sz; -} - -void mx28_mem_init(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct mx28_pinctrl_regs *pinctrl_regs = - (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; - - /* Set DDR2 mode */ - writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, - &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); - - /* Power up PLL0 */ - writel(CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - - early_delay(11000); - - mx28_mem_init_clock(); - - mx28_mem_setup_vdda(); - - /* - * Configure the DRAM registers - */ - - /* Clear START bit from DRAM_CTL16 */ - clrbits_le32(MXS_DRAM_BASE + 0x40, 1); - - init_m28_200mhz_ddr2(); - - /* Clear SREFRESH bit from DRAM_CTL17 */ - clrbits_le32(MXS_DRAM_BASE + 0x44, 1); - - /* Set START bit in DRAM_CTL16 */ - setbits_le32(MXS_DRAM_BASE + 0x40, 1); - - /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ - while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) - ; - - mx28_mem_setup_vddd(); - - early_delay(10000); - - mx28_mem_setup_cpu_and_hbus(); -} diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c deleted file mode 100644 index 4b09b0c..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ /dev/null @@ -1,1007 +0,0 @@ -/* - * Freescale i.MX28 Boot PMIC init - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#include "mx28_init.h" - -void mx28_power_clock2xtal(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set XTAL as CPU reference clock */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, - CLKCTRL_PLL0CTRL0_POWER); - early_delay(100); - setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, - CLKCTRL_CLKSEQ_BYPASS_CPU); -} - -void mx28_power_clear_auto_restart(void) -{ - struct mx28_rtc_regs *rtc_regs = - (struct mx28_rtc_regs *)MXS_RTC_BASE; - - writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) - ; - - writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) - ; - - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ - if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) - return; - - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; - - setbits_le32(&rtc_regs->hw_rtc_persistent0, - RTC_PERSISTENT0_AUTO_RESTART); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) - ; -} - -void mx28_power_set_linreg(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* Set linear regulator 25mV below switching converter */ - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_LINREG_OFFSET_MASK, - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrsetbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_LINREG_OFFSET_MASK, - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_LINREG_OFFSET_MASK, - POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); -} - -int mx28_get_batt_volt(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt = readl(&power_regs->hw_power_battmonitor); - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; - volt *= 8; - return volt; -} - -int mx28_is_batt_ready(void) -{ - return (mx28_get_batt_volt() >= 3600); -} - -int mx28_is_batt_good(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt = mx28_get_batt_volt(); - - if ((volt >= 2400) && (volt <= 4300)) - return 1; - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - clrsetbits_le32(&power_regs->hw_power_charge, - POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); - - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - early_delay(500000); - - volt = mx28_get_batt_volt(); - - if (volt >= 3500) - return 0; - - if (volt >= 2400) - return 1; - - writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - &power_regs->hw_power_charge_clr); - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); - - return 0; -} - -void mx28_power_setup_5v_detect(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* Start 5V detection */ - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_TRSH_MASK, - POWER_5VCTRL_VBUSVALID_TRSH_4V4 | - POWER_5VCTRL_PWRUP_VBUS_CMPS); -} - -void mx28_src_power_init(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* Improve efficieny and reduce transient ripple */ - writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | - POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); - - clrsetbits_le32(&power_regs->hw_power_dclimits, - POWER_DCLIMITS_POSLIMIT_BUCK_MASK, - 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); - - setbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_EN_BATADJ); - - /* Increase the RCSCALE level for quick DCDC response to dynamic load */ - clrsetbits_le32(&power_regs->hw_power_loopctrl, - POWER_LOOPCTRL_EN_RCSCALE_MASK, - POWER_LOOPCTRL_RCSCALE_THRESH | - POWER_LOOPCTRL_EN_RCSCALE_8X); - - clrsetbits_le32(&power_regs->hw_power_minpwr, - POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - - /* 5V to battery handoff ... FIXME */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); -} - -void mx28_power_init_4p2_params(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* Setup 4P2 parameters */ - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, - POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_HEADROOM_ADJ_MASK, - 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); - - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_DROPOUT_CTRL_MASK, - POWER_DCDC4P2_DROPOUT_CTRL_100MV | - POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); -} - -void mx28_enable_4p2_dcdc_input(int xfer) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; - uint32_t prev_5v_brnout, prev_5v_droop; - - prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_PWDN_5VBRNOUT; - prev_5v_droop = readl(&power_regs->hw_power_ctrl) & - POWER_CTRL_ENIRQ_VDD5V_DROOP; - - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); - - clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); - - if (xfer && (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return; - } - - /* - * Recording orignal values that will be modified temporarlily - * to handle a chip bug. See chip errata for CQ ENGR00115837 - */ - tmp = readl(&power_regs->hw_power_5vctrl); - vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; - vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; - - pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; - - /* - * Disable mechanisms that get erroneously tripped by when setting - * the DCDC4P2 EN_DCDC - */ - clrbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_5VDETECT | - POWER_5VCTRL_VBUSVALID_TRSH_MASK); - - writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); - - if (xfer) { - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_DCDC_XFER); - early_delay(20); - clrbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_DCDC_XFER); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_ENABLE_DCDC); - } else { - setbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - } - - early_delay(25); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); - - if (vbus_5vdetect) - writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); - - if (!pwd_bo) - clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); - - while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) - writel(POWER_CTRL_VBUS_VALID_IRQ, - &power_regs->hw_power_ctrl_clr); - - if (prev_5v_brnout) { - writel(POWER_5VCTRL_PWDN_5VBRNOUT, - &power_regs->hw_power_5vctrl_set); - writel(POWER_RESET_UNLOCK_KEY, - &power_regs->hw_power_reset); - } else { - writel(POWER_5VCTRL_PWDN_5VBRNOUT, - &power_regs->hw_power_5vctrl_clr); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); - } - - while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) - writel(POWER_CTRL_VDD5V_DROOP_IRQ, - &power_regs->hw_power_ctrl_clr); - - if (prev_5v_droop) - clrbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_ENIRQ_VDD5V_DROOP); - else - setbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_ENIRQ_VDD5V_DROOP); -} - -void mx28_power_init_4p2_regulator(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t tmp, tmp2; - - setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); - - writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); - - writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - &power_regs->hw_power_5vctrl_clr); - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); - - /* Power up the 4p2 rail and logic/control */ - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - /* - * Start charging up the 4p2 capacitor. We ramp of this charge - * gradually to avoid large inrush current from the 5V cable which can - * cause transients/problems - */ - mx28_enable_4p2_dcdc_input(0); - - if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { - /* - * If we arrived here, we were unable to recover from mx23 chip - * errata 5837. 4P2 is disabled and sufficient battery power is - * not present. Exiting to not enable DCDC power during 5V - * connected state. - */ - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_set); - hang(); - } - - /* - * Here we set the 4p2 brownout level to something very close to 4.2V. - * We then check the brownout status. If the brownout status is false, - * the voltage is already close to the target voltage of 4.2V so we - * can go ahead and set the 4P2 current limit to our max target limit. - * If the brownout status is true, we need to ramp us the current limit - * so that we don't cause large inrush current issues. We step up the - * current limit until the brownout status is false or until we've - * reached our maximum defined 4p2 current limit. - */ - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_BO_MASK, - 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ - - if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { - setbits_le32(&power_regs->hw_power_5vctrl, - 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - } else { - tmp = (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> - POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; - while (tmp < 0x3f) { - if (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DCDC_4P2_BO)) { - tmp = readl(&power_regs->hw_power_5vctrl); - tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; - early_delay(100); - writel(tmp, &power_regs->hw_power_5vctrl); - break; - } else { - tmp++; - tmp2 = readl(&power_regs->hw_power_5vctrl); - tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; - tmp2 |= tmp << - POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; - writel(tmp2, &power_regs->hw_power_5vctrl); - early_delay(100); - } - } - } - - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); - writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); -} - -void mx28_power_init_dcdc_4p2_source(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - if (!(readl(&power_regs->hw_power_dcdc4p2) & - POWER_DCDC4P2_ENABLE_DCDC)) { - hang(); - } - - mx28_enable_4p2_dcdc_input(1); - - if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - writel(POWER_5VCTRL_ENABLE_DCDC, - &power_regs->hw_power_5vctrl_clr); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_set); - } -} - -void mx28_power_enable_4p2(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t vdddctrl, vddactrl, vddioctrl; - uint32_t tmp; - - vdddctrl = readl(&power_regs->hw_power_vdddctrl); - vddactrl = readl(&power_regs->hw_power_vddactrl); - vddioctrl = readl(&power_regs->hw_power_vddioctrl); - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | - POWER_VDDDCTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | - POWER_VDDACTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); - - mx28_power_init_4p2_params(); - mx28_power_init_4p2_regulator(); - - /* Shutdown battery (none present) */ - if (!mx28_is_batt_ready()) { - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_BO_MASK); - writel(POWER_CTRL_DCDC4P2_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, - &power_regs->hw_power_ctrl_clr); - } - - mx28_power_init_dcdc_4p2_source(); - - writel(vdddctrl, &power_regs->hw_power_vdddctrl); - early_delay(20); - writel(vddactrl, &power_regs->hw_power_vddactrl); - early_delay(20); - writel(vddioctrl, &power_regs->hw_power_vddioctrl); - - /* - * Check if FET is enabled on either powerout and if so, - * disable load. - */ - tmp = 0; - tmp |= !(readl(&power_regs->hw_power_vdddctrl) & - POWER_VDDDCTRL_DISABLE_FET); - tmp |= !(readl(&power_regs->hw_power_vddactrl) & - POWER_VDDACTRL_DISABLE_FET); - tmp |= !(readl(&power_regs->hw_power_vddioctrl) & - POWER_VDDIOCTRL_DISABLE_FET); - if (tmp) - writel(POWER_CHARGE_ENABLE_LOAD, - &power_regs->hw_power_charge_clr); -} - -void mx28_boot_valid_5v(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* - * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V - * disconnect event. FIXME - */ - writel(POWER_5VCTRL_VBUSVALID_5VDETECT, - &power_regs->hw_power_5vctrl_set); - - /* Configure polarity to check for 5V disconnection. */ - writel(POWER_CTRL_POLARITY_VBUSVALID | - POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, - &power_regs->hw_power_ctrl_clr); - - writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, - &power_regs->hw_power_ctrl_clr); - - mx28_power_enable_4p2(); -} - -void mx28_powerdown(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); -} - -void mx28_batt_boot(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); - - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); - writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); - - /* 5V to battery handoff. */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); - - clrsetbits_le32(&power_regs->hw_power_minpwr, - POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - - mx28_power_set_linreg(); - - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); - - clrbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); - - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_DISABLE_FET); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_PWD_CHARGE_4P2_MASK); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_ENABLE_DCDC); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); -} - -void mx28_handle_5v_conflict(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_BO_OFFSET_MASK); - - for (;;) { - tmp = readl(&power_regs->hw_power_sts); - - if (tmp & POWER_STS_VDDIO_BO) { - mx28_powerdown(); - break; - } - - if (tmp & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); - break; - } else { - mx28_powerdown(); - break; - } - - if (tmp & POWER_STS_PSWITCH_MASK) { - mx28_batt_boot(); - break; - } - } -} - -void mx28_5v_boot(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* - * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, - * but their implementation always returns 1 so we omit it here. - */ - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); - return; - } - - early_delay(1000); - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); - return; - } - - mx28_handle_5v_conflict(); -} - -void mx28_init_batt_bo(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - /* Brownout at 3V */ - clrsetbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BRWNOUT_LVL_MASK, - 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); - - writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); - writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); -} - -void mx28_switch_vddd_to_dcdc_source(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_LINREG_OFFSET_MASK, - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | - POWER_VDDDCTRL_DISABLE_STEPPING); -} - -void mx28_power_configure_power_source(void) -{ - int batt_ready, batt_good; - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - struct mx28_lradc_regs *lradc_regs = - (struct mx28_lradc_regs *)MXS_LRADC_BASE; - - mx28_src_power_init(); - - batt_ready = mx28_is_batt_ready(); - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - batt_good = mx28_is_batt_good(); - if (batt_ready) { - /* 5V source detected, good battery detected. */ - mx28_batt_boot(); - } else { - if (batt_good) { - /* 5V source detected, low battery detceted. */ - } else { - /* 5V source detected, bad battery detected. */ - writel(LRADC_CONVERSION_AUTOMATIC, - &lradc_regs->hw_lradc_conversion_clr); - clrbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BATT_VAL_MASK); - } - mx28_5v_boot(); - } - } else { - /* 5V not detected, booting from battery. */ - mx28_batt_boot(); - } - - mx28_power_clock2pll(); - - mx28_init_batt_bo(); - - mx28_switch_vddd_to_dcdc_source(); -} - -void mx28_enable_output_rail_protection(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | - POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_PWDN_BRNOUT); -} - -int mx28_get_vddio_power_source_off(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - tmp = readl(&power_regs->hw_power_vddioctrl); - if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { - if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - - if (!(readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - } - - return 0; - -} - -int mx28_get_vddd_power_source_off(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - tmp = readl(&power_regs->hw_power_vdddctrl); - if (tmp & POWER_VDDDCTRL_DISABLE_FET) { - if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - if (!(readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return 1; - } - } - - if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { - if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { - return 1; - } - } - - return 0; -} - -void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - - new_brownout = new_target - new_brownout; - - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ - - powered_by_linreg = mx28_get_vddio_power_source_off(); - if (new_target > cur_target) { - - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vddioctrl); - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_BO_OFFSET_MASK); - do { - if (new_target - cur_target > 100) - diff = cur_target + 100; - else - diff = new_target; - - diff -= 2800; - diff /= 50; - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ - } while (new_target > cur_target); - - if (powered_by_linreg) { - writel(POWER_CTRL_VDDIO_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } - } else { - do { - if (cur_target - new_target > 100) - diff = cur_target - 100; - else - diff = new_target; - - diff -= 2800; - diff /= 50; - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ - } while (new_target < cur_target); - } - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); -} - -void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - - new_brownout = new_target - new_brownout; - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - - powered_by_linreg = mx28_get_vddd_power_source_off(); - if (new_target > cur_target) { - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vdddctrl); - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); - } - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK); - - do { - if (new_target - cur_target > 100) - diff = cur_target + 100; - else - diff = new_target; - - diff -= 800; - diff /= 25; - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - } while (new_target > cur_target); - - if (powered_by_linreg) { - writel(POWER_CTRL_VDDD_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); - } - } else { - do { - if (cur_target - new_target > 100) - diff = cur_target - 100; - else - diff = new_target; - - diff -= 800; - diff /= 25; - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - } while (new_target < cur_target); - } - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); -} - -void mx28_setup_batt_detect(void) -{ - mx28_lradc_init(); - mx28_lradc_enable_batt_measurement(); - early_delay(10); -} - -void mx28_power_init(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - mx28_power_clock2xtal(); - mx28_power_clear_auto_restart(); - mx28_power_set_linreg(); - mx28_power_setup_5v_detect(); - - mx28_setup_batt_detect(); - - mx28_power_configure_power_source(); - mx28_enable_output_rail_protection(); - - mx28_power_set_vddio(3300, 3150); - - mx28_power_set_vddd(1350, 1200); - - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | - POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | - POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | - POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); - - writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); - - early_delay(1000); -} - -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT -void mx28_power_wait_pswitch(void) -{ - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - - while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) - ; -} -#endif diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S deleted file mode 100644 index e572b78..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ /dev/null @@ -1,247 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Groger mag@sysgo.de - * Copyright (c) 2002 Alex Zupke azu@sysgo.de - * Copyright (c) 2002 Gary Jennejohn garyj@denx.de - * Copyright (c) 2003 Richard Woodruff r-woodruff2@ti.com - * Copyright (c) 2003 Kshitij kshitij@ti.com - * Copyright (c) 2010 Albert Aribaud albert.u.boot@aribaud.net - * - * Change to support call back into iMX28 bootrom - * Copyright (c) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm-offsets.h> -#include <config.h> -#include <common.h> -#include <version.h> - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_vt_reset: - .word _reset -_vt_undefined_instruction: - .word _hang -_vt_software_interrupt: - .word _hang -_vt_prefetch_abort: - .word _hang -_vt_data_abort: - .word _hang -_vt_not_used: - .word _reset -_vt_irq: - .word _hang -_vt_fiq: - .word _hang - -reset: - ldr pc, _vt_reset -undefined_instruction: - ldr pc, _vt_undefined_instruction -software_interrupt: - ldr pc, _vt_software_interrupt -prefetch_abort: - ldr pc, _vt_prefetch_abort -data_abort: - ldr pc, _vt_data_abort -not_used: - ldr pc, _vt_not_used -irq: - ldr pc, _vt_irq -fiq: - ldr pc, _vt_fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end__ - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -_reset: - /* - * Store all registers on old stack pointer, this will allow us later to - * return to the BootROM and let the BootROM load U-Boot into RAM. - */ - push {r0-r12,r14} - - /* save control register c1 */ - mrc p15, 0, r0, c1, c0, 0 - push {r0} - - /* - * set the cpu to SVC32 mode and store old CPSR register content - */ - mrs r0,cpsr - push {r0} - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - - bl board_init_ll - - /* - * restore bootrom's cpu mode (especially FIQ) - */ - pop {r0} - msr cpsr,r0 - - /* - * restore c1 register - * (especially set exception vector location back to - * bootrom space which is required by bootrom for USB boot) - */ - pop {r0} - mcr p15, 0, r0, c1, c0, 0 - - pop {r0-r12,r14} - bx lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - mov pc, lr /* back to my caller */ - - .align 5 -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -_hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ -1: - bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mx28/timer.c deleted file mode 100644 index 5b73f4a..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/timer.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Freescale i.MX28 timer driver - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -/* Maximum fixed count */ -#define TIMER_LOAD_VAL 0xffffffff - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->tbl) -#define lastdec (gd->lastinc) - -/* - * This driver uses 1kHz clock source. - */ -#define MX28_INCREMENTER_HZ 1000 - -static inline unsigned long tick_to_time(unsigned long tick) -{ - return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); -} - -static inline unsigned long time_to_tick(unsigned long time) -{ - return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); -} - -/* Calculate how many ticks happen in "us" microseconds */ -static inline unsigned long us_to_tick(unsigned long us) -{ - return (us * MX28_INCREMENTER_HZ) / 1000000; -} - -int timer_init(void) -{ - struct mx28_timrot_regs *timrot_regs = - (struct mx28_timrot_regs *)MXS_TIMROT_BASE; - - /* Reset Timers and Rotary Encoder module */ - mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); - - /* Set fixed_count to 0 */ - writel(0, &timrot_regs->hw_timrot_fixed_count0); - - /* Set UPDATE bit and 1Khz frequency */ - writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | - TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, - &timrot_regs->hw_timrot_timctrl0); - - /* Set fixed_count to maximal value */ - writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); - - return 0; -} - -unsigned long long get_ticks(void) -{ - struct mx28_timrot_regs *timrot_regs = - (struct mx28_timrot_regs *)MXS_TIMROT_BASE; - - /* Current tick value */ - uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (lastdec - now); - } else { - /* we have rollover of decrementer */ - timestamp += (TIMER_LOAD_VAL - now) + lastdec; - - } - lastdec = now; - - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ -#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 - -void __udelay(unsigned long usec) -{ - uint32_t old, new, incr; - uint32_t counter = 0; - - old = readl(MX28_HW_DIGCTL_MICROSECONDS); - - while (counter < usec) { - new = readl(MX28_HW_DIGCTL_MICROSECONDS); - - /* Check if the timer wrapped. */ - if (new < old) { - incr = 0xffffffff - old; - incr += new; - } else { - incr = new - old; - } - - /* - * Check if we are close to the maximum time and the counter - * would wrap if incremented. If that's the case, break out - * from the loop as the requested delay time passed. - */ - if (counter + incr < counter) - break; - - counter += incr; - old = new; - } -} - -ulong get_tbclk(void) -{ - return MX28_INCREMENTER_HZ; -} diff --git a/arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds deleted file mode 100644 index 0fccd52..0000000 --- a/arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm926ejs/mx28/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - .bss : { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end__ = .; - } - - _end = .; - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile new file mode 100644 index 0000000..674a3af --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = clock.o mx28.o iomux.o timer.o + +ifdef CONFIG_SPL_BUILD +COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o +endif + +SRCS := $(START:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c new file mode 100644 index 0000000..0439f9c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -0,0 +1,339 @@ +/* + * Freescale i.MX28 clock setup code + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> + +/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */ +#define PLL_FREQ_KHZ 480000 +#define PLL_FREQ_COEF 18 +/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */ +#define XTAL_FREQ_KHZ 24000 + +#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) +#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) + +static uint32_t mx28_get_pclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; + + clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); + + /* No support of fractional divider calculation */ + if (clkctrl & + (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) { + return 0; + } + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) { + div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> + CLKCTRL_CPU_DIV_XTAL_OFFSET; + return XTAL_FREQ_MHZ / div; + } + + /* REF Path */ + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; + div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +static uint32_t mx28_get_hclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t div; + uint32_t clkctrl; + + clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); + + /* No support of fractional divider calculation */ + if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) + return 0; + + div = clkctrl & CLKCTRL_HBUS_DIV_MASK; + return mx28_get_pclk() / div; +} + +static uint32_t mx28_get_emiclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) { + div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> + CLKCTRL_EMI_DIV_XTAL_OFFSET; + return XTAL_FREQ_MHZ / div; + } + + /* REF Path */ + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; + div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +static uint32_t mx28_get_gpmiclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) { + div = clkctrl & CLKCTRL_GPMI_DIV_MASK; + return XTAL_FREQ_MHZ / div; + } + + /* REF Path */ + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; + div = clkctrl & CLKCTRL_GPMI_DIV_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +/* + * Set IO clock frequency, in kHz + */ +void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t div; + int io_reg; + + if (freq == 0) + return; + + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) + return; + + div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; + + if (div < 18) + div = 18; + + if (div > 35) + div = 35; + + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); +} + +/* + * Get IO clock, returns IO clock in kHz + */ +static uint32_t mx28_get_ioclk(enum mxs_ioclock io) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint8_t ret; + int io_reg; + + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) + return 0; + + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ + + ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & + CLKCTRL_FRAC_FRAC_MASK; + + return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; +} + +/* + * Configure SSP clock frequency, in kHz + */ +void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t clk, clkreg; + + if (ssp > MXC_SSPCLK3) + return; + + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + + (ssp * sizeof(struct mx28_register_32)); + + clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); + while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) + ; + + if (xtal) + clk = XTAL_FREQ_KHZ; + else + clk = mx28_get_ioclk(ssp >> 1); + + if (freq > clk) + return; + + /* Calculate the divider and cap it if necessary */ + clk /= freq; + if (clk > CLKCTRL_SSP_DIV_MASK) + clk = CLKCTRL_SSP_DIV_MASK; + + clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk); + while (readl(clkreg) & CLKCTRL_SSP_BUSY) + ; + + if (xtal) + writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, + &clkctrl_regs->hw_clkctrl_clkseq_set); + else + writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +/* + * Return SSP frequency, in kHz + */ +static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t clkreg; + uint32_t clk, tmp; + + if (ssp > MXC_SSPCLK3) + return 0; + + tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); + if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp)) + return XTAL_FREQ_KHZ; + + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + + (ssp * sizeof(struct mx28_register_32)); + + tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; + + if (tmp == 0) + return 0; + + clk = mx28_get_ioclk(ssp >> 1); + + return clk / tmp; +} + +/* + * Set SSP/MMC bus frequency, in kHz) + */ +void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq) +{ + struct mx28_ssp_regs *ssp_regs; + const uint32_t sspclk = mx28_get_sspclk(bus); + uint32_t reg; + uint32_t divide, rate, tgtclk; + + ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000)); + + /* + * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), + * CLOCK_DIVIDE has to be an even value from 2 to 254, and + * CLOCK_RATE could be any integer from 0 to 255. + */ + for (divide = 2; divide < 254; divide += 2) { + rate = sspclk / freq / divide; + if (rate <= 256) + break; + } + + tgtclk = sspclk / divide / rate; + while (tgtclk > freq) { + rate++; + tgtclk = sspclk / divide / rate; + } + if (rate > 256) + rate = 256; + + /* Always set timeout the maximum */ + reg = SSP_TIMING_TIMEOUT_MASK | + (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) | + ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET); + writel(reg, &ssp_regs->hw_ssp_timing); + + debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n", + bus, tgtclk, freq); +} + +uint32_t mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx28_get_pclk() * 1000000; + case MXC_GPMI_CLK: + return mx28_get_gpmiclk() * 1000000; + case MXC_AHB_CLK: + case MXC_IPG_CLK: + return mx28_get_hclk() * 1000000; + case MXC_EMI_CLK: + return mx28_get_emiclk(); + case MXC_IO0_CLK: + return mx28_get_ioclk(MXC_IOCLK0); + case MXC_IO1_CLK: + return mx28_get_ioclk(MXC_IOCLK1); + case MXC_SSP0_CLK: + return mx28_get_sspclk(MXC_SSPCLK0); + case MXC_SSP1_CLK: + return mx28_get_sspclk(MXC_SSPCLK1); + case MXC_SSP2_CLK: + return mx28_get_sspclk(MXC_SSPCLK2); + case MXC_SSP3_CLK: + return mx28_get_sspclk(MXC_SSPCLK3); + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c new file mode 100644 index 0000000..12916b6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -0,0 +1,109 @@ +/* + * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer kernel@pengutronix.de + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * armlinux@phytec.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> + +#if defined(CONFIG_MX23) +#define DRIVE_OFFSET 0x200 +#define PULL_OFFSET 0x400 +#elif defined(CONFIG_MX28) +#define DRIVE_OFFSET 0x300 +#define PULL_OFFSET 0x600 +#else +#error "Please select CONFIG_MX23 or CONFIG_MX28" +#endif + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad) +{ + u32 reg, ofs, bp, bm; + void *iomux_base = (void *)MXS_PINCTRL_BASE; + struct mx28_register_32 *mxs_reg; + + /* muxsel */ + ofs = 0x100; + ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; + bp = PAD_PIN(pad) % 16 * 2; + bm = 0x3 << bp; + reg = readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MUXSEL(pad) << bp; + writel(reg, iomux_base + ofs); + + /* drive */ + ofs = DRIVE_OFFSET; + ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; + /* mA */ + if (PAD_MA_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4; + bm = 0x3 << bp; + reg = readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MA(pad) << bp; + writel(reg, iomux_base + ofs); + } + /* vol */ + if (PAD_VOL_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4 + 2; + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + if (PAD_VOL(pad)) + writel(1 << bp, &mxs_reg->reg_set); + else + writel(1 << bp, &mxs_reg->reg_clr); + } + + /* pull */ + if (PAD_PULL_VALID(pad)) { + ofs = PULL_OFFSET; + ofs += PAD_BANK(pad) * 0x10; + bp = PAD_PIN(pad); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + if (PAD_PULL(pad)) + writel(1 << bp, &mxs_reg->reg_set); + else + writel(1 << bp, &mxs_reg->reg_clr); + } + + return 0; +} + +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) +{ + const iomux_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxs_iomux_setup_pad(*p); + if (ret) + return ret; + p++; + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c b/arch/arm/cpu/arm926ejs/mxs/mx28.c new file mode 100644 index 0000000..a82ff25 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mx28.c @@ -0,0 +1,310 @@ +/* + * Freescale i.MX28 common code + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dma.h> +#include <asm/arch/gpio.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* 1 second delay should be plenty of time for block reset. */ +#define RESET_MAX_TIMEOUT 1000000 + +#define MX28_BLOCK_SFTRST (1 << 31) +#define MX28_BLOCK_CLKGATE (1 << 30) + +/* Lowlevel init isn't used on i.MX28, so just have a dummy here */ +inline void lowlevel_init(void) {} + +void reset_cpu(ulong ignored) __attribute__((noreturn)); + +void reset_cpu(ulong ignored) +{ + struct mx28_rtc_regs *rtc_regs = + (struct mx28_rtc_regs *)MXS_RTC_BASE; + struct mx28_lcdif_regs *lcdif_regs = + (struct mx28_lcdif_regs *)MXS_LCDIF_BASE; + + /* + * Shut down the LCD controller as it interferes with BootROM boot mode + * pads sampling. + */ + writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); + + /* Wait 1 uS before doing the actual watchdog reset */ + writel(1, &rtc_regs->hw_rtc_watchdog); + writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); + + /* Endless loop, reset will exit from here */ + for (;;) + ; +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) +{ + while (--timeout) { + if ((readl(&reg->reg) & mask) == mask) + break; + udelay(1); + } + + return !timeout; +} + +int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) +{ + while (--timeout) { + if ((readl(&reg->reg) & mask) == 0) + break; + udelay(1); + } + + return !timeout; +} + +int mx28_reset_block(struct mx28_register_32 *reg) +{ + /* Clear SFTRST */ + writel(MX28_BLOCK_SFTRST, &reg->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear CLKGATE */ + writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); + + /* Set SFTRST */ + writel(MX28_BLOCK_SFTRST, &reg->reg_set); + + /* Wait for CLKGATE being set */ + if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear SFTRST */ + writel(MX28_BLOCK_SFTRST, &reg->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear CLKGATE */ + writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + return 1; + + return 0; +} + +void mx28_fixup_vt(uint32_t start_addr) +{ + uint32_t *vt = (uint32_t *)0x20; + int i; + + for (i = 0; i < 8; i++) + vt[i] = start_addr + (4 * i); +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + mx28_fixup_vt(gd->relocaddr); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + extern uint32_t _start; + + mx28_fixup_vt((uint32_t)&_start); + + /* + * Enable NAND clock + */ + /* Clear bypass bit */ + writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + /* Set GPMI clock to ref_gpmi / 12 */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, + CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + + udelay(1000); + + /* + * Configure GPIO unit + */ + mxs_gpio_init(); + +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + + printf("Freescale i.MX28 family at %d MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); + return 0; +} +#endif + +int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); + printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); + printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); + return 0; +} + +/* + * Initializes on-chip ethernet controllers. + */ +#ifdef CONFIG_CMD_NET +int cpu_eth_init(bd_t *bis) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Turn on ENET clocks */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); + + /* Set up ENET PLL for 50 MHz */ + /* Power on ENET PLL */ + writel(CLKCTRL_PLL2CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); + + udelay(10); + + /* Gate on ENET PLL */ + writel(CLKCTRL_PLL2CTRL0_CLKGATE, + &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); + + /* Enable pad output */ + setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); + + return 0; +} +#endif + +static void __mx28_adjust_mac(int dev_id, unsigned char *mac) +{ + mac[0] = 0x00; + mac[1] = 0x04; /* Use FSL vendor MAC address by default */ + + if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ + mac[5] += 1; +} + +void mx28_adjust_mac(int dev_id, unsigned char *mac) + __attribute__((weak, alias("__mx28_adjust_mac"))); + +#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP + +#define MXS_OCOTP_MAX_TIMEOUT 1000000 +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct mx28_ocotp_regs *ocotp_regs = + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; + uint32_t data; + + memset(mac, 0, 6); + + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); + + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + MXS_OCOTP_MAX_TIMEOUT)) { + printf("MXS FEC: Can't get MAC from OCOTP\n"); + return; + } + + data = readl(&ocotp_regs->hw_ocotp_cust0); + + mac[2] = (data >> 24) & 0xff; + mac[3] = (data >> 16) & 0xff; + mac[4] = (data >> 8) & 0xff; + mac[5] = data & 0xff; + mx28_adjust_mac(dev_id, mac); +} +#else +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + memset(mac, 0, 6); +} +#endif + +int mx28_dram_init(void) +{ + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + + if (data->mem_dram_size == 0) { + printf("MX28:\n" + "Error, the RAM size passed up from SPL is 0!\n"); + hang(); + } + + gd->ram_size = data->mem_dram_size; + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28_init.h b/arch/arm/cpu/arm926ejs/mxs/mx28_init.h new file mode 100644 index 0000000..e3a4493 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mx28_init.h @@ -0,0 +1,45 @@ +/* + * Freescale i.MX28 SPL functions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M28_INIT_H__ +#define __M28_INIT_H__ + +void early_delay(int delay); + +void mx28_power_init(void); + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void); +#else +static inline void mx28_power_wait_pswitch(void) { } +#endif + +void mx28_mem_init(void); +uint32_t mx28_mem_get_size(void); + +void mx28_lradc_init(void); +void mx28_lradc_enable_batt_measurement(void); + +#endif /* __M28_INIT_H__ */ diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c new file mode 100644 index 0000000..a6dfca3 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -0,0 +1,135 @@ +/* + * Freescale i.MX28 Boot setup + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +#include "mx28_init.h" + +/* + * This delay function is intended to be used only in early stage of boot, where + * clock are not set up yet. The timer used here is reset on every boot and + * takes a few seconds to roll. The boot doesn't take that long, so to keep the + * code simple, it doesn't take rolling into consideration. + */ +#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 +void early_delay(int delay) +{ + uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + st += delay; + while (st > readl(HW_DIGCTRL_MICROSECONDS)) + ; +} + +#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +const iomux_cfg_t iomux_boot[] = { + MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, + MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, +}; + +uint8_t mx28_get_bootmode_index(void) +{ + uint8_t bootmode = 0; + int i; + uint8_t masked; + + /* Setup IOMUX of bootmode pads to GPIO */ + mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); + + /* Setup bootmode pins as GPIO input */ + gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); + gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); + gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); + gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); + gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); + gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); + + /* Read bootmode pads */ + bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; + bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; + + for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { + masked = bootmode & mx28_boot_modes[i].boot_mask; + if (masked == mx28_boot_modes[i].boot_pads) + break; + } + + return i; +} + +void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size) +{ + struct mx28_spl_data *data = (struct mx28_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + uint8_t bootmode = mx28_get_bootmode_index(); + + mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); + mx28_power_init(); + + mx28_mem_init(); + data->mem_dram_size = mx28_mem_get_size(); + + data->boot_mode_idx = bootmode; + + mx28_power_wait_pswitch(); +} + +/* Support aparatus */ +inline void board_init_f(unsigned long bootflag) +{ + for (;;) + ; +} + +inline void board_init_r(gd_t *id, ulong dest_addr) +{ + for (;;) + ; +} + +#ifndef CONFIG_SPL_SERIAL_SUPPORT +void serial_putc(const char c) {} +void serial_puts(const char *s) {} +#endif +void hang(void) __attribute__ ((noreturn)); +void hang(void) +{ + for (;;) + ; +} diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c new file mode 100644 index 0000000..9fa5d29 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -0,0 +1,242 @@ +/* + * Freescale i.MX28 RAM init + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> + +#include "mx28_init.h" + +uint32_t dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, + 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000F02, + 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, + 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, + 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, + 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, + 0x00000004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, + 0x00040004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010001 +}; + +void init_m28_200mhz_ddr2(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} + +void mx28_mem_init_clock(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Gate EMI clock */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); + + /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ + writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); + + /* Ungate EMI clock */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); + + early_delay(11000); + + /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ + writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | + (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), + &clkctrl_regs->hw_clkctrl_emi); + + /* Unbypass EMI */ + writel(CLKCTRL_CLKSEQ_BYPASS_EMI, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + early_delay(10000); +} + +void mx28_mem_setup_cpu_and_hbus(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz + * and ungate CPU clock */ + writeb(19 & CLKCTRL_FRAC_FRAC_MASK, + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + /* HBUS = 151MHz */ + writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); + writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + early_delay(10000); + + /* CPU clock divider = 1 */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, + CLKCTRL_CPU_DIV_CPU_MASK, 1); + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + early_delay(15000); +} + +void mx28_mem_setup_vdda(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | + (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vddactrl); +} + +void mx28_mem_setup_vddd(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | + (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vdddctrl); +} + +uint32_t mx28_mem_get_size(void) +{ + uint32_t sz, da; + uint32_t *vt = (uint32_t *)0x20; + /* The following is "subs pc, r14, #4", used as return from DABT. */ + const uint32_t data_abort_memdetect_handler = 0xe25ef004; + + /* Replace the DABT handler. */ + da = vt[4]; + vt[4] = data_abort_memdetect_handler; + + sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + + /* Restore the old DABT handler. */ + vt[4] = da; + + return sz; +} + +void mx28_mem_init(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mx28_pinctrl_regs *pinctrl_regs = + (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set DDR2 mode */ + writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + /* Power up PLL0 */ + writel(CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + + early_delay(11000); + + mx28_mem_init_clock(); + + mx28_mem_setup_vdda(); + + /* + * Configure the DRAM registers + */ + + /* Clear START bit from DRAM_CTL16 */ + clrbits_le32(MXS_DRAM_BASE + 0x40, 1); + + init_m28_200mhz_ddr2(); + + /* Clear SREFRESH bit from DRAM_CTL17 */ + clrbits_le32(MXS_DRAM_BASE + 0x44, 1); + + /* Set START bit in DRAM_CTL16 */ + setbits_le32(MXS_DRAM_BASE + 0x40, 1); + + /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ + while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) + ; + + mx28_mem_setup_vddd(); + + early_delay(10000); + + mx28_mem_setup_cpu_and_hbus(); +} diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c new file mode 100644 index 0000000..4b09b0c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -0,0 +1,1007 @@ +/* + * Freescale i.MX28 Boot PMIC init + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +#include "mx28_init.h" + +void mx28_power_clock2xtal(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Set XTAL as CPU reference clock */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); +} + +void mx28_power_clock2pll(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, + CLKCTRL_PLL0CTRL0_POWER); + early_delay(100); + setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, + CLKCTRL_CLKSEQ_BYPASS_CPU); +} + +void mx28_power_clear_auto_restart(void) +{ + struct mx28_rtc_regs *rtc_regs = + (struct mx28_rtc_regs *)MXS_RTC_BASE; + + writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) + ; + + writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) + ; + + /* + * Due to the hardware design bug of mx28 EVK-A + * we need to set the AUTO_RESTART bit. + */ + if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) + return; + + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + + setbits_le32(&rtc_regs->hw_rtc_persistent0, + RTC_PERSISTENT0_AUTO_RESTART); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) + ; +} + +void mx28_power_set_linreg(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Set linear regulator 25mV below switching converter */ + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_LINREG_OFFSET_MASK, + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_LINREG_OFFSET_MASK, + POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); +} + +int mx28_get_batt_volt(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + return volt; +} + +int mx28_is_batt_ready(void) +{ + return (mx28_get_batt_volt() >= 3600); +} + +int mx28_is_batt_good(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = mx28_get_batt_volt(); + + if ((volt >= 2400) && (volt <= 4300)) + return 1; + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_charge, + POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + early_delay(500000); + + volt = mx28_get_batt_volt(); + + if (volt >= 3500) + return 0; + + if (volt >= 2400) + return 1; + + writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + &power_regs->hw_power_charge_clr); + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + return 0; +} + +void mx28_power_setup_5v_detect(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Start 5V detection */ + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, + POWER_5VCTRL_VBUSVALID_TRSH_4V4 | + POWER_5VCTRL_PWRUP_VBUS_CMPS); +} + +void mx28_src_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Improve efficieny and reduce transient ripple */ + writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | + POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); + + clrsetbits_le32(&power_regs->hw_power_dclimits, + POWER_DCLIMITS_POSLIMIT_BUCK_MASK, + 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); + + setbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_EN_BATADJ); + + /* Increase the RCSCALE level for quick DCDC response to dynamic load */ + clrsetbits_le32(&power_regs->hw_power_loopctrl, + POWER_LOOPCTRL_EN_RCSCALE_MASK, + POWER_LOOPCTRL_RCSCALE_THRESH | + POWER_LOOPCTRL_EN_RCSCALE_8X); + + clrsetbits_le32(&power_regs->hw_power_minpwr, + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); + + /* 5V to battery handoff ... FIXME */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); +} + +void mx28_power_init_4p2_params(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Setup 4P2 parameters */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, + POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_HEADROOM_ADJ_MASK, + 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); + + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_DROPOUT_CTRL_MASK, + POWER_DCDC4P2_DROPOUT_CTRL_100MV | + POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +} + +void mx28_enable_4p2_dcdc_input(int xfer) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; + uint32_t prev_5v_brnout, prev_5v_droop; + + prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_PWDN_5VBRNOUT; + prev_5v_droop = readl(&power_regs->hw_power_ctrl) & + POWER_CTRL_ENIRQ_VDD5V_DROOP; + + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + + clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); + + if (xfer && (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return; + } + + /* + * Recording orignal values that will be modified temporarlily + * to handle a chip bug. See chip errata for CQ ENGR00115837 + */ + tmp = readl(&power_regs->hw_power_5vctrl); + vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; + vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; + + pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; + + /* + * Disable mechanisms that get erroneously tripped by when setting + * the DCDC4P2 EN_DCDC + */ + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_5VDETECT | + POWER_5VCTRL_VBUSVALID_TRSH_MASK); + + writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); + + if (xfer) { + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + early_delay(20); + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ENABLE_DCDC); + } else { + setbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + } + + early_delay(25); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); + + if (vbus_5vdetect) + writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); + + if (!pwd_bo) + clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) + writel(POWER_CTRL_VBUS_VALID_IRQ, + &power_regs->hw_power_ctrl_clr); + + if (prev_5v_brnout) { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_set); + writel(POWER_RESET_UNLOCK_KEY, + &power_regs->hw_power_reset); + } else { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + } + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) + writel(POWER_CTRL_VDD5V_DROOP_IRQ, + &power_regs->hw_power_ctrl_clr); + + if (prev_5v_droop) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); + else + setbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); +} + +void mx28_power_init_4p2_regulator(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, tmp2; + + setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); + + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); + + writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + &power_regs->hw_power_5vctrl_clr); + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); + + /* Power up the 4p2 rail and logic/control */ + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + /* + * Start charging up the 4p2 capacitor. We ramp of this charge + * gradually to avoid large inrush current from the 5V cable which can + * cause transients/problems + */ + mx28_enable_4p2_dcdc_input(0); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + /* + * If we arrived here, we were unable to recover from mx23 chip + * errata 5837. 4P2 is disabled and sufficient battery power is + * not present. Exiting to not enable DCDC power during 5V + * connected state. + */ + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + hang(); + } + + /* + * Here we set the 4p2 brownout level to something very close to 4.2V. + * We then check the brownout status. If the brownout status is false, + * the voltage is already close to the target voltage of 4.2V so we + * can go ahead and set the 4P2 current limit to our max target limit. + * If the brownout status is true, we need to ramp us the current limit + * so that we don't cause large inrush current issues. We step up the + * current limit until the brownout status is false or until we've + * reached our maximum defined 4p2 current limit. + */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_BO_MASK, + 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ + + if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { + setbits_le32(&power_regs->hw_power_5vctrl, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + } else { + tmp = (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + while (tmp < 0x3f) { + if (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DCDC_4P2_BO)) { + tmp = readl(&power_regs->hw_power_5vctrl); + tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + early_delay(100); + writel(tmp, &power_regs->hw_power_5vctrl); + break; + } else { + tmp++; + tmp2 = readl(&power_regs->hw_power_5vctrl); + tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + tmp2 |= tmp << + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + writel(tmp2, &power_regs->hw_power_5vctrl); + early_delay(100); + } + } + } + + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +} + +void mx28_power_init_dcdc_4p2_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + if (!(readl(&power_regs->hw_power_dcdc4p2) & + POWER_DCDC4P2_ENABLE_DCDC)) { + hang(); + } + + mx28_enable_4p2_dcdc_input(1); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_ENABLE_DCDC, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + } +} + +void mx28_power_enable_4p2(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t vdddctrl, vddactrl, vddioctrl; + uint32_t tmp; + + vdddctrl = readl(&power_regs->hw_power_vdddctrl); + vddactrl = readl(&power_regs->hw_power_vddactrl); + vddioctrl = readl(&power_regs->hw_power_vddioctrl); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); + + mx28_power_init_4p2_params(); + mx28_power_init_4p2_regulator(); + + /* Shutdown battery (none present) */ + if (!mx28_is_batt_ready()) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, + &power_regs->hw_power_ctrl_clr); + } + + mx28_power_init_dcdc_4p2_source(); + + writel(vdddctrl, &power_regs->hw_power_vdddctrl); + early_delay(20); + writel(vddactrl, &power_regs->hw_power_vddactrl); + early_delay(20); + writel(vddioctrl, &power_regs->hw_power_vddioctrl); + + /* + * Check if FET is enabled on either powerout and if so, + * disable load. + */ + tmp = 0; + tmp |= !(readl(&power_regs->hw_power_vdddctrl) & + POWER_VDDDCTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddactrl) & + POWER_VDDACTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddioctrl) & + POWER_VDDIOCTRL_DISABLE_FET); + if (tmp) + writel(POWER_CHARGE_ENABLE_LOAD, + &power_regs->hw_power_charge_clr); +} + +void mx28_boot_valid_5v(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V + * disconnect event. FIXME + */ + writel(POWER_5VCTRL_VBUSVALID_5VDETECT, + &power_regs->hw_power_5vctrl_set); + + /* Configure polarity to check for 5V disconnection. */ + writel(POWER_CTRL_POLARITY_VBUSVALID | + POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, + &power_regs->hw_power_ctrl_clr); + + writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + &power_regs->hw_power_ctrl_clr); + + mx28_power_enable_4p2(); +} + +void mx28_powerdown(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); +} + +void mx28_batt_boot(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); + + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); + + /* 5V to battery handoff. */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_minpwr, + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); + + mx28_power_set_linreg(); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); + + clrbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); + + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_PWD_CHARGE_4P2_MASK); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ENABLE_DCDC); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +} + +void mx28_handle_5v_conflict(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + + for (;;) { + tmp = readl(&power_regs->hw_power_sts); + + if (tmp & POWER_STS_VDDIO_BO) { + mx28_powerdown(); + break; + } + + if (tmp & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + break; + } else { + mx28_powerdown(); + break; + } + + if (tmp & POWER_STS_PSWITCH_MASK) { + mx28_batt_boot(); + break; + } + } +} + +void mx28_5v_boot(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, + * but their implementation always returns 1 so we omit it here. + */ + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + early_delay(1000); + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + mx28_handle_5v_conflict(); +} + +void mx28_init_batt_bo(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Brownout at 3V */ + clrsetbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BRWNOUT_LVL_MASK, + 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); + + writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); +} + +void mx28_switch_vddd_to_dcdc_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_DISABLE_STEPPING); +} + +void mx28_power_configure_power_source(void) +{ + int batt_ready, batt_good; + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + struct mx28_lradc_regs *lradc_regs = + (struct mx28_lradc_regs *)MXS_LRADC_BASE; + + mx28_src_power_init(); + + batt_ready = mx28_is_batt_ready(); + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + batt_good = mx28_is_batt_good(); + if (batt_ready) { + /* 5V source detected, good battery detected. */ + mx28_batt_boot(); + } else { + if (batt_good) { + /* 5V source detected, low battery detceted. */ + } else { + /* 5V source detected, bad battery detected. */ + writel(LRADC_CONVERSION_AUTOMATIC, + &lradc_regs->hw_lradc_conversion_clr); + clrbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BATT_VAL_MASK); + } + mx28_5v_boot(); + } + } else { + /* 5V not detected, booting from battery. */ + mx28_batt_boot(); + } + + mx28_power_clock2pll(); + + mx28_init_batt_bo(); + + mx28_switch_vddd_to_dcdc_source(); +} + +void mx28_enable_output_rail_protection(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_PWDN_BRNOUT); +} + +int mx28_get_vddio_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + tmp = readl(&power_regs->hw_power_vddioctrl); + if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + } + + return 0; + +} + +int mx28_get_vddd_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + tmp = readl(&power_regs->hw_power_vdddctrl); + if (tmp & POWER_VDDDCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return 1; + } + } + + if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { + return 1; + } + } + + return 0; +} + +void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + + powered_by_linreg = mx28_get_vddio_power_source_off(); + if (new_target > cur_target) { + + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vddioctrl); + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) + early_delay(500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDIO_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) + early_delay(500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + + powered_by_linreg = mx28_get_vddd_power_source_off(); + if (new_target > cur_target) { + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vdddctrl); + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK); + + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) + early_delay(500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDD_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) + early_delay(500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_setup_batt_detect(void) +{ + mx28_lradc_init(); + mx28_lradc_enable_batt_measurement(); + early_delay(10); +} + +void mx28_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + mx28_power_clock2xtal(); + mx28_power_clear_auto_restart(); + mx28_power_set_linreg(); + mx28_power_setup_5v_detect(); + + mx28_setup_batt_detect(); + + mx28_power_configure_power_source(); + mx28_enable_output_rail_protection(); + + mx28_power_set_vddio(3300, 3150); + + mx28_power_set_vddd(1350, 1200); + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | + POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | + POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); + + early_delay(1000); +} + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) + ; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S new file mode 100644 index 0000000..e572b78 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -0,0 +1,247 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Groger mag@sysgo.de + * Copyright (c) 2002 Alex Zupke azu@sysgo.de + * Copyright (c) 2002 Gary Jennejohn garyj@denx.de + * Copyright (c) 2003 Richard Woodruff r-woodruff2@ti.com + * Copyright (c) 2003 Kshitij kshitij@ti.com + * Copyright (c) 2010 Albert Aribaud albert.u.boot@aribaud.net + * + * Change to support call back into iMX28 bootrom + * Copyright (c) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <common.h> +#include <version.h> + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: + b reset + b undefined_instruction + b software_interrupt + b prefetch_abort + b data_abort + b not_used + b irq + b fiq + +/* + * Vector table, located at address 0x20. + * This table allows the code running AFTER SPL, the U-Boot, to install it's + * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, + * including it's interrupt vectoring table and the table at 0x0 is still the + * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table + * is still used. + */ +_vt_reset: + .word _reset +_vt_undefined_instruction: + .word _hang +_vt_software_interrupt: + .word _hang +_vt_prefetch_abort: + .word _hang +_vt_data_abort: + .word _hang +_vt_not_used: + .word _reset +_vt_irq: + .word _hang +_vt_fiq: + .word _hang + +reset: + ldr pc, _vt_reset +undefined_instruction: + ldr pc, _vt_undefined_instruction +software_interrupt: + ldr pc, _vt_software_interrupt +prefetch_abort: + ldr pc, _vt_prefetch_abort +data_abort: + ldr pc, _vt_data_abort +not_used: + ldr pc, _vt_not_used +irq: + ldr pc, _vt_irq +fiq: + ldr pc, _vt_fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end__ - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +_reset: + /* + * Store all registers on old stack pointer, this will allow us later to + * return to the BootROM and let the BootROM load U-Boot into RAM. + */ + push {r0-r12,r14} + + /* save control register c1 */ + mrc p15, 0, r0, c1, c0, 0 + push {r0} + + /* + * set the cpu to SVC32 mode and store old CPSR register content + */ + mrs r0,cpsr + push {r0} + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + bl board_init_ll + + /* + * restore bootrom's cpu mode (especially FIQ) + */ + pop {r0} + msr cpsr,r0 + + /* + * restore c1 register + * (especially set exception vector location back to + * bootrom space which is required by bootrom for USB boot) + */ + pop {r0} + mcr p15, 0, r0, c1, c0, 0 + + pop {r0-r12,r14} + bx lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr /* back to my caller */ + + .align 5 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c new file mode 100644 index 0000000..5b73f4a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -0,0 +1,156 @@ +/* + * Freescale i.MX28 timer driver + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +/* Maximum fixed count */ +#define TIMER_LOAD_VAL 0xffffffff + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp (gd->tbl) +#define lastdec (gd->lastinc) + +/* + * This driver uses 1kHz clock source. + */ +#define MX28_INCREMENTER_HZ 1000 + +static inline unsigned long tick_to_time(unsigned long tick) +{ + return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); +} + +static inline unsigned long time_to_tick(unsigned long time) +{ + return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); +} + +/* Calculate how many ticks happen in "us" microseconds */ +static inline unsigned long us_to_tick(unsigned long us) +{ + return (us * MX28_INCREMENTER_HZ) / 1000000; +} + +int timer_init(void) +{ + struct mx28_timrot_regs *timrot_regs = + (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + + /* Reset Timers and Rotary Encoder module */ + mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); + + /* Set fixed_count to 0 */ + writel(0, &timrot_regs->hw_timrot_fixed_count0); + + /* Set UPDATE bit and 1Khz frequency */ + writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | + TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, + &timrot_regs->hw_timrot_timctrl0); + + /* Set fixed_count to maximal value */ + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); + + return 0; +} + +unsigned long long get_ticks(void) +{ + struct mx28_timrot_regs *timrot_regs = + (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + + /* Current tick value */ + uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (lastdec - now); + } else { + /* we have rollover of decrementer */ + timestamp += (TIMER_LOAD_VAL - now) + lastdec; + + } + lastdec = now; + + return timestamp; +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ +#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 + +void __udelay(unsigned long usec) +{ + uint32_t old, new, incr; + uint32_t counter = 0; + + old = readl(MX28_HW_DIGCTL_MICROSECONDS); + + while (counter < usec) { + new = readl(MX28_HW_DIGCTL_MICROSECONDS); + + /* Check if the timer wrapped. */ + if (new < old) { + incr = 0xffffffff - old; + incr += new; + } else { + incr = new - old; + } + + /* + * Check if we are close to the maximum time and the counter + * would wrap if incremented. If that's the case, break out + * from the loop as the requested delay time passed. + */ + if (counter + incr < counter) + break; + + counter += incr; + old = new; + } +} + +ulong get_tbclk(void) +{ + return MX28_INCREMENTER_HZ; +} diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds new file mode 100644 index 0000000..f8ea38c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm926ejs/mxs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-mx28/clock.h b/arch/arm/include/asm/arch-mx28/clock.h deleted file mode 100644 index 1700fe3..0000000 --- a/arch/arm/include/asm/arch-mx28/clock.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Freescale i.MX28 Clock - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __CLOCK_H__ -#define __CLOCK_H__ - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_EMI_CLK, - MXC_GPMI_CLK, - MXC_IO0_CLK, - MXC_IO1_CLK, - MXC_SSP0_CLK, - MXC_SSP1_CLK, - MXC_SSP2_CLK, - MXC_SSP3_CLK, -}; - -enum mxs_ioclock { - MXC_IOCLK0 = 0, - MXC_IOCLK1, -}; - -enum mxs_sspclock { - MXC_SSPCLK0 = 0, - MXC_SSPCLK1, - MXC_SSPCLK2, - MXC_SSPCLK3, -}; - -uint32_t mxc_get_clock(enum mxc_clock clk); - -void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq); -void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); -void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq); - -/* Compatibility with the FEC Ethernet driver */ -#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) - -#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h deleted file mode 100644 index 4a1820b..0000000 --- a/arch/arm/include/asm/arch-mx28/dma.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale i.MX28 APBH DMA - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __DMA_H__ -#define __DMA_H__ - -#include <linux/list.h> - -#ifndef CONFIG_ARCH_DMA_PIO_WORDS -#define DMA_PIO_WORDS 15 -#else -#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS -#endif - -#define MXS_DMA_ALIGNMENT 32 - -/* - * MXS DMA channels - */ -enum { - MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, - MXS_DMA_CHANNEL_AHB_APBH_SSP1, - MXS_DMA_CHANNEL_AHB_APBH_SSP2, - MXS_DMA_CHANNEL_AHB_APBH_SSP3, - MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI1, - MXS_DMA_CHANNEL_AHB_APBH_GPMI2, - MXS_DMA_CHANNEL_AHB_APBH_GPMI3, - MXS_DMA_CHANNEL_AHB_APBH_GPMI4, - MXS_DMA_CHANNEL_AHB_APBH_GPMI5, - MXS_DMA_CHANNEL_AHB_APBH_GPMI6, - MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - MXS_DMA_CHANNEL_AHB_APBH_SSP, - MXS_MAX_DMA_CHANNELS, -}; - -/* - * MXS DMA hardware command. - * - * This structure describes the in-memory layout of an entire DMA command, - * including space for the maximum number of PIO accesses. See the appropriate - * reference manual for a detailed description of what these fields mean to the - * DMA hardware. - */ -#define MXS_DMA_DESC_COMMAND_MASK 0x3 -#define MXS_DMA_DESC_COMMAND_OFFSET 0 -#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 -#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 -#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 -#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 -#define MXS_DMA_DESC_CHAIN (1 << 2) -#define MXS_DMA_DESC_IRQ (1 << 3) -#define MXS_DMA_DESC_NAND_LOCK (1 << 4) -#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) -#define MXS_DMA_DESC_DEC_SEM (1 << 6) -#define MXS_DMA_DESC_WAIT4END (1 << 7) -#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) -#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) -#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) -#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 -#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) -#define MXS_DMA_DESC_BYTES_OFFSET 16 - -struct mxs_dma_cmd { - unsigned long next; - unsigned long data; - union { - dma_addr_t address; - unsigned long alternate; - }; - unsigned long pio_words[DMA_PIO_WORDS]; -}; - -/* - * MXS DMA command descriptor. - * - * This structure incorporates an MXS DMA hardware command structure, along - * with metadata. - */ -#define MXS_DMA_DESC_FIRST (1 << 0) -#define MXS_DMA_DESC_LAST (1 << 1) -#define MXS_DMA_DESC_READY (1 << 31) - -struct mxs_dma_desc { - struct mxs_dma_cmd cmd; - unsigned int flags; - dma_addr_t address; - void *buffer; - struct list_head node; -}; - -/** - * MXS DMA channel - * - * This structure represents a single DMA channel. The MXS platform code - * maintains an array of these structures to represent every DMA channel in the - * system (see mxs_dma_channels). - */ -#define MXS_DMA_FLAGS_IDLE 0 -#define MXS_DMA_FLAGS_BUSY (1 << 0) -#define MXS_DMA_FLAGS_FREE 0 -#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) -#define MXS_DMA_FLAGS_VALID (1 << 31) - -struct mxs_dma_chan { - const char *name; - unsigned long dev; - struct mxs_dma_device *dma; - unsigned int flags; - unsigned int active_num; - unsigned int pending_num; - struct list_head active; - struct list_head done; -}; - -struct mxs_dma_desc *mxs_dma_desc_alloc(void); -void mxs_dma_desc_free(struct mxs_dma_desc *); -int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); - -int mxs_dma_go(int chan); -void mxs_dma_init(void); -int mxs_dma_init_channel(int chan); -int mxs_dma_release(int chan); - -#endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/gpio.h b/arch/arm/include/asm/arch-mx28/gpio.h deleted file mode 100644 index be1c944..0000000 --- a/arch/arm/include/asm/arch-mx28/gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Freescale i.MX28 GPIO - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_GPIO_H__ -#define __MX28_GPIO_H__ - -#ifdef CONFIG_MXS_GPIO -void mxs_gpio_init(void); -#else -inline void mxs_gpio_init(void) {} -#endif - -#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h deleted file mode 100644 index 37d0a93..0000000 --- a/arch/arm/include/asm/arch-mx28/imx-regs.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Freescale i.MX28 Registers - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __IMX_REGS_H__ -#define __IMX_REGS_H__ - -#include <asm/arch/regs-apbh.h> -#include <asm/arch/regs-base.h> -#include <asm/arch/regs-bch.h> -#include <asm/arch/regs-clkctrl.h> -#include <asm/arch/regs-digctl.h> -#include <asm/arch/regs-gpmi.h> -#include <asm/arch/regs-i2c.h> -#include <asm/arch/regs-lcdif.h> -#include <asm/arch/regs-lradc.h> -#include <asm/arch/regs-ocotp.h> -#include <asm/arch/regs-pinctrl.h> -#include <asm/arch/regs-power.h> -#include <asm/arch/regs-rtc.h> -#include <asm/arch/regs-ssp.h> -#include <asm/arch/regs-timrot.h> - -#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux-mx28.h b/arch/arm/include/asm/arch-mx28/iomux-mx28.h deleted file mode 100644 index b42820d..0000000 --- a/arch/arm/include/asm/arch-mx28/iomux-mx28.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria amit.kucheria@canonical.com - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux.h b/arch/arm/include/asm/arch-mx28/iomux.h deleted file mode 100644 index 7abdf58..0000000 --- a/arch/arm/include/asm/arch-mx28/iomux.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * armlinux@phytec.de - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#define PAD_3V3 1 - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h deleted file mode 100644 index 91d7bc8..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-apbh.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * Freescale i.MX28 APBH Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __REGS_APBH_H__ -#define __REGS_APBH_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_apbh_regs { - mx28_reg_32(hw_apbh_ctrl0) - mx28_reg_32(hw_apbh_ctrl1) - mx28_reg_32(hw_apbh_ctrl2) - mx28_reg_32(hw_apbh_channel_ctrl) - mx28_reg_32(hw_apbh_devsel) - mx28_reg_32(hw_apbh_dma_burst_size) - mx28_reg_32(hw_apbh_debug) - - uint32_t reserved[36]; - - union { - struct { - mx28_reg_32(hw_apbh_ch_curcmdar) - mx28_reg_32(hw_apbh_ch_nxtcmdar) - mx28_reg_32(hw_apbh_ch_cmd) - mx28_reg_32(hw_apbh_ch_bar) - mx28_reg_32(hw_apbh_ch_sema) - mx28_reg_32(hw_apbh_ch_debug1) - mx28_reg_32(hw_apbh_ch_debug2) - } ch[16]; - struct { - mx28_reg_32(hw_apbh_ch0_curcmdar) - mx28_reg_32(hw_apbh_ch0_nxtcmdar) - mx28_reg_32(hw_apbh_ch0_cmd) - mx28_reg_32(hw_apbh_ch0_bar) - mx28_reg_32(hw_apbh_ch0_sema) - mx28_reg_32(hw_apbh_ch0_debug1) - mx28_reg_32(hw_apbh_ch0_debug2) - mx28_reg_32(hw_apbh_ch1_curcmdar) - mx28_reg_32(hw_apbh_ch1_nxtcmdar) - mx28_reg_32(hw_apbh_ch1_cmd) - mx28_reg_32(hw_apbh_ch1_bar) - mx28_reg_32(hw_apbh_ch1_sema) - mx28_reg_32(hw_apbh_ch1_debug1) - mx28_reg_32(hw_apbh_ch1_debug2) - mx28_reg_32(hw_apbh_ch2_curcmdar) - mx28_reg_32(hw_apbh_ch2_nxtcmdar) - mx28_reg_32(hw_apbh_ch2_cmd) - mx28_reg_32(hw_apbh_ch2_bar) - mx28_reg_32(hw_apbh_ch2_sema) - mx28_reg_32(hw_apbh_ch2_debug1) - mx28_reg_32(hw_apbh_ch2_debug2) - mx28_reg_32(hw_apbh_ch3_curcmdar) - mx28_reg_32(hw_apbh_ch3_nxtcmdar) - mx28_reg_32(hw_apbh_ch3_cmd) - mx28_reg_32(hw_apbh_ch3_bar) - mx28_reg_32(hw_apbh_ch3_sema) - mx28_reg_32(hw_apbh_ch3_debug1) - mx28_reg_32(hw_apbh_ch3_debug2) - mx28_reg_32(hw_apbh_ch4_curcmdar) - mx28_reg_32(hw_apbh_ch4_nxtcmdar) - mx28_reg_32(hw_apbh_ch4_cmd) - mx28_reg_32(hw_apbh_ch4_bar) - mx28_reg_32(hw_apbh_ch4_sema) - mx28_reg_32(hw_apbh_ch4_debug1) - mx28_reg_32(hw_apbh_ch4_debug2) - mx28_reg_32(hw_apbh_ch5_curcmdar) - mx28_reg_32(hw_apbh_ch5_nxtcmdar) - mx28_reg_32(hw_apbh_ch5_cmd) - mx28_reg_32(hw_apbh_ch5_bar) - mx28_reg_32(hw_apbh_ch5_sema) - mx28_reg_32(hw_apbh_ch5_debug1) - mx28_reg_32(hw_apbh_ch5_debug2) - mx28_reg_32(hw_apbh_ch6_curcmdar) - mx28_reg_32(hw_apbh_ch6_nxtcmdar) - mx28_reg_32(hw_apbh_ch6_cmd) - mx28_reg_32(hw_apbh_ch6_bar) - mx28_reg_32(hw_apbh_ch6_sema) - mx28_reg_32(hw_apbh_ch6_debug1) - mx28_reg_32(hw_apbh_ch6_debug2) - mx28_reg_32(hw_apbh_ch7_curcmdar) - mx28_reg_32(hw_apbh_ch7_nxtcmdar) - mx28_reg_32(hw_apbh_ch7_cmd) - mx28_reg_32(hw_apbh_ch7_bar) - mx28_reg_32(hw_apbh_ch7_sema) - mx28_reg_32(hw_apbh_ch7_debug1) - mx28_reg_32(hw_apbh_ch7_debug2) - mx28_reg_32(hw_apbh_ch8_curcmdar) - mx28_reg_32(hw_apbh_ch8_nxtcmdar) - mx28_reg_32(hw_apbh_ch8_cmd) - mx28_reg_32(hw_apbh_ch8_bar) - mx28_reg_32(hw_apbh_ch8_sema) - mx28_reg_32(hw_apbh_ch8_debug1) - mx28_reg_32(hw_apbh_ch8_debug2) - mx28_reg_32(hw_apbh_ch9_curcmdar) - mx28_reg_32(hw_apbh_ch9_nxtcmdar) - mx28_reg_32(hw_apbh_ch9_cmd) - mx28_reg_32(hw_apbh_ch9_bar) - mx28_reg_32(hw_apbh_ch9_sema) - mx28_reg_32(hw_apbh_ch9_debug1) - mx28_reg_32(hw_apbh_ch9_debug2) - mx28_reg_32(hw_apbh_ch10_curcmdar) - mx28_reg_32(hw_apbh_ch10_nxtcmdar) - mx28_reg_32(hw_apbh_ch10_cmd) - mx28_reg_32(hw_apbh_ch10_bar) - mx28_reg_32(hw_apbh_ch10_sema) - mx28_reg_32(hw_apbh_ch10_debug1) - mx28_reg_32(hw_apbh_ch10_debug2) - mx28_reg_32(hw_apbh_ch11_curcmdar) - mx28_reg_32(hw_apbh_ch11_nxtcmdar) - mx28_reg_32(hw_apbh_ch11_cmd) - mx28_reg_32(hw_apbh_ch11_bar) - mx28_reg_32(hw_apbh_ch11_sema) - mx28_reg_32(hw_apbh_ch11_debug1) - mx28_reg_32(hw_apbh_ch11_debug2) - mx28_reg_32(hw_apbh_ch12_curcmdar) - mx28_reg_32(hw_apbh_ch12_nxtcmdar) - mx28_reg_32(hw_apbh_ch12_cmd) - mx28_reg_32(hw_apbh_ch12_bar) - mx28_reg_32(hw_apbh_ch12_sema) - mx28_reg_32(hw_apbh_ch12_debug1) - mx28_reg_32(hw_apbh_ch12_debug2) - mx28_reg_32(hw_apbh_ch13_curcmdar) - mx28_reg_32(hw_apbh_ch13_nxtcmdar) - mx28_reg_32(hw_apbh_ch13_cmd) - mx28_reg_32(hw_apbh_ch13_bar) - mx28_reg_32(hw_apbh_ch13_sema) - mx28_reg_32(hw_apbh_ch13_debug1) - mx28_reg_32(hw_apbh_ch13_debug2) - mx28_reg_32(hw_apbh_ch14_curcmdar) - mx28_reg_32(hw_apbh_ch14_nxtcmdar) - mx28_reg_32(hw_apbh_ch14_cmd) - mx28_reg_32(hw_apbh_ch14_bar) - mx28_reg_32(hw_apbh_ch14_sema) - mx28_reg_32(hw_apbh_ch14_debug1) - mx28_reg_32(hw_apbh_ch14_debug2) - mx28_reg_32(hw_apbh_ch15_curcmdar) - mx28_reg_32(hw_apbh_ch15_nxtcmdar) - mx28_reg_32(hw_apbh_ch15_cmd) - mx28_reg_32(hw_apbh_ch15_bar) - mx28_reg_32(hw_apbh_ch15_sema) - mx28_reg_32(hw_apbh_ch15_debug1) - mx28_reg_32(hw_apbh_ch15_debug2) - }; - }; - mx28_reg_32(hw_apbh_version) -}; -#endif - -#define APBH_CTRL0_SFTRST (1 << 31) -#define APBH_CTRL0_CLKGATE (1 << 30) -#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) -#define APBH_CTRL0_APB_BURST_EN (1 << 28) -#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) -#define APBH_CTRL0_RSVD0_OFFSET 16 -#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 -#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 -#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 - -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) -#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 -#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) - -#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) -#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) -#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) -#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) -#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) -#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) -#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) -#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) -#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) -#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) -#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) -#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) -#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) -#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) -#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) -#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) -#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) -#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) -#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) -#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) -#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) -#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) -#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) -#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) -#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) -#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) -#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) -#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) -#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) -#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) -#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) -#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) - -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 - -#define APBH_DEVSEL_CH15_MASK (0x3 << 30) -#define APBH_DEVSEL_CH15_OFFSET 30 -#define APBH_DEVSEL_CH14_MASK (0x3 << 28) -#define APBH_DEVSEL_CH14_OFFSET 28 -#define APBH_DEVSEL_CH13_MASK (0x3 << 26) -#define APBH_DEVSEL_CH13_OFFSET 26 -#define APBH_DEVSEL_CH12_MASK (0x3 << 24) -#define APBH_DEVSEL_CH12_OFFSET 24 -#define APBH_DEVSEL_CH11_MASK (0x3 << 22) -#define APBH_DEVSEL_CH11_OFFSET 22 -#define APBH_DEVSEL_CH10_MASK (0x3 << 20) -#define APBH_DEVSEL_CH10_OFFSET 20 -#define APBH_DEVSEL_CH9_MASK (0x3 << 18) -#define APBH_DEVSEL_CH9_OFFSET 18 -#define APBH_DEVSEL_CH8_MASK (0x3 << 16) -#define APBH_DEVSEL_CH8_OFFSET 16 -#define APBH_DEVSEL_CH7_MASK (0x3 << 14) -#define APBH_DEVSEL_CH7_OFFSET 14 -#define APBH_DEVSEL_CH6_MASK (0x3 << 12) -#define APBH_DEVSEL_CH6_OFFSET 12 -#define APBH_DEVSEL_CH5_MASK (0x3 << 10) -#define APBH_DEVSEL_CH5_OFFSET 10 -#define APBH_DEVSEL_CH4_MASK (0x3 << 8) -#define APBH_DEVSEL_CH4_OFFSET 8 -#define APBH_DEVSEL_CH3_MASK (0x3 << 6) -#define APBH_DEVSEL_CH3_OFFSET 6 -#define APBH_DEVSEL_CH2_MASK (0x3 << 4) -#define APBH_DEVSEL_CH2_OFFSET 4 -#define APBH_DEVSEL_CH1_MASK (0x3 << 2) -#define APBH_DEVSEL_CH1_OFFSET 2 -#define APBH_DEVSEL_CH0_MASK (0x3 << 0) -#define APBH_DEVSEL_CH0_OFFSET 0 - -#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) -#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 -#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) -#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 -#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) -#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 -#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) -#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 -#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) -#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 -#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) -#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 -#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) -#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 -#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) -#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 -#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) -#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) -#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) -#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) -#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 -#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) -#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 -#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) -#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 -#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) -#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 -#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) -#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 -#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) -#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) -#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) - -#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) -#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 -#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) -#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) -#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) -#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) -#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 -#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) -#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) -#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) - -#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 -#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 -#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 -#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 -#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 - -#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) - -#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff -#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 - -#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff -#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 - -#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) -#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 -#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) -#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 -#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) -#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) -#define APBH_CHn_CMD_SEMAPHORE (1 << 6) -#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) -#define APBH_CHn_CMD_NANDLOCK (1 << 4) -#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) -#define APBH_CHn_CMD_CHAIN (1 << 2) -#define APBH_CHn_CMD_COMMAND_MASK 0x3 -#define APBH_CHn_CMD_COMMAND_OFFSET 0 -#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 -#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 -#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 -#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 - -#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff -#define APBH_CHn_BAR_ADDRESS_OFFSET 0 - -#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) -#define APBH_CHn_SEMA_RSVD2_OFFSET 24 -#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) -#define APBH_CHn_SEMA_PHORE_OFFSET 16 -#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) -#define APBH_CHn_SEMA_RSVD1_OFFSET 8 -#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) -#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 - -#define APBH_CHn_DEBUG1_REQ (1 << 31) -#define APBH_CHn_DEBUG1_BURST (1 << 30) -#define APBH_CHn_DEBUG1_KICK (1 << 29) -#define APBH_CHn_DEBUG1_END (1 << 28) -#define APBH_CHn_DEBUG1_SENSE (1 << 27) -#define APBH_CHn_DEBUG1_READY (1 << 26) -#define APBH_CHn_DEBUG1_LOCK (1 << 25) -#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) -#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) -#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) -#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) -#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) -#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) -#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 -#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f -#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 -#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 -#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 -#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 -#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d -#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e -#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f -#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 -#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 -#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c -#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d -#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e -#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f - -#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) -#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 -#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff -#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 - -#define APBH_VERSION_MAJOR_MASK (0xff << 24) -#define APBH_VERSION_MAJOR_OFFSET 24 -#define APBH_VERSION_MINOR_MASK (0xff << 16) -#define APBH_VERSION_MINOR_OFFSET 16 -#define APBH_VERSION_STEP_MASK 0xffff -#define APBH_VERSION_STEP_OFFSET 0 - -#endif /* __REGS_APBH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-base.h b/arch/arm/include/asm/arch-mx28/regs-base.h deleted file mode 100644 index dbdcc2b..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-base.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Freescale i.MX28 Peripheral Base Addresses - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_BASE_H__ -#define __MX28_REGS_BASE_H__ - -/* - * Register base address - */ -#define MXS_ICOL_BASE 0x80000000 -#define MXS_HSADC_BASE 0x80002000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_PERFMON_BASE 0x80006000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80012000 -#define MXS_SSP2_BASE 0x80014000 -#define MXS_SSP3_BASE 0x80016000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_ETM_BASE 0x80022000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_AHB0_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_CAN0_BASE 0x80032000 -#define MXS_CAN1_BASE 0x80034000 -#define MXS_SIMDBG_BASE 0x8003C000 -#define MXS_SIMGPMISEL_BASE 0x8003C200 -#define MXS_SIMSSPSEL_BASE 0x8003C300 -#define MXS_SIMMEMSEL_BASE 0x8003C400 -#define MXS_GPIOMON_BASE 0x8003C500 -#define MXS_SIMENET_BASE 0x8003C700 -#define MXS_ARMJTAG_BASE 0x8003C800 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_RTC_BASE 0x80056000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_I2C1_BASE 0x8005A000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006A000 -#define MXS_UARTAPP1_BASE 0x8006C000 -#define MXS_UARTAPP2_BASE 0x8006E000 -#define MXS_UARTAPP3_BASE 0x80070000 -#define MXS_UARTAPP4_BASE 0x80072000 -#define MXS_UARTDBG_BASE 0x80074000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBPHY1_BASE 0x8007E000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_USBCTRL1_BASE 0x80090000 -#define MXS_DFLPT_BASE 0x800C0000 -#define MXS_DRAM_BASE 0x800E0000 -#define MXS_ENET0_BASE 0x800F0000 -#define MXS_ENET1_BASE 0x800F4000 - -#endif /* __MX28_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h deleted file mode 100644 index 9243bdd..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-bch.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Freescale i.MX28 BCH Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_BCH_H__ -#define __MX28_REGS_BCH_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_bch_regs { - mx28_reg_32(hw_bch_ctrl) - mx28_reg_32(hw_bch_status0) - mx28_reg_32(hw_bch_mode) - mx28_reg_32(hw_bch_encodeptr) - mx28_reg_32(hw_bch_dataptr) - mx28_reg_32(hw_bch_metaptr) - - uint32_t reserved[4]; - - mx28_reg_32(hw_bch_layoutselect) - mx28_reg_32(hw_bch_flash0layout0) - mx28_reg_32(hw_bch_flash0layout1) - mx28_reg_32(hw_bch_flash1layout0) - mx28_reg_32(hw_bch_flash1layout1) - mx28_reg_32(hw_bch_flash2layout0) - mx28_reg_32(hw_bch_flash2layout1) - mx28_reg_32(hw_bch_flash3layout0) - mx28_reg_32(hw_bch_flash3layout1) - mx28_reg_32(hw_bch_dbgkesread) - mx28_reg_32(hw_bch_dbgcsferead) - mx28_reg_32(hw_bch_dbgsyndegread) - mx28_reg_32(hw_bch_dbgahbmread) - mx28_reg_32(hw_bch_blockname) - mx28_reg_32(hw_bch_version) -}; -#endif - -#define BCH_CTRL_SFTRST (1 << 31) -#define BCH_CTRL_CLKGATE (1 << 30) -#define BCH_CTRL_DEBUGSYNDROME (1 << 22) -#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) -#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 -#define BCH_CTRL_M2M_ENCODE (1 << 17) -#define BCH_CTRL_M2M_ENABLE (1 << 16) -#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) -#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) -#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) -#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) -#define BCH_CTRL_COMPLETE_IRQ (1 << 0) - -#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) -#define BCH_STATUS0_HANDLE_OFFSET 20 -#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) -#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 -#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) -#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 -#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) -#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) -#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) -#define BCH_STATUS0_ALLONES (1 << 4) -#define BCH_STATUS0_CORRECTED (1 << 3) -#define BCH_STATUS0_UNCORRECTABLE (1 << 2) - -#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff -#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 - -#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff -#define BCH_ENCODEPTR_ADDR_OFFSET 0 - -#define BCH_DATAPTR_ADDR_MASK 0xffffffff -#define BCH_DATAPTR_ADDR_OFFSET 0 - -#define BCH_METAPTR_ADDR_MASK 0xffffffff -#define BCH_METAPTR_ADDR_OFFSET 0 - -#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) -#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 -#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) -#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 -#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) -#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 -#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) -#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 -#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) -#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 -#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) -#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 -#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) -#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 -#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) -#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 -#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) -#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 -#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) -#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 -#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) -#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 -#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) -#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 -#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) -#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 -#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) -#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 -#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) -#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 -#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) -#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 - -#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) -#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 -#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) -#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) -#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 -#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) -#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff -#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 - -#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) -#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) -#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 -#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) -#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff -#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 - -#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) -#define BCH_DEBUG0_RSVD1_OFFSET 27 -#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) -#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) -#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) -#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) -#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) -#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) -#define BCH_DEBUG0_KES_STANDALONE (1 << 11) -#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) -#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) -#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) -#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) -#define BCH_DEBUG0_RSVD0_OFFSET 6 -#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f -#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 - -#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff -#define BCH_DBGKESREAD_VALUES_OFFSET 0 - -#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff -#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 - -#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff -#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 - -#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff -#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 - -#define BCH_BLOCKNAME_NAME_MASK 0xffffffff -#define BCH_BLOCKNAME_NAME_OFFSET 0 - -#define BCH_VERSION_MAJOR_MASK (0xff << 24) -#define BCH_VERSION_MAJOR_OFFSET 24 -#define BCH_VERSION_MINOR_MASK (0xff << 16) -#define BCH_VERSION_MINOR_OFFSET 16 -#define BCH_VERSION_STEP_MASK 0xffff -#define BCH_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_BCH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h deleted file mode 100644 index 3c4947d..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Freescale i.MX28 CLKCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_CLKCTRL_H__ -#define __MX28_REGS_CLKCTRL_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_clkctrl_regs { - mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ - mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ - mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mx28_reg_32(hw_clkctrl_etm) /* 0x130 */ - mx28_reg_32(hw_clkctrl_enet) /* 0x140 */ - mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */ - - uint32_t reserved[16]; - - mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mx28_reg_32(hw_clkctrl_version) /* 0x200 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) -#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF1_DIV_MASK 0xffff -#define CLKCTRL_SAIF1_DIV_OFFSET 0 - -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) -#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff -#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) -#define CLKCTRL_ETM_DIV_MASK 0x7f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) -#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) -#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 -#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) -#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 -#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) -#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) -#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) -#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) - -#define CLKCTRL_HSADC_RESETB (1 << 30) -#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) -#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 - -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_IO1 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_PIX 0 -#define CLKCTRL_FRAC1_HSADC 1 -#define CLKCTRL_FRAC1_GPMI 2 - -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) - -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h deleted file mode 100644 index d2e1953..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Freescale i.MX28 Register Accessors - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_COMMON_H__ -#define __MX28_REGS_COMMON_H__ - -/* - * The i.MX28 has interesting feature when it comes to register access. There - * are four kinds of access to one particular register. Those are: - * - * 1) Common read/write access. To use this mode, just write to the address of - * the register. - * 2) Set bits only access. To set bits, write which bits you want to set to the - * address of the register + 0x4. - * 3) Clear bits only access. To clear bits, write which bits you want to clear - * to the address of the register + 0x8. - * 4) Toggle bits only access. To toggle bits, write which bits you want to - * toggle to the address of the register + 0xc. - * - * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits - * can be set/cleared by pure write as in access type 1, some need to be - * explicitly set/cleared by using access type 2-3. - * - * The following macros and structures allow the user to either access the - * register in all aforementioned modes (by accessing reg_name, reg_name_set, - * reg_name_clr, reg_name_tog) or pass the register structure further into - * various functions with correct type information (by accessing reg_name_reg). - * - */ - -#define __mx28_reg_8(name) \ - uint8_t name[4]; \ - uint8_t name##_set[4]; \ - uint8_t name##_clr[4]; \ - uint8_t name##_tog[4]; \ - -#define __mx28_reg_32(name) \ - uint32_t name; \ - uint32_t name##_set; \ - uint32_t name##_clr; \ - uint32_t name##_tog; - -struct mx28_register_8 { - __mx28_reg_8(reg) -}; - -struct mx28_register_32 { - __mx28_reg_32(reg) -}; - -#define mx28_reg_8(name) \ - union { \ - struct { __mx28_reg_8(name) }; \ - struct mx28_register_8 name##_reg; \ - }; - -#define mx28_reg_32(name) \ - union { \ - struct { __mx28_reg_32(name) }; \ - struct mx28_register_32 name##_reg; \ - }; - -#endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-digctl.h b/arch/arm/include/asm/arch-mx28/regs-digctl.h deleted file mode 100644 index 9a63594..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-digctl.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Freescale i.MX28 DIGCTL Register Definitions - * - * Copyright (C) 2012 Robert Delien robert@delien.nl - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_DIGCTL_H__ -#define __MX28_REGS_DIGCTL_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_digctl_regs { - mx28_reg_32(hw_digctl_ctrl) /* 0x000 */ - mx28_reg_32(hw_digctl_status) /* 0x010 */ - mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mx28_reg_32(hw_digctl_emi_status) /* 0x040 */ - mx28_reg_32(hw_digctl_read_margin) /* 0x050 */ - uint32_t hw_digctl_writeonce; /* 0x060 */ - uint32_t reserved_writeonce[3]; - mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mx28_reg_32(hw_digctl_bist_status) /* 0x080 */ - uint32_t hw_digctl_entropy; /* 0x090 */ - uint32_t reserved_entropy[3]; - uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ - uint32_t reserved_entropy_latched[3]; - - uint32_t reserved1[4]; - - mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */ - uint32_t hw_digctl_dbgrd; /* 0x0d0 */ - uint32_t reserved_hw_digctl_dbgrd[3]; - uint32_t hw_digctl_dbg; /* 0x0e0 */ - uint32_t reserved_hw_digctl_dbg[3]; - - uint32_t reserved2[4]; - - mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ - - uint32_t reserved3[36]; - - uint32_t hw_digctl_scratch0; /* 0x280 */ - uint32_t reserved_hw_digctl_scratch0[3]; - uint32_t hw_digctl_scratch1; /* 0x290 */ - uint32_t reserved_hw_digctl_scratch1[3]; - uint32_t hw_digctl_armcache; /* 0x2a0 */ - uint32_t reserved_hw_digctl_armcache[3]; - mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ - uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; - uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; - uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; - uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; - uint32_t hw_digctl_fsl; /* 0x300 */ - uint32_t reserved_hw_digctl_fsl[3]; - uint32_t hw_digctl_chipid; /* 0x310 */ - uint32_t reserved_hw_digctl_chipid[3]; - - uint32_t reserved4[4]; - - uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ - uint32_t reserved_hw_digctl_ahb_stats_select[3]; - - uint32_t reserved5[12]; - - uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ - uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; - uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ - uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; - uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ - uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; - uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ - uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; - uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; - uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; - uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ - uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; - uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; - uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; - - uint32_t reserved6[64]; - - uint32_t hw_digctl_mpte0_loc; /* 0x500 */ - uint32_t reserved_hw_digctl_mpte0_loc[3]; - uint32_t hw_digctl_mpte1_loc; /* 0x510 */ - uint32_t reserved_hw_digctl_mpte1_loc[3]; - uint32_t hw_digctl_mpte2_loc; /* 0x520 */ - uint32_t reserved_hw_digctl_mpte2_loc[3]; - uint32_t hw_digctl_mpte3_loc; /* 0x530 */ - uint32_t reserved_hw_digctl_mpte3_loc[3]; - uint32_t hw_digctl_mpte4_loc; /* 0x540 */ - uint32_t reserved_hw_digctl_mpte4_loc[3]; - uint32_t hw_digctl_mpte5_loc; /* 0x550 */ - uint32_t reserved_hw_digctl_mpte5_loc[3]; - uint32_t hw_digctl_mpte6_loc; /* 0x560 */ - uint32_t reserved_hw_digctl_mpte6_loc[3]; - uint32_t hw_digctl_mpte7_loc; /* 0x570 */ - uint32_t reserved_hw_digctl_mpte7_loc[3]; - uint32_t hw_digctl_mpte8_loc; /* 0x580 */ - uint32_t reserved_hw_digctl_mpte8_loc[3]; - uint32_t hw_digctl_mpte9_loc; /* 0x590 */ - uint32_t reserved_hw_digctl_mpte9_loc[3]; - uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ - uint32_t reserved_hw_digctl_mpte10_loc[3]; - uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ - uint32_t reserved_hw_digctl_mpte11_loc[3]; - uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ - uint32_t reserved_hw_digctl_mpte12_loc[3]; - uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ - uint32_t reserved_hw_digctl_mpte13_loc[3]; - uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ - uint32_t reserved_hw_digctl_mpte14_loc[3]; - uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ - uint32_t reserved_hw_digctl_mpte15_loc[3]; -}; -#endif - -#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h deleted file mode 100644 index 1b487f4..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-gpmi.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Freescale i.MX28 GPMI Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_GPMI_H__ -#define __MX28_REGS_GPMI_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_gpmi_regs { - mx28_reg_32(hw_gpmi_ctrl0) - mx28_reg_32(hw_gpmi_compare) - mx28_reg_32(hw_gpmi_eccctrl) - mx28_reg_32(hw_gpmi_ecccount) - mx28_reg_32(hw_gpmi_payload) - mx28_reg_32(hw_gpmi_auxiliary) - mx28_reg_32(hw_gpmi_ctrl1) - mx28_reg_32(hw_gpmi_timing0) - mx28_reg_32(hw_gpmi_timing1) - - uint32_t reserved[4]; - - mx28_reg_32(hw_gpmi_data) - mx28_reg_32(hw_gpmi_stat) - mx28_reg_32(hw_gpmi_debug) - mx28_reg_32(hw_gpmi_version) -}; -#endif - -#define GPMI_CTRL0_SFTRST (1 << 31) -#define GPMI_CTRL0_CLKGATE (1 << 30) -#define GPMI_CTRL0_RUN (1 << 29) -#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) -#define GPMI_CTRL0_LOCK_CS (1 << 27) -#define GPMI_CTRL0_UDMA (1 << 26) -#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) -#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 -#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) -#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) -#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) -#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) -#define GPMI_CTRL0_WORD_LENGTH (1 << 23) -#define GPMI_CTRL0_CS_MASK (0x7 << 20) -#define GPMI_CTRL0_CS_OFFSET 20 -#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) -#define GPMI_CTRL0_ADDRESS_OFFSET 17 -#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) -#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) -#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) -#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) -#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff -#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 - -#define GPMI_COMPARE_MASK_MASK (0xffff << 16) -#define GPMI_COMPARE_MASK_OFFSET 16 -#define GPMI_COMPARE_REFERENCE_MASK 0xffff -#define GPMI_COMPARE_REFERENCE_OFFSET 0 - -#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) -#define GPMI_ECCCTRL_HANDLE_OFFSET 16 -#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) -#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 -#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) -#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) -#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) -#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff -#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 -#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 -#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff - -#define GPMI_ECCCOUNT_COUNT_MASK 0xffff -#define GPMI_ECCCOUNT_COUNT_OFFSET 0 - -#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) -#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 - -#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) -#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 - -#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) -#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) -#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 -#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) -#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) -#define GPMI_CTRL1_BCH_MODE (1 << 18) -#define GPMI_CTRL1_DLL_ENABLE (1 << 17) -#define GPMI_CTRL1_HALF_PERIOD (1 << 16) -#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) -#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 -#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) -#define GPMI_CTRL1_DEV_IRQ (1 << 10) -#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) -#define GPMI_CTRL1_BURST_EN (1 << 8) -#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) -#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) -#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 -#define GPMI_CTRL1_DEV_RESET (1 << 3) -#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) -#define GPMI_CTRL1_CAMERA_MODE (1 << 1) -#define GPMI_CTRL1_GPMI_MODE (1 << 0) - -#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) -#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 -#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) -#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 -#define GPMI_TIMING0_DATA_SETUP_MASK 0xff -#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 - -#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) -#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 - -#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) -#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 -#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) -#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 -#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) -#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 -#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff -#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 - -#define GPMI_DATA_DATA_MASK 0xffffffff -#define GPMI_DATA_DATA_OFFSET 0 - -#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) -#define GPMI_STAT_READY_BUSY_OFFSET 24 -#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) -#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 -#define GPMI_STAT_DEV7_ERROR (1 << 15) -#define GPMI_STAT_DEV6_ERROR (1 << 14) -#define GPMI_STAT_DEV5_ERROR (1 << 13) -#define GPMI_STAT_DEV4_ERROR (1 << 12) -#define GPMI_STAT_DEV3_ERROR (1 << 11) -#define GPMI_STAT_DEV2_ERROR (1 << 10) -#define GPMI_STAT_DEV1_ERROR (1 << 9) -#define GPMI_STAT_DEV0_ERROR (1 << 8) -#define GPMI_STAT_ATA_IRQ (1 << 4) -#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) -#define GPMI_STAT_FIFO_EMPTY (1 << 2) -#define GPMI_STAT_FIFO_FULL (1 << 1) -#define GPMI_STAT_PRESENT (1 << 0) - -#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) -#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 -#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) -#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 -#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) -#define GPMI_DEBUG_DMAREQ_OFFSET 8 -#define GPMI_DEBUG_CMD_END_MASK 0xff -#define GPMI_DEBUG_CMD_END_OFFSET 0 - -#define GPMI_VERSION_MAJOR_MASK (0xff << 24) -#define GPMI_VERSION_MAJOR_OFFSET 24 -#define GPMI_VERSION_MINOR_MASK (0xff << 16) -#define GPMI_VERSION_MINOR_OFFSET 16 -#define GPMI_VERSION_STEP_MASK 0xffff -#define GPMI_VERSION_STEP_OFFSET 0 - -#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) -#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 -#define GPMI_DEBUG2_BUSY (1 << 23) -#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) -#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 -#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) -#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) -#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 -#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) -#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) -#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 -#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) -#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) -#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) -#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) -#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) -#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) -#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f -#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 - -#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) -#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 -#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff -#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 - -#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h deleted file mode 100644 index 2e2e814..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-i2c.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Freescale i.MX28 I2C Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_I2C_H__ -#define __MX28_REGS_I2C_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_i2c_regs { - mx28_reg_32(hw_i2c_ctrl0) - mx28_reg_32(hw_i2c_timing0) - mx28_reg_32(hw_i2c_timing1) - mx28_reg_32(hw_i2c_timing2) - mx28_reg_32(hw_i2c_ctrl1) - mx28_reg_32(hw_i2c_stat) - mx28_reg_32(hw_i2c_queuectrl) - mx28_reg_32(hw_i2c_queuestat) - mx28_reg_32(hw_i2c_queuecmd) - mx28_reg_32(hw_i2c_queuedata) - mx28_reg_32(hw_i2c_data) - mx28_reg_32(hw_i2c_debug0) - mx28_reg_32(hw_i2c_debug1) - mx28_reg_32(hw_i2c_version) -}; -#endif - -#define I2C_CTRL_SFTRST (1 << 31) -#define I2C_CTRL_CLKGATE (1 << 30) -#define I2C_CTRL_RUN (1 << 29) -#define I2C_CTRL_PREACK (1 << 27) -#define I2C_CTRL_ACKNOWLEDGE (1 << 26) -#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) -#define I2C_CTRL_MULTI_MASTER (1 << 23) -#define I2C_CTRL_CLOCK_HELD (1 << 22) -#define I2C_CTRL_RETAIN_CLOCK (1 << 21) -#define I2C_CTRL_POST_SEND_STOP (1 << 20) -#define I2C_CTRL_PRE_SEND_START (1 << 19) -#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_CTRL_MASTER_MODE (1 << 17) -#define I2C_CTRL_DIRECTION (1 << 16) -#define I2C_CTRL_XFER_COUNT_MASK 0xffff -#define I2C_CTRL_XFER_COUNT_OFFSET 0 - -#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 -#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff -#define I2C_TIMING0_RCV_COUNT_OFFSET 0 - -#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING1_LOW_COUNT_OFFSET 16 -#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff -#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 - -#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) -#define I2C_TIMING2_BUS_FREE_OFFSET 16 -#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff -#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 - -#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) -#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) -#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) -#define I2C_CTRL1_ACK_MODE (1 << 27) -#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) -#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) -#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 -#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) -#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) -#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) -#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) -#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) -#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) -#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) -#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) -#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) -#define I2C_CTRL1_SLAVE_IRQ (1 << 0) - -#define I2C_STAT_MASTER_PRESENT (1 << 31) -#define I2C_STAT_SLAVE_PRESENT (1 << 30) -#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) -#define I2C_STAT_GOT_A_NAK (1 << 28) -#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) -#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 -#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) -#define I2C_STAT_SLAVE_FOUND (1 << 14) -#define I2C_STAT_SLAVE_SEARCHING (1 << 13) -#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) -#define I2C_STAT_BUS_BUSY (1 << 11) -#define I2C_STAT_CLK_GEN_BUSY (1 << 10) -#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) -#define I2C_STAT_SLAVE_BUSY (1 << 8) -#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) -#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) -#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) -#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) -#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) -#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) -#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) -#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) - -#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) -#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 -#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) -#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 -#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) -#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) -#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) -#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) -#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) -#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) - -#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) -#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 -#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) -#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) -#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f -#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 - -#define I2C_QUEUECMD_PREACK (1 << 27) -#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) -#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) -#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) -#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) -#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) -#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) -#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) -#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_QUEUECMD_MASTER_MODE (1 << 17) -#define I2C_QUEUECMD_DIRECTION (1 << 16) -#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff -#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 - -#define I2C_QUEUEDATA_DATA_MASK 0xffffffff -#define I2C_QUEUEDATA_DATA_OFFSET 0 - -#define I2C_DATA_DATA_MASK 0xffffffff -#define I2C_DATA_DATA_OFFSET 0 - -#define I2C_DEBUG0_DMAREQ (1 << 31) -#define I2C_DEBUG0_DMAENDCMD (1 << 30) -#define I2C_DEBUG0_DMAKICK (1 << 29) -#define I2C_DEBUG0_DMATERMINATE (1 << 28) -#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) -#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 -#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) -#define I2C_DEBUG0_DMA_STATE_OFFSET 16 -#define I2C_DEBUG0_START_TOGGLE (1 << 15) -#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) -#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) -#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) -#define I2C_DEBUG0_STATE_LATCH (1 << 11) -#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) -#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff -#define I2C_DEBUG0_STATE_STATE_OFFSET 0 - -#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) -#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 -#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) -#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 -#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) -#define I2C_DEBUG1_LST_MODE_OFFSET 9 -#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) -#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) -#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) -#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) -#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) -#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) - -#define I2C_VERSION_MAJOR_MASK (0xff << 24) -#define I2C_VERSION_MAJOR_OFFSET 24 -#define I2C_VERSION_MINOR_MASK (0xff << 16) -#define I2C_VERSION_MINOR_OFFSET 16 -#define I2C_VERSION_STEP_MASK 0xffff -#define I2C_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h deleted file mode 100644 index 2738035..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-ocotp.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Freescale i.MX28 OCOTP Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_OCOTP_H__ -#define __MX28_REGS_OCOTP_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_ocotp_regs { - mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mx28_reg_32(hw_ocotp_data) /* 0x10 */ - mx28_reg_32(hw_ocotp_cust0) /* 0x20 */ - mx28_reg_32(hw_ocotp_cust1) /* 0x30 */ - mx28_reg_32(hw_ocotp_cust2) /* 0x40 */ - mx28_reg_32(hw_ocotp_cust3) /* 0x50 */ - mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mx28_reg_32(hw_ocotp_swcap) /* 0x100 */ - mx28_reg_32(hw_ocotp_custcap) /* 0x110 */ - mx28_reg_32(hw_ocotp_lock) /* 0x120 */ - mx28_reg_32(hw_ocotp_ops0) /* 0x130 */ - mx28_reg_32(hw_ocotp_ops1) /* 0x140 */ - mx28_reg_32(hw_ocotp_ops2) /* 0x150 */ - mx28_reg_32(hw_ocotp_ops3) /* 0x160 */ - mx28_reg_32(hw_ocotp_un0) /* 0x170 */ - mx28_reg_32(hw_ocotp_un1) /* 0x180 */ - mx28_reg_32(hw_ocotp_un2) /* 0x190 */ - mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mx28_reg_32(hw_ocotp_rom6) /* 0x200 */ - mx28_reg_32(hw_ocotp_rom7) /* 0x210 */ - mx28_reg_32(hw_ocotp_srk0) /* 0x220 */ - mx28_reg_32(hw_ocotp_srk1) /* 0x230 */ - mx28_reg_32(hw_ocotp_srk2) /* 0x240 */ - mx28_reg_32(hw_ocotp_srk3) /* 0x250 */ - mx28_reg_32(hw_ocotp_srk4) /* 0x260 */ - mx28_reg_32(hw_ocotp_srk5) /* 0x270 */ - mx28_reg_32(hw_ocotp_srk6) /* 0x280 */ - mx28_reg_32(hw_ocotp_srk7) /* 0x290 */ - mx28_reg_32(hw_ocotp_version) /* 0x2a0 */ -}; -#endif - -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) -#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 -#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) -#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -#define OCOTP_CTRL_ERROR (1 << 9) -#define OCOTP_CTRL_BUSY (1 << 8) -#define OCOTP_CTRL_ADDR_MASK 0x3f -#define OCOTP_CTRL_ADDR_OFFSET 0 - -#define OCOTP_DATA_DATA_MASK 0xffffffff -#define OCOTP_DATA_DATA_OFFSET 0 - -#define OCOTP_CUST_BITS_MASK 0xffffffff -#define OCOTP_CUST_BITS_OFFSET 0 - -#define OCOTP_CRYPTO_BITS_MASK 0xffffffff -#define OCOTP_CRYPTO_BITS_OFFSET 0 - -#define OCOTP_HWCAP_BITS_MASK 0xffffffff -#define OCOTP_HWCAP_BITS_OFFSET 0 - -#define OCOTP_SWCAP_BITS_MASK 0xffffffff -#define OCOTP_SWCAP_BITS_OFFSET 0 - -#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) -#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) - -#define OCOTP_LOCK_ROM7 (1 << 31) -#define OCOTP_LOCK_ROM6 (1 << 30) -#define OCOTP_LOCK_ROM5 (1 << 29) -#define OCOTP_LOCK_ROM4 (1 << 28) -#define OCOTP_LOCK_ROM3 (1 << 27) -#define OCOTP_LOCK_ROM2 (1 << 26) -#define OCOTP_LOCK_ROM1 (1 << 25) -#define OCOTP_LOCK_ROM0 (1 << 24) -#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) -#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) -#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) -#define OCOTP_LOCK_PIN (1 << 20) -#define OCOTP_LOCK_OPS (1 << 19) -#define OCOTP_LOCK_UN2 (1 << 18) -#define OCOTP_LOCK_UN1 (1 << 17) -#define OCOTP_LOCK_UN0 (1 << 16) -#define OCOTP_LOCK_SRK (1 << 15) -#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) -#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 -#define OCOTP_LOCK_SRK_SHADOW (1 << 11) -#define OCOTP_LOCK_ROM_SHADOW (1 << 10) -#define OCOTP_LOCK_CUSTCAP (1 << 9) -#define OCOTP_LOCK_HWSW (1 << 8) -#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) -#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) -#define OCOTP_LOCK_CRYPTODCP (1 << 5) -#define OCOTP_LOCK_CRYPTOKEY (1 << 4) -#define OCOTP_LOCK_CUST3 (1 << 3) -#define OCOTP_LOCK_CUST2 (1 << 2) -#define OCOTP_LOCK_CUST1 (1 << 1) -#define OCOTP_LOCK_CUST0 (1 << 0) - -#define OCOTP_OPS_BITS_MASK 0xffffffff -#define OCOTP_OPS_BITS_OFFSET 0 - -#define OCOTP_UN_BITS_MASK 0xffffffff -#define OCOTP_UN_BITS_OFFSET 0 - -#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) -#define OCOTP_ROM_BOOT_MODE_OFFSET 24 -#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) -#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 -#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) -#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 -#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) -#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 -#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) -#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 -#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) -#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 -#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) -#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) -#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) -#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) -#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) - -#define OCOTP_SRK_BITS_MASK 0xffffffff -#define OCOTP_SRK_BITS_OFFSET 0 - -#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) -#define OCOTP_VERSION_MAJOR_OFFSET 24 -#define OCOTP_VERSION_MINOR_MASK (0xff << 16) -#define OCOTP_VERSION_MINOR_OFFSET 16 -#define OCOTP_VERSION_STEP_MASK 0xffff -#define OCOTP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h deleted file mode 100644 index 80dcdf6..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h +++ /dev/null @@ -1,1284 +0,0 @@ -/* - * Freescale i.MX28 PINCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_PINCTRL_H__ -#define __MX28_REGS_PINCTRL_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_pinctrl_regs { - mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */ - - uint32_t reserved1[60]; - - mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ - - uint32_t reserved2[72]; - - mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */ - - uint32_t reserved3[112]; - - mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */ - - uint32_t reserved4[36]; - - mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */ - - uint32_t reserved5[108]; - - mx28_reg_32(hw_pinctrl_din0) /* 0x900 */ - mx28_reg_32(hw_pinctrl_din1) /* 0x910 */ - mx28_reg_32(hw_pinctrl_din2) /* 0x920 */ - mx28_reg_32(hw_pinctrl_din3) /* 0x930 */ - mx28_reg_32(hw_pinctrl_din4) /* 0x940 */ - - uint32_t reserved6[108]; - - mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */ - - uint32_t reserved7[300]; - - mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ - - uint32_t reserved8[44]; - - mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ - - uint32_t reserved9[44]; - - mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ - - uint32_t reserved10[44]; - - mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ - - uint32_t reserved11[44]; - - mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ - - uint32_t reserved12[380]; - - mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ - - uint32_t reserved13[76]; - - mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ -}; -#endif - -#define PINCTRL_CTRL_SFTRST (1 << 31) -#define PINCTRL_CTRL_CLKGATE (1 << 30) -#define PINCTRL_CTRL_PRESENT4 (1 << 24) -#define PINCTRL_CTRL_PRESENT3 (1 << 23) -#define PINCTRL_CTRL_PRESENT2 (1 << 22) -#define PINCTRL_CTRL_PRESENT1 (1 << 21) -#define PINCTRL_CTRL_PRESENT0 (1 << 20) -#define PINCTRL_CTRL_IRQOUT4 (1 << 4) -#define PINCTRL_CTRL_IRQOUT3 (1 << 3) -#define PINCTRL_CTRL_IRQOUT2 (1 << 2) -#define PINCTRL_CTRL_IRQOUT1 (1 << 1) -#define PINCTRL_CTRL_IRQOUT0 (1 << 0) - -#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) -#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 -#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 - -#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 -#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 - -#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) -#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) -#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) -#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) -#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) -#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) -#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) -#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) -#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) -#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) -#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) -#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) -#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) -#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) -#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) -#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) -#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) -#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) -#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) -#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) -#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) - -#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) -#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) -#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) -#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) -#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) -#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) -#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) -#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) -#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) -#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) -#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) -#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) -#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) -#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) -#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) -#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) -#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) -#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) -#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) -#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) -#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) -#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) -#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) -#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) -#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) -#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) -#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) -#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) -#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) -#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) -#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) -#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) - -#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) -#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) -#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) -#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) -#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) -#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) -#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) -#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) -#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) -#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) -#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) -#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) -#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) -#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) -#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) -#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) -#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) -#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) -#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) -#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) -#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) -#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) -#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) -#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) -#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) - -#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) -#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) -#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) -#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) -#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) -#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) -#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) -#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) -#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) -#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) -#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) -#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) -#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) -#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) -#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) -#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) -#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) -#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) -#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) -#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) -#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) -#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) -#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) -#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) -#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) -#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) -#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) -#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) -#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) -#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) - -#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) -#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) -#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) -#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) -#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) -#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) -#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) -#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) -#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) -#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) -#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) -#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) -#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) -#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) -#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) -#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) -#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) -#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) - -#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) -#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) -#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) -#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) -#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) -#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) -#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) -#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) -#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) -#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) -#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) -#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) -#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) -#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) -#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) -#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) -#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) -#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) -#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) -#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) -#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) -#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) -#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) -#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) -#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) - -#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) -#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) -#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) -#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) -#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) -#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) -#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) -#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) -#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) -#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) -#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) -#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) -#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) -#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) -#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) -#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) -#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) -#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) -#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) -#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) -#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) -#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) -#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) -#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) - -#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff -#define PINCTRL_DOUT0_DOUT_OFFSET 0 - -#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff -#define PINCTRL_DOUT1_DOUT_OFFSET 0 - -#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff -#define PINCTRL_DOUT2_DOUT_OFFSET 0 - -#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff -#define PINCTRL_DOUT3_DOUT_OFFSET 0 - -#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff -#define PINCTRL_DOUT4_DOUT_OFFSET 0 - -#define PINCTRL_DIN0_DIN_MASK 0x1fffffff -#define PINCTRL_DIN0_DIN_OFFSET 0 - -#define PINCTRL_DIN1_DIN_MASK 0xffffffff -#define PINCTRL_DIN1_DIN_OFFSET 0 - -#define PINCTRL_DIN2_DIN_MASK 0xfffffff -#define PINCTRL_DIN2_DIN_OFFSET 0 - -#define PINCTRL_DIN3_DIN_MASK 0x7fffffff -#define PINCTRL_DIN3_DIN_OFFSET 0 - -#define PINCTRL_DIN4_DIN_MASK 0x1fffff -#define PINCTRL_DIN4_DIN_OFFSET 0 - -#define PINCTRL_DOE0_DOE_MASK 0x1fffffff -#define PINCTRL_DOE0_DOE_OFFSET 0 - -#define PINCTRL_DOE1_DOE_MASK 0xffffffff -#define PINCTRL_DOE1_DOE_OFFSET 0 - -#define PINCTRL_DOE2_DOE_MASK 0xfffffff -#define PINCTRL_DOE2_DOE_OFFSET 0 - -#define PINCTRL_DOE3_DOE_MASK 0x7fffffff -#define PINCTRL_DOE3_DOE_OFFSET 0 - -#define PINCTRL_DOE4_DOE_MASK 0x1fffff -#define PINCTRL_DOE4_DOE_OFFSET 0 - -#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff -#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff -#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff -#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff -#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff -#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 - -#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff -#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff -#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff -#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff -#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff -#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 - -#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff -#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff -#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff -#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff -#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff -#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff -#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff -#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff -#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff -#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff -#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff -#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff -#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff -#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff -#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff -#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 - -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 - -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 - -#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h deleted file mode 100644 index 8eadc6d..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-power.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Freescale i.MX28 Power Controller Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_POWER_H__ -#define __MX28_REGS_POWER_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_power_regs { - mx28_reg_32(hw_power_ctrl) - mx28_reg_32(hw_power_5vctrl) - mx28_reg_32(hw_power_minpwr) - mx28_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mx28_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mx28_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved[4]; - - mx28_reg_32(hw_power_reset) - mx28_reg_32(hw_power_debug) - mx28_reg_32(hw_power_thermal) - mx28_reg_32(hw_power_usb1ctrl) - mx28_reg_32(hw_power_special) - mx28_reg_32(hw_power_version) - mx28_reg_32(hw_power_anaclkctrl) - mx28_reg_32(hw_power_refctrl) -}; -#endif - -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_FBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_LIION_4P1 (1 << 18) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) -#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) -#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_THERMAL_WARNING (1 << 19) -#define POWER_STS_VDDMEM_BO (1 << 18) -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xffff << 8) -#define POWER_SPEED_STATUS_OFFSET 8 -#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) -#define POWER_SPEED_STATUS_SEL_OFFSET 6 -#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) -#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) -#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_THERMAL_TEST (1 << 8) -#define POWER_THERMAL_PWD (1 << 7) -#define POWER_THERMAL_LOW_POWER (1 << 6) -#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) -#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 -#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) -#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 -#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 - -#define POWER_USB1CTRL_AVALID1 (1 << 3) -#define POWER_USB1CTRL_BVALID1 (1 << 2) -#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) -#define POWER_USB1CTRL_SESSEND1 (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) -#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) -#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 -#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) -#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) -#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) -#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) -#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) -#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) -#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 -#define POWER_ANACLKCTRL_INDIV_MASK 0x7 -#define POWER_ANACLKCTRL_INDIV_OFFSET 0 - -#define POWER_REFCTRL_FASTSETTLING (1 << 26) -#define POWER_REFCTRL_RAISE_REF (1 << 25) -#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) -#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) -#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 -#define POWER_REFCTRL_LOW_PWR (1 << 19) -#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) -#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 -#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) -#define POWER_REFCTRL_ADJ_ANA (1 << 13) -#define POWER_REFCTRL_ADJ_VAG (1 << 12) -#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) -#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 -#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) -#define POWER_REFCTRL_VAG_VAL_OFFSET 4 - -#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h deleted file mode 100644 index e605a03..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-rtc.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale i.MX28 RTC Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_RTC_H__ -#define __MX28_REGS_RTC_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_rtc_regs { - mx28_reg_32(hw_rtc_ctrl) - mx28_reg_32(hw_rtc_stat) - mx28_reg_32(hw_rtc_milliseconds) - mx28_reg_32(hw_rtc_seconds) - mx28_reg_32(hw_rtc_rtc_alarm) - mx28_reg_32(hw_rtc_watchdog) - mx28_reg_32(hw_rtc_persistent0) - mx28_reg_32(hw_rtc_persistent1) - mx28_reg_32(hw_rtc_persistent2) - mx28_reg_32(hw_rtc_persistent3) - mx28_reg_32(hw_rtc_persistent4) - mx28_reg_32(hw_rtc_persistent5) - mx28_reg_32(hw_rtc_debug) - mx28_reg_32(hw_rtc_version) -}; -#endif - -#define RTC_CTRL_SFTRST (1 << 31) -#define RTC_CTRL_CLKGATE (1 << 30) -#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) -#define RTC_CTRL_FORCE_UPDATE (1 << 5) -#define RTC_CTRL_WATCHDOGEN (1 << 4) -#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) -#define RTC_CTRL_ALARM_IRQ (1 << 2) -#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) -#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) - -#define RTC_STAT_RTC_PRESENT (1 << 31) -#define RTC_STAT_ALARM_PRESENT (1 << 30) -#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) -#define RTC_STAT_XTAL32000_PRESENT (1 << 28) -#define RTC_STAT_XTAL32768_PRESENT (1 << 27) -#define RTC_STAT_STALE_REGS_MASK (0xff << 16) -#define RTC_STAT_STALE_REGS_OFFSET 16 -#define RTC_STAT_NEW_REGS_MASK (0xff << 8) -#define RTC_STAT_NEW_REGS_OFFSET 8 - -#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff -#define RTC_MILLISECONDS_COUNT_OFFSET 0 - -#define RTC_SECONDS_COUNT_MASK 0xffffffff -#define RTC_SECONDS_COUNT_OFFSET 0 - -#define RTC_ALARM_VALUE_MASK 0xffffffff -#define RTC_ALARM_VALUE_OFFSET 0 - -#define RTC_WATCHDOG_COUNT_MASK 0xffffffff -#define RTC_WATCHDOG_COUNT_OFFSET 0 - -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) -#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) -#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) -#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) -#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) -#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) -#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) -#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 -#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) -#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) -#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) -#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 -#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) -#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) -#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) -#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) -#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) -#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) -#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) -#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) -#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) -#define RTC_PERSISTENT0_LCK_SECS (1 << 3) -#define RTC_PERSISTENT0_ALARM_EN (1 << 2) -#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) -#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) - -#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT1_GENERAL_OFFSET 0 -#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 -#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 -#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 -#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 -#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 -#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 - -#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT2_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT3_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT4_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT5_GENERAL_OFFSET 0 - -#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) -#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) - -#define RTC_VERSION_MAJOR_MASK (0xff << 24) -#define RTC_VERSION_MAJOR_OFFSET 24 -#define RTC_VERSION_MINOR_MASK (0xff << 16) -#define RTC_VERSION_MINOR_OFFSET 16 -#define RTC_VERSION_STEP_MASK 0xffff -#define RTC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h deleted file mode 100644 index be71d48..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-ssp.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Freescale i.MX28 SSP Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_SSP_H__ -#define __MX28_REGS_SSP_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_ssp_regs { - mx28_reg_32(hw_ssp_ctrl0) - mx28_reg_32(hw_ssp_cmd0) - mx28_reg_32(hw_ssp_cmd1) - mx28_reg_32(hw_ssp_xfer_size) - mx28_reg_32(hw_ssp_block_size) - mx28_reg_32(hw_ssp_compref) - mx28_reg_32(hw_ssp_compmask) - mx28_reg_32(hw_ssp_timing) - mx28_reg_32(hw_ssp_ctrl1) - mx28_reg_32(hw_ssp_data) - mx28_reg_32(hw_ssp_sdresp0) - mx28_reg_32(hw_ssp_sdresp1) - mx28_reg_32(hw_ssp_sdresp2) - mx28_reg_32(hw_ssp_sdresp3) - mx28_reg_32(hw_ssp_ddr_ctrl) - mx28_reg_32(hw_ssp_dll_ctrl) - mx28_reg_32(hw_ssp_status) - mx28_reg_32(hw_ssp_dll_sts) - mx28_reg_32(hw_ssp_debug) - mx28_reg_32(hw_ssp_version) -}; -#endif - -#define SSP_CTRL0_SFTRST (1 << 31) -#define SSP_CTRL0_CLKGATE (1 << 30) -#define SSP_CTRL0_RUN (1 << 29) -#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) -#define SSP_CTRL0_LOCK_CS (1 << 27) -#define SSP_CTRL0_IGNORE_CRC (1 << 26) -#define SSP_CTRL0_READ (1 << 25) -#define SSP_CTRL0_DATA_XFER (1 << 24) -#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) -#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 -#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) -#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) -#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) -#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) -#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) -#define SSP_CTRL0_LONG_RESP (1 << 19) -#define SSP_CTRL0_CHECK_RESP (1 << 18) -#define SSP_CTRL0_GET_RESP (1 << 17) -#define SSP_CTRL0_ENABLE (1 << 16) - -#define SSP_CMD0_SOFT_TERMINATE (1 << 26) -#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) -#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) -#define SSP_CMD0_BOOT_ACK_EN (1 << 23) -#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) -#define SSP_CMD0_CONT_CLKING_EN (1 << 21) -#define SSP_CMD0_APPEND_8CYC (1 << 20) -#define SSP_CMD0_CMD_MASK 0xff -#define SSP_CMD0_CMD_OFFSET 0 -#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 -#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 -#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 -#define SSP_CMD0_CMD_MMC_SWITCH 0x06 -#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 -#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 -#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a -#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b -#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e -#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 -#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 -#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 -#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a -#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_MMC_ERASE 0x26 -#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 -#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 -#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 -#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 -#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_SD_SET_DSR 0x04 -#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 -#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 -#define SSP_CMD0_CMD_SD_SEND_CID 0x0a -#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_SD_ERASE 0x26 -#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 -#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 -#define SSP_CMD0_CMD_SD_APP_CMD 0x37 -#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 - -#define SSP_CMD1_CMD_ARG_MASK 0xffffffff -#define SSP_CMD1_CMD_ARG_OFFSET 0 - -#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff -#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 - -#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) -#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 -#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf -#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 - -#define SSP_COMPREF_REFERENCE_MASK 0xffffffff -#define SSP_COMPREF_REFERENCE_OFFSET 0 - -#define SSP_COMPMASK_MASK_MASK 0xffffffff -#define SSP_COMPMASK_MASK_OFFSET 0 - -#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) -#define SSP_TIMING_TIMEOUT_OFFSET 16 -#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) -#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 -#define SSP_TIMING_CLOCK_RATE_MASK 0xff -#define SSP_TIMING_CLOCK_RATE_OFFSET 0 - -#define SSP_CTRL1_SDIO_IRQ (1 << 31) -#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) -#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) -#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) -#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) -#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) -#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) -#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) -#define SSP_CTRL1_DMA_ENABLE (1 << 13) -#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) -#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) -#define SSP_CTRL1_PHASE (1 << 10) -#define SSP_CTRL1_POLARITY (1 << 9) -#define SSP_CTRL1_SLAVE_MODE (1 << 8) -#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) -#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 -#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) -#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) -#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) -#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) -#define SSP_CTRL1_SSP_MODE_MASK 0xf -#define SSP_CTRL1_SSP_MODE_OFFSET 0 -#define SSP_CTRL1_SSP_MODE_SPI 0x0 -#define SSP_CTRL1_SSP_MODE_SSI 0x1 -#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 -#define SSP_CTRL1_SSP_MODE_MS 0x4 - -#define SSP_DATA_DATA_MASK 0xffffffff -#define SSP_DATA_DATA_OFFSET 0 - -#define SSP_SDRESP0_RESP0_MASK 0xffffffff -#define SSP_SDRESP0_RESP0_OFFSET 0 - -#define SSP_SDRESP1_RESP1_MASK 0xffffffff -#define SSP_SDRESP1_RESP1_OFFSET 0 - -#define SSP_SDRESP2_RESP2_MASK 0xffffffff -#define SSP_SDRESP2_RESP2_OFFSET 0 - -#define SSP_SDRESP3_RESP3_MASK 0xffffffff -#define SSP_SDRESP3_RESP3_OFFSET 0 - -#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) -#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 -#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) -#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) - -#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) -#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 -#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) -#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 -#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) -#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 -#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) -#define SSP_DLL_CTRL_RESET (1 << 1) -#define SSP_DLL_CTRL_ENABLE (1 << 0) - -#define SSP_STATUS_PRESENT (1 << 31) -#define SSP_STATUS_MS_PRESENT (1 << 30) -#define SSP_STATUS_SD_PRESENT (1 << 29) -#define SSP_STATUS_CARD_DETECT (1 << 28) -#define SSP_STATUS_DMABURST (1 << 22) -#define SSP_STATUS_DMASENSE (1 << 21) -#define SSP_STATUS_DMATERM (1 << 20) -#define SSP_STATUS_DMAREQ (1 << 19) -#define SSP_STATUS_DMAEND (1 << 18) -#define SSP_STATUS_SDIO_IRQ (1 << 17) -#define SSP_STATUS_RESP_CRC_ERR (1 << 16) -#define SSP_STATUS_RESP_ERR (1 << 15) -#define SSP_STATUS_RESP_TIMEOUT (1 << 14) -#define SSP_STATUS_DATA_CRC_ERR (1 << 13) -#define SSP_STATUS_TIMEOUT (1 << 12) -#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) -#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) -#define SSP_STATUS_FIFO_OVRFLW (1 << 9) -#define SSP_STATUS_FIFO_FULL (1 << 8) -#define SSP_STATUS_FIFO_EMPTY (1 << 5) -#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) -#define SSP_STATUS_CMD_BUSY (1 << 3) -#define SSP_STATUS_DATA_BUSY (1 << 2) -#define SSP_STATUS_BUSY (1 << 0) - -#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) -#define SSP_DLL_STS_REF_SEL_OFFSET 8 -#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) -#define SSP_DLL_STS_SLV_SEL_OFFSET 2 -#define SSP_DLL_STS_REF_LOCK (1 << 1) -#define SSP_DLL_STS_SLV_LOCK (1 << 0) - -#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) -#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 -#define SSP_DEBUG_DATA_STALL (1 << 27) -#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) -#define SSP_DEBUG_DAT_SM_OFFSET 24 -#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) -#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) -#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) -#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) -#define SSP_DEBUG_MSTK_SM_OFFSET 20 -#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) -#define SSP_DEBUG_CMD_OE (1 << 19) -#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) -#define SSP_DEBUG_DMA_SM_OFFSET 16 -#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) -#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) -#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) -#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) -#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) -#define SSP_DEBUG_MMC_SM_OFFSET 12 -#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) -#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) -#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) -#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) -#define SSP_DEBUG_CMD_SM_OFFSET 10 -#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) -#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) -#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) -#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) -#define SSP_DEBUG_SSP_CMD (1 << 9) -#define SSP_DEBUG_SSP_RESP (1 << 8) -#define SSP_DEBUG_SSP_RXD_MASK 0xff -#define SSP_DEBUG_SSP_RXD_OFFSET 0 - -#define SSP_VERSION_MAJOR_MASK (0xff << 24) -#define SSP_VERSION_MAJOR_OFFSET 24 -#define SSP_VERSION_MINOR_MASK (0xff << 16) -#define SSP_VERSION_MINOR_OFFSET 16 -#define SSP_VERSION_STEP_MASK 0xffff -#define SSP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h deleted file mode 100644 index 3e8dfe7..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-timrot.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Freescale i.MX28 TIMROT Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_TIMROT_H__ -#define __MX28_REGS_TIMROT_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_timrot_regs { - mx28_reg_32(hw_timrot_rotctrl) - mx28_reg_32(hw_timrot_rotcount) - mx28_reg_32(hw_timrot_timctrl0) - mx28_reg_32(hw_timrot_running_count0) - mx28_reg_32(hw_timrot_fixed_count0) - mx28_reg_32(hw_timrot_match_count0) - mx28_reg_32(hw_timrot_timctrl1) - mx28_reg_32(hw_timrot_running_count1) - mx28_reg_32(hw_timrot_fixed_count1) - mx28_reg_32(hw_timrot_match_count1) - mx28_reg_32(hw_timrot_timctrl2) - mx28_reg_32(hw_timrot_running_count2) - mx28_reg_32(hw_timrot_fixed_count2) - mx28_reg_32(hw_timrot_match_count2) - mx28_reg_32(hw_timrot_timctrl3) - mx28_reg_32(hw_timrot_running_count3) - mx28_reg_32(hw_timrot_fixed_count3) - mx28_reg_32(hw_timrot_match_count3) - mx28_reg_32(hw_timrot_version) -}; -#endif - -#define TIMROT_ROTCTRL_SFTRST (1 << 31) -#define TIMROT_ROTCTRL_CLKGATE (1 << 30) -#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) -#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) -#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) -#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) -#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) -#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) -#define TIMROT_ROTCTRL_STATE_OFFSET 22 -#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) -#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 -#define TIMROT_ROTCTRL_RELATIVE (1 << 12) -#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 -#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) -#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) -#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) -#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 -#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf -#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 -#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 -#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 -#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 -#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 -#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 -#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 -#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 -#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa - -#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff -#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 - -#define TIMROT_TIMCTRLn_IRQ (1 << 15) -#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) -#define TIMROT_TIMCTRLn_POLARITY (1 << 8) -#define TIMROT_TIMCTRLn_UPDATE (1 << 7) -#define TIMROT_TIMCTRLn_RELOAD (1 << 6) -#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRLn_SELECT_MASK 0xf -#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 -#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 -#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 -#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf - -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 - -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 - -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 - -#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 -#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) -#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) - -#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) -#define TIMROT_VERSION_MAJOR_OFFSET 24 -#define TIMROT_VERSION_MINOR_MASK (0xff << 16) -#define TIMROT_VERSION_MINOR_OFFSET 16 -#define TIMROT_VERSION_STEP_MASK 0xffff -#define TIMROT_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usb.h b/arch/arm/include/asm/arch-mx28/regs-usb.h deleted file mode 100644 index ea61de8..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-usb.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Freescale i.MX28 USB OTG Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct mx28_usb_regs { - uint32_t hw_usbctrl_id; /* 0x000 */ - uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ - uint32_t hw_usbctrl_hwhost; /* 0x008 */ - uint32_t hw_usbctrl_hwdevice; /* 0x00c */ - uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ - uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ - - uint32_t reserved1[26]; - - uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ - uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ - uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ - uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ - uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ - - uint32_t reserved2[27]; - - uint32_t hw_usbctrl_caplength; /* 0x100 */ - uint32_t hw_usbctrl_hcsparams; /* 0x104 */ - uint32_t hw_usbctrl_hccparams; /* 0x108 */ - - uint32_t reserved3[5]; - - uint32_t hw_usbctrl_dciversion; /* 0x120 */ - uint32_t hw_usbctrl_dccparams; /* 0x124 */ - - uint32_t reserved4[6]; - - uint32_t hw_usbctrl_usbcmd; /* 0x140 */ - uint32_t hw_usbctrl_usbsts; /* 0x144 */ - uint32_t hw_usbctrl_usbintr; /* 0x148 */ - uint32_t hw_usbctrl_frindex; /* 0x14c */ - - uint32_t reserved5; - - union { - uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ - uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ - }; - union { - uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ - uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ - }; - - uint32_t hw_usbctrl_ttctrl; /* 0x15c */ - uint32_t hw_usbctrl_burstsize; /* 0x160 */ - uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ - - uint32_t reserved6; - - uint32_t hw_usbctrl_ic_usb; /* 0x16c */ - uint32_t hw_usbctrl_ulpi; /* 0x170 */ - - uint32_t reserved7; - - uint32_t hw_usbctrl_endptnak; /* 0x178 */ - uint32_t hw_usbctrl_endptnaken; /* 0x17c */ - - uint32_t reserved8; - - uint32_t hw_usbctrl_portsc1; /* 0x184 */ - - uint32_t reserved9[7]; - - uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ - uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ - uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ - uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ - uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ - uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ - uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ - uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ - uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ - uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ - uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ - uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ - uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ - uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ - uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ -}; - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) - -#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 -#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) -#define HW_USBCTRL_ID_VERSION_OFFSET 25 -#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) -#define HW_USBCTRL_ID_REVISION_OFFSET 21 -#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) -#define HW_USBCTRL_ID_TAG_OFFSET 16 -#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) -#define HW_USBCTRL_ID_NID_OFFSET 8 -#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) -#define HW_USBCTRL_ID_ID_OFFSET 0 -#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) - -#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 -#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) -#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 -#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) -#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 -#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) -#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) -#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 -#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) -#define HW_USBCTRL_HWGENERAL_RT (1 << 0) - -#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 -#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) -#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 -#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) -#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 -#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) -#define HW_USBCTRL_HWHOST_HC (1 << 0) - -#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 -#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) -#define HW_USBCTRL_HWDEVICE_DC (1 << 0) - -#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) -#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 -#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) -#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 -#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 -#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff - -#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 -#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 -#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff - -#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 -#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff - -#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) -#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) -#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff - -#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h deleted file mode 100644 index 0291d81..0000000 --- a/arch/arm/include/asm/arch-mx28/regs-usbphy.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale i.MX28 USB PHY Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __REGS_USBPHY_H__ -#define __REGS_USBPHY_H__ - -struct mx28_usbphy_regs { - mx28_reg_32(hw_usbphy_pwd) - mx28_reg_32(hw_usbphy_tx) - mx28_reg_32(hw_usbphy_rx) - mx28_reg_32(hw_usbphy_ctrl) - mx28_reg_32(hw_usbphy_status) - mx28_reg_32(hw_usbphy_debug) - mx28_reg_32(hw_usbphy_debug0_status) - mx28_reg_32(hw_usbphy_debug1) - mx28_reg_32(hw_usbphy_version) - mx28_reg_32(hw_usbphy_ip) -}; - -#define USBPHY_PWD_RXPWDRX (1 << 20) -#define USBPHY_PWD_RXPWDDIFF (1 << 19) -#define USBPHY_PWD_RXPWD1PT1 (1 << 18) -#define USBPHY_PWD_RXPWDENV (1 << 17) -#define USBPHY_PWD_TXPWDV2I (1 << 12) -#define USBPHY_PWD_TXPWDIBIAS (1 << 11) -#define USBPHY_PWD_TXPWDFS (1 << 10) - -#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) -#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) -#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) -#define USBPHY_TX_TXENCAL45DP (1 << 21) -#define USBPHY_TX_TXCAL45DP_OFFSET 16 -#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) -#define USBPHY_TX_TXENCAL45DM (1 << 13) -#define USBPHY_TX_TXCAL45DM_OFFSET 8 -#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) -#define USBPHY_TX_D_CAL_OFFSET 0 -#define USBPHY_TX_D_CAL_MASK 0xf - -#define USBPHY_RX_RXDBYPASS (1 << 22) -#define USBPHY_RX_DISCONADJ_OFFSET 4 -#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) -#define USBPHY_RX_ENVADJ_OFFSET 0 -#define USBPHY_RX_ENVADJ_MASK 0x7 - -#define USBPHY_CTRL_SFTRST (1 << 31) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) -#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) -#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) -#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) -#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) -#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) -#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) -#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) -#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) -#define USBPHY_CTRL_RESUME_IRQ (1 << 10) -#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) -#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) -#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) -#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) -#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) -#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) - -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) - -#define USBPHY_DEBUG_CLKGATE (1 << 30) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) -#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) -#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) -#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 -#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) -#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) -#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 -#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) -#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) - -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff - -#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) -#define USBPHY_DEBUG1_ENTX2TX (1 << 12) -#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 -#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf - -#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) -#define USBPHY_VERSION_MAJOR_OFFSET 24 -#define USBPHY_VERSION_MINOR_MASK (0xff << 16) -#define USBPHY_VERSION_MINOR_OFFSET 16 -#define USBPHY_VERSION_STEP_MASK 0xffff -#define USBPHY_VERSION_STEP_OFFSET 0 - -#define USBPHY_IP_DIV_SEL_OFFSET 23 -#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) -#define USBPHY_IP_LFR_SEL_OFFSET 21 -#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) -#define USBPHY_IP_CP_SEL_OFFSET 19 -#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) -#define USBPHY_IP_TSTI_TX_DP (1 << 18) -#define USBPHY_IP_TSTI_TX_DM (1 << 17) -#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) -#define USBPHY_IP_EN_USB_CLKS (1 << 2) -#define USBPHY_IP_PLL_LOCKED (1 << 1) -#define USBPHY_IP_PLL_POWER (1 << 0) - -#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h deleted file mode 100644 index e701c64..0000000 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Freescale i.MX28 MX28 specific functions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_H__ -#define __MX28_H__ - -int mx28_reset_block(struct mx28_register_32 *reg); -int mx28_wait_mask_set(struct mx28_register_32 *reg, - uint32_t mask, - int timeout); -int mx28_wait_mask_clr(struct mx28_register_32 *reg, - uint32_t mask, - int timeout); - -int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); - -#ifdef CONFIG_SPL_BUILD -#include <asm/arch/iomux-mx28.h> -void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); -#endif - -struct mx28_pair { - uint8_t boot_pads; - uint8_t boot_mask; - const char *mode; -}; - -static const struct mx28_pair mx28_boot_modes[] = { - { 0x00, 0x0f, "USB #0" }, - { 0x01, 0x1f, "I2C #0, master, 3V3" }, - { 0x11, 0x1f, "I2C #0, master, 1V8" }, - { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, - { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, - { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, - { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, - { 0x04, 0x1f, "NAND, 3V3" }, - { 0x14, 0x1f, "NAND, 1V8" }, - { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, - { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, - { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, - { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, - { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -}; - -struct mx28_spl_data { - uint8_t boot_mode_idx; - uint32_t mem_dram_size; -}; - -int mx28_dram_init(void); - -#endif /* __MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h new file mode 100644 index 0000000..1700fe3 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/clock.h @@ -0,0 +1,61 @@ +/* + * Freescale i.MX28 Clock + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_EMI_CLK, + MXC_GPMI_CLK, + MXC_IO0_CLK, + MXC_IO1_CLK, + MXC_SSP0_CLK, + MXC_SSP1_CLK, + MXC_SSP2_CLK, + MXC_SSP3_CLK, +}; + +enum mxs_ioclock { + MXC_IOCLK0 = 0, + MXC_IOCLK1, +}; + +enum mxs_sspclock { + MXC_SSPCLK0 = 0, + MXC_SSPCLK1, + MXC_SSPCLK2, + MXC_SSPCLK3, +}; + +uint32_t mxc_get_clock(enum mxc_clock clk); + +void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq); +void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); +void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq); + +/* Compatibility with the FEC Ethernet driver */ +#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) + +#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/arch-mxs/dma.h new file mode 100644 index 0000000..4a1820b --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/dma.h @@ -0,0 +1,147 @@ +/* + * Freescale i.MX28 APBH DMA + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include <linux/list.h> + +#ifndef CONFIG_ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 32 + +/* + * MXS DMA channels + */ +enum { + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_MAX_DMA_CHANNELS, +}; + +/* + * MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +#define MXS_DMA_DESC_COMMAND_MASK 0x3 +#define MXS_DMA_DESC_COMMAND_OFFSET 0 +#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 +#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 +#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 +#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 +#define MXS_DMA_DESC_CHAIN (1 << 2) +#define MXS_DMA_DESC_IRQ (1 << 3) +#define MXS_DMA_DESC_NAND_LOCK (1 << 4) +#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) +#define MXS_DMA_DESC_DEC_SEM (1 << 6) +#define MXS_DMA_DESC_WAIT4END (1 << 7) +#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) +#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) +#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) +#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 +#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) +#define MXS_DMA_DESC_BYTES_OFFSET 16 + +struct mxs_dma_cmd { + unsigned long next; + unsigned long data; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/* + * MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + */ +#define MXS_DMA_DESC_FIRST (1 << 0) +#define MXS_DMA_DESC_LAST (1 << 1) +#define MXS_DMA_DESC_READY (1 << 31) + +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +/** + * MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + */ +#define MXS_DMA_FLAGS_IDLE 0 +#define MXS_DMA_FLAGS_BUSY (1 << 0) +#define MXS_DMA_FLAGS_FREE 0 +#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) +#define MXS_DMA_FLAGS_VALID (1 << 31) + +struct mxs_dma_chan { + const char *name; + unsigned long dev; + struct mxs_dma_device *dma; + unsigned int flags; + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +struct mxs_dma_desc *mxs_dma_desc_alloc(void); +void mxs_dma_desc_free(struct mxs_dma_desc *); +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +int mxs_dma_go(int chan); +void mxs_dma_init(void); +int mxs_dma_init_channel(int chan); +int mxs_dma_release(int chan); + +#endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/gpio.h b/arch/arm/include/asm/arch-mxs/gpio.h new file mode 100644 index 0000000..be1c944 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/gpio.h @@ -0,0 +1,32 @@ +/* + * Freescale i.MX28 GPIO + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_GPIO_H__ +#define __MX28_GPIO_H__ + +#ifdef CONFIG_MXS_GPIO +void mxs_gpio_init(void); +#else +inline void mxs_gpio_init(void) {} +#endif + +#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h new file mode 100644 index 0000000..37d0a93 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -0,0 +1,42 @@ +/* + * Freescale i.MX28 Registers + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __IMX_REGS_H__ +#define __IMX_REGS_H__ + +#include <asm/arch/regs-apbh.h> +#include <asm/arch/regs-base.h> +#include <asm/arch/regs-bch.h> +#include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-digctl.h> +#include <asm/arch/regs-gpmi.h> +#include <asm/arch/regs-i2c.h> +#include <asm/arch/regs-lcdif.h> +#include <asm/arch/regs-lradc.h> +#include <asm/arch/regs-ocotp.h> +#include <asm/arch/regs-pinctrl.h> +#include <asm/arch/regs-power.h> +#include <asm/arch/regs-rtc.h> +#include <asm/arch/regs-ssp.h> +#include <asm/arch/regs-timrot.h> + +#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/arch/arm/include/asm/arch-mxs/iomux-mx28.h new file mode 100644 index 0000000..b42820d --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/iomux-mx28.h @@ -0,0 +1,537 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria amit.kucheria@canonical.com + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX28_H__ +#define __MACH_IOMUX_MX28_H__ + +#include <asm/arch/iomux.h> + +/* + * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) + +#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) + +#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) + +#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) +#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) +#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) +#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) + +#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) + +#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) + +#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) +#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) +#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) +#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) +#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) + +#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) + +#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) +#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) +#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) + +#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) +#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) +#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) +#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) +#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) + +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) + +#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) + +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) + +#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) + +#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h new file mode 100644 index 0000000..7abdf58 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/iomux.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * armlinux@phytec.de + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_IOMUX_H__ +#define __MACH_MXS_IOMUX_H__ + +/* + * IOMUX/PAD Bit field definitions + * + * PAD_BANK: 0..2 (3) + * PAD_PIN: 3..7 (5) + * PAD_MUXSEL: 8..9 (2) + * PAD_MA: 10..11 (2) + * PAD_MA_VALID: 12 (1) + * PAD_VOL: 13 (1) + * PAD_VOL_VALID: 14 (1) + * PAD_PULL: 15 (1) + * PAD_PULL_VALID: 16 (1) + * RESERVED: 17..31 (15) + */ +typedef u32 iomux_cfg_t; + +#define MXS_PAD_BANK_SHIFT 0 +#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) +#define MXS_PAD_PIN_SHIFT 3 +#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) +#define MXS_PAD_MUXSEL_SHIFT 8 +#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) +#define MXS_PAD_MA_SHIFT 10 +#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) +#define MXS_PAD_MA_VALID_SHIFT 12 +#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) +#define MXS_PAD_VOL_SHIFT 13 +#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) +#define MXS_PAD_VOL_VALID_SHIFT 14 +#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) +#define MXS_PAD_PULL_SHIFT 15 +#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) +#define MXS_PAD_PULL_VALID_SHIFT 16 +#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) + +#define PAD_MUXSEL_0 0 +#define PAD_MUXSEL_1 1 +#define PAD_MUXSEL_2 2 +#define PAD_MUXSEL_GPIO 3 + +#define PAD_4MA 0 +#define PAD_8MA 1 +#define PAD_12MA 2 +#define PAD_16MA 3 + +#define PAD_1V8 0 +#define PAD_3V3 1 + +#define PAD_NOPULL 0 +#define PAD_PULLUP 1 + +#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) + +#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) +#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) + +#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) +#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) + +/* generic pad control used in most cases */ +#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) + +#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ + (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ + ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ + ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ + ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ + ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ + ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) + +/* + * A pad becomes naked, when none of mA, vol or pull + * validity bits is set. + */ +#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ + MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) + +static inline unsigned int PAD_BANK(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; +} + +static inline unsigned int PAD_PIN(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; +} + +static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; +} + +static inline unsigned int PAD_MA(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; +} + +static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; +} + +static inline unsigned int PAD_VOL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; +} + +static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; +} + +static inline unsigned int PAD_PULL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; +} + +static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; +} + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad); + +/* + * configures multiple pads + * convenient way to call the above function with tables + */ +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); + +#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mxs/regs-apbh.h b/arch/arm/include/asm/arch-mxs/regs-apbh.h new file mode 100644 index 0000000..91d7bc8 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-apbh.h @@ -0,0 +1,466 @@ +/* + * Freescale i.MX28 APBH Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_APBH_H__ +#define __REGS_APBH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_apbh_regs { + mx28_reg_32(hw_apbh_ctrl0) + mx28_reg_32(hw_apbh_ctrl1) + mx28_reg_32(hw_apbh_ctrl2) + mx28_reg_32(hw_apbh_channel_ctrl) + mx28_reg_32(hw_apbh_devsel) + mx28_reg_32(hw_apbh_dma_burst_size) + mx28_reg_32(hw_apbh_debug) + + uint32_t reserved[36]; + + union { + struct { + mx28_reg_32(hw_apbh_ch_curcmdar) + mx28_reg_32(hw_apbh_ch_nxtcmdar) + mx28_reg_32(hw_apbh_ch_cmd) + mx28_reg_32(hw_apbh_ch_bar) + mx28_reg_32(hw_apbh_ch_sema) + mx28_reg_32(hw_apbh_ch_debug1) + mx28_reg_32(hw_apbh_ch_debug2) + } ch[16]; + struct { + mx28_reg_32(hw_apbh_ch0_curcmdar) + mx28_reg_32(hw_apbh_ch0_nxtcmdar) + mx28_reg_32(hw_apbh_ch0_cmd) + mx28_reg_32(hw_apbh_ch0_bar) + mx28_reg_32(hw_apbh_ch0_sema) + mx28_reg_32(hw_apbh_ch0_debug1) + mx28_reg_32(hw_apbh_ch0_debug2) + mx28_reg_32(hw_apbh_ch1_curcmdar) + mx28_reg_32(hw_apbh_ch1_nxtcmdar) + mx28_reg_32(hw_apbh_ch1_cmd) + mx28_reg_32(hw_apbh_ch1_bar) + mx28_reg_32(hw_apbh_ch1_sema) + mx28_reg_32(hw_apbh_ch1_debug1) + mx28_reg_32(hw_apbh_ch1_debug2) + mx28_reg_32(hw_apbh_ch2_curcmdar) + mx28_reg_32(hw_apbh_ch2_nxtcmdar) + mx28_reg_32(hw_apbh_ch2_cmd) + mx28_reg_32(hw_apbh_ch2_bar) + mx28_reg_32(hw_apbh_ch2_sema) + mx28_reg_32(hw_apbh_ch2_debug1) + mx28_reg_32(hw_apbh_ch2_debug2) + mx28_reg_32(hw_apbh_ch3_curcmdar) + mx28_reg_32(hw_apbh_ch3_nxtcmdar) + mx28_reg_32(hw_apbh_ch3_cmd) + mx28_reg_32(hw_apbh_ch3_bar) + mx28_reg_32(hw_apbh_ch3_sema) + mx28_reg_32(hw_apbh_ch3_debug1) + mx28_reg_32(hw_apbh_ch3_debug2) + mx28_reg_32(hw_apbh_ch4_curcmdar) + mx28_reg_32(hw_apbh_ch4_nxtcmdar) + mx28_reg_32(hw_apbh_ch4_cmd) + mx28_reg_32(hw_apbh_ch4_bar) + mx28_reg_32(hw_apbh_ch4_sema) + mx28_reg_32(hw_apbh_ch4_debug1) + mx28_reg_32(hw_apbh_ch4_debug2) + mx28_reg_32(hw_apbh_ch5_curcmdar) + mx28_reg_32(hw_apbh_ch5_nxtcmdar) + mx28_reg_32(hw_apbh_ch5_cmd) + mx28_reg_32(hw_apbh_ch5_bar) + mx28_reg_32(hw_apbh_ch5_sema) + mx28_reg_32(hw_apbh_ch5_debug1) + mx28_reg_32(hw_apbh_ch5_debug2) + mx28_reg_32(hw_apbh_ch6_curcmdar) + mx28_reg_32(hw_apbh_ch6_nxtcmdar) + mx28_reg_32(hw_apbh_ch6_cmd) + mx28_reg_32(hw_apbh_ch6_bar) + mx28_reg_32(hw_apbh_ch6_sema) + mx28_reg_32(hw_apbh_ch6_debug1) + mx28_reg_32(hw_apbh_ch6_debug2) + mx28_reg_32(hw_apbh_ch7_curcmdar) + mx28_reg_32(hw_apbh_ch7_nxtcmdar) + mx28_reg_32(hw_apbh_ch7_cmd) + mx28_reg_32(hw_apbh_ch7_bar) + mx28_reg_32(hw_apbh_ch7_sema) + mx28_reg_32(hw_apbh_ch7_debug1) + mx28_reg_32(hw_apbh_ch7_debug2) + mx28_reg_32(hw_apbh_ch8_curcmdar) + mx28_reg_32(hw_apbh_ch8_nxtcmdar) + mx28_reg_32(hw_apbh_ch8_cmd) + mx28_reg_32(hw_apbh_ch8_bar) + mx28_reg_32(hw_apbh_ch8_sema) + mx28_reg_32(hw_apbh_ch8_debug1) + mx28_reg_32(hw_apbh_ch8_debug2) + mx28_reg_32(hw_apbh_ch9_curcmdar) + mx28_reg_32(hw_apbh_ch9_nxtcmdar) + mx28_reg_32(hw_apbh_ch9_cmd) + mx28_reg_32(hw_apbh_ch9_bar) + mx28_reg_32(hw_apbh_ch9_sema) + mx28_reg_32(hw_apbh_ch9_debug1) + mx28_reg_32(hw_apbh_ch9_debug2) + mx28_reg_32(hw_apbh_ch10_curcmdar) + mx28_reg_32(hw_apbh_ch10_nxtcmdar) + mx28_reg_32(hw_apbh_ch10_cmd) + mx28_reg_32(hw_apbh_ch10_bar) + mx28_reg_32(hw_apbh_ch10_sema) + mx28_reg_32(hw_apbh_ch10_debug1) + mx28_reg_32(hw_apbh_ch10_debug2) + mx28_reg_32(hw_apbh_ch11_curcmdar) + mx28_reg_32(hw_apbh_ch11_nxtcmdar) + mx28_reg_32(hw_apbh_ch11_cmd) + mx28_reg_32(hw_apbh_ch11_bar) + mx28_reg_32(hw_apbh_ch11_sema) + mx28_reg_32(hw_apbh_ch11_debug1) + mx28_reg_32(hw_apbh_ch11_debug2) + mx28_reg_32(hw_apbh_ch12_curcmdar) + mx28_reg_32(hw_apbh_ch12_nxtcmdar) + mx28_reg_32(hw_apbh_ch12_cmd) + mx28_reg_32(hw_apbh_ch12_bar) + mx28_reg_32(hw_apbh_ch12_sema) + mx28_reg_32(hw_apbh_ch12_debug1) + mx28_reg_32(hw_apbh_ch12_debug2) + mx28_reg_32(hw_apbh_ch13_curcmdar) + mx28_reg_32(hw_apbh_ch13_nxtcmdar) + mx28_reg_32(hw_apbh_ch13_cmd) + mx28_reg_32(hw_apbh_ch13_bar) + mx28_reg_32(hw_apbh_ch13_sema) + mx28_reg_32(hw_apbh_ch13_debug1) + mx28_reg_32(hw_apbh_ch13_debug2) + mx28_reg_32(hw_apbh_ch14_curcmdar) + mx28_reg_32(hw_apbh_ch14_nxtcmdar) + mx28_reg_32(hw_apbh_ch14_cmd) + mx28_reg_32(hw_apbh_ch14_bar) + mx28_reg_32(hw_apbh_ch14_sema) + mx28_reg_32(hw_apbh_ch14_debug1) + mx28_reg_32(hw_apbh_ch14_debug2) + mx28_reg_32(hw_apbh_ch15_curcmdar) + mx28_reg_32(hw_apbh_ch15_nxtcmdar) + mx28_reg_32(hw_apbh_ch15_cmd) + mx28_reg_32(hw_apbh_ch15_bar) + mx28_reg_32(hw_apbh_ch15_sema) + mx28_reg_32(hw_apbh_ch15_debug1) + mx28_reg_32(hw_apbh_ch15_debug2) + }; + }; + mx28_reg_32(hw_apbh_version) +}; +#endif + +#define APBH_CTRL0_SFTRST (1 << 31) +#define APBH_CTRL0_CLKGATE (1 << 30) +#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) +#define APBH_CTRL0_APB_BURST_EN (1 << 28) +#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) +#define APBH_CTRL0_RSVD0_OFFSET 16 +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 +#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 +#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) + +#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) +#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) +#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) +#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) +#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) +#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) +#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) +#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) +#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) +#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) +#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) +#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) +#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) +#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) +#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) +#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) +#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) +#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) +#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) +#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) +#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) +#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) +#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) +#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) +#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) +#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) +#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) +#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) +#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) +#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) +#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) +#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) + +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 + +#define APBH_DEVSEL_CH15_MASK (0x3 << 30) +#define APBH_DEVSEL_CH15_OFFSET 30 +#define APBH_DEVSEL_CH14_MASK (0x3 << 28) +#define APBH_DEVSEL_CH14_OFFSET 28 +#define APBH_DEVSEL_CH13_MASK (0x3 << 26) +#define APBH_DEVSEL_CH13_OFFSET 26 +#define APBH_DEVSEL_CH12_MASK (0x3 << 24) +#define APBH_DEVSEL_CH12_OFFSET 24 +#define APBH_DEVSEL_CH11_MASK (0x3 << 22) +#define APBH_DEVSEL_CH11_OFFSET 22 +#define APBH_DEVSEL_CH10_MASK (0x3 << 20) +#define APBH_DEVSEL_CH10_OFFSET 20 +#define APBH_DEVSEL_CH9_MASK (0x3 << 18) +#define APBH_DEVSEL_CH9_OFFSET 18 +#define APBH_DEVSEL_CH8_MASK (0x3 << 16) +#define APBH_DEVSEL_CH8_OFFSET 16 +#define APBH_DEVSEL_CH7_MASK (0x3 << 14) +#define APBH_DEVSEL_CH7_OFFSET 14 +#define APBH_DEVSEL_CH6_MASK (0x3 << 12) +#define APBH_DEVSEL_CH6_OFFSET 12 +#define APBH_DEVSEL_CH5_MASK (0x3 << 10) +#define APBH_DEVSEL_CH5_OFFSET 10 +#define APBH_DEVSEL_CH4_MASK (0x3 << 8) +#define APBH_DEVSEL_CH4_OFFSET 8 +#define APBH_DEVSEL_CH3_MASK (0x3 << 6) +#define APBH_DEVSEL_CH3_OFFSET 6 +#define APBH_DEVSEL_CH2_MASK (0x3 << 4) +#define APBH_DEVSEL_CH2_OFFSET 4 +#define APBH_DEVSEL_CH1_MASK (0x3 << 2) +#define APBH_DEVSEL_CH1_OFFSET 2 +#define APBH_DEVSEL_CH0_MASK (0x3 << 0) +#define APBH_DEVSEL_CH0_OFFSET 0 + +#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) +#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) +#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 +#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) +#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) +#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 +#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) +#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) +#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 +#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) +#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) +#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 +#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) +#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) +#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 +#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) +#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) +#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 +#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) +#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 +#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) + +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) +#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 +#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) +#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 +#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) + +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 +#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 +#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 +#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 +#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 + +#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) + +#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) +#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 +#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) +#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 +#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) +#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) +#define APBH_CHn_CMD_SEMAPHORE (1 << 6) +#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) +#define APBH_CHn_CMD_NANDLOCK (1 << 4) +#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) +#define APBH_CHn_CMD_CHAIN (1 << 2) +#define APBH_CHn_CMD_COMMAND_MASK 0x3 +#define APBH_CHn_CMD_COMMAND_OFFSET 0 +#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 +#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 +#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 +#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 + +#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff +#define APBH_CHn_BAR_ADDRESS_OFFSET 0 + +#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) +#define APBH_CHn_SEMA_RSVD2_OFFSET 24 +#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) +#define APBH_CHn_SEMA_PHORE_OFFSET 16 +#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) +#define APBH_CHn_SEMA_RSVD1_OFFSET 8 +#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) +#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 + +#define APBH_CHn_DEBUG1_REQ (1 << 31) +#define APBH_CHn_DEBUG1_BURST (1 << 30) +#define APBH_CHn_DEBUG1_KICK (1 << 29) +#define APBH_CHn_DEBUG1_END (1 << 28) +#define APBH_CHn_DEBUG1_SENSE (1 << 27) +#define APBH_CHn_DEBUG1_READY (1 << 26) +#define APBH_CHn_DEBUG1_LOCK (1 << 25) +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) +#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) +#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) +#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) +#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 +#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f +#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 +#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 +#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f +#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c +#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f + +#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) +#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 +#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff +#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 + +#define APBH_VERSION_MAJOR_MASK (0xff << 24) +#define APBH_VERSION_MAJOR_OFFSET 24 +#define APBH_VERSION_MINOR_MASK (0xff << 16) +#define APBH_VERSION_MINOR_OFFSET 16 +#define APBH_VERSION_STEP_MASK 0xffff +#define APBH_VERSION_STEP_OFFSET 0 + +#endif /* __REGS_APBH_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h new file mode 100644 index 0000000..dbdcc2b --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -0,0 +1,88 @@ +/* + * Freescale i.MX28 Peripheral Base Addresses + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BASE_H__ +#define __MX28_REGS_BASE_H__ + +/* + * Register base address + */ +#define MXS_ICOL_BASE 0x80000000 +#define MXS_HSADC_BASE 0x80002000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_PERFMON_BASE 0x80006000 +#define MXS_BCH_BASE 0x8000A000 +#define MXS_GPMI_BASE 0x8000C000 +#define MXS_SSP0_BASE 0x80010000 +#define MXS_SSP1_BASE 0x80012000 +#define MXS_SSP2_BASE 0x80014000 +#define MXS_SSP3_BASE 0x80016000 +#define MXS_PINCTRL_BASE 0x80018000 +#define MXS_DIGCTL_BASE 0x8001C000 +#define MXS_ETM_BASE 0x80022000 +#define MXS_APBX_BASE 0x80024000 +#define MXS_DCP_BASE 0x80028000 +#define MXS_PXP_BASE 0x8002A000 +#define MXS_OCOTP_BASE 0x8002C000 +#define MXS_AXI_AHB0_BASE 0x8002E000 +#define MXS_LCDIF_BASE 0x80030000 +#define MXS_CAN0_BASE 0x80032000 +#define MXS_CAN1_BASE 0x80034000 +#define MXS_SIMDBG_BASE 0x8003C000 +#define MXS_SIMGPMISEL_BASE 0x8003C200 +#define MXS_SIMSSPSEL_BASE 0x8003C300 +#define MXS_SIMMEMSEL_BASE 0x8003C400 +#define MXS_GPIOMON_BASE 0x8003C500 +#define MXS_SIMENET_BASE 0x8003C700 +#define MXS_ARMJTAG_BASE 0x8003C800 +#define MXS_CLKCTRL_BASE 0x80040000 +#define MXS_SAIF0_BASE 0x80042000 +#define MXS_POWER_BASE 0x80044000 +#define MXS_SAIF1_BASE 0x80046000 +#define MXS_LRADC_BASE 0x80050000 +#define MXS_SPDIF_BASE 0x80054000 +#define MXS_RTC_BASE 0x80056000 +#define MXS_I2C0_BASE 0x80058000 +#define MXS_I2C1_BASE 0x8005A000 +#define MXS_PWM_BASE 0x80064000 +#define MXS_TIMROT_BASE 0x80068000 +#define MXS_UARTAPP0_BASE 0x8006A000 +#define MXS_UARTAPP1_BASE 0x8006C000 +#define MXS_UARTAPP2_BASE 0x8006E000 +#define MXS_UARTAPP3_BASE 0x80070000 +#define MXS_UARTAPP4_BASE 0x80072000 +#define MXS_UARTDBG_BASE 0x80074000 +#define MXS_USBPHY0_BASE 0x8007C000 +#define MXS_USBPHY1_BASE 0x8007E000 +#define MXS_USBCTRL0_BASE 0x80080000 +#define MXS_USBCTRL1_BASE 0x80090000 +#define MXS_DFLPT_BASE 0x800C0000 +#define MXS_DRAM_BASE 0x800E0000 +#define MXS_ENET0_BASE 0x800F0000 +#define MXS_ENET1_BASE 0x800F4000 + +#endif /* __MX28_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-bch.h b/arch/arm/include/asm/arch-mxs/regs-bch.h new file mode 100644 index 0000000..9243bdd --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-bch.h @@ -0,0 +1,230 @@ +/* + * Freescale i.MX28 BCH Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BCH_H__ +#define __MX28_REGS_BCH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_bch_regs { + mx28_reg_32(hw_bch_ctrl) + mx28_reg_32(hw_bch_status0) + mx28_reg_32(hw_bch_mode) + mx28_reg_32(hw_bch_encodeptr) + mx28_reg_32(hw_bch_dataptr) + mx28_reg_32(hw_bch_metaptr) + + uint32_t reserved[4]; + + mx28_reg_32(hw_bch_layoutselect) + mx28_reg_32(hw_bch_flash0layout0) + mx28_reg_32(hw_bch_flash0layout1) + mx28_reg_32(hw_bch_flash1layout0) + mx28_reg_32(hw_bch_flash1layout1) + mx28_reg_32(hw_bch_flash2layout0) + mx28_reg_32(hw_bch_flash2layout1) + mx28_reg_32(hw_bch_flash3layout0) + mx28_reg_32(hw_bch_flash3layout1) + mx28_reg_32(hw_bch_dbgkesread) + mx28_reg_32(hw_bch_dbgcsferead) + mx28_reg_32(hw_bch_dbgsyndegread) + mx28_reg_32(hw_bch_dbgahbmread) + mx28_reg_32(hw_bch_blockname) + mx28_reg_32(hw_bch_version) +}; +#endif + +#define BCH_CTRL_SFTRST (1 << 31) +#define BCH_CTRL_CLKGATE (1 << 30) +#define BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) +#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 +#define BCH_CTRL_M2M_ENCODE (1 << 17) +#define BCH_CTRL_M2M_ENABLE (1 << 16) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) +#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) +#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) +#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) +#define BCH_CTRL_COMPLETE_IRQ (1 << 0) + +#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) +#define BCH_STATUS0_HANDLE_OFFSET 20 +#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) +#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 +#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) +#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 +#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) +#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) +#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) +#define BCH_STATUS0_ALLONES (1 << 4) +#define BCH_STATUS0_CORRECTED (1 << 3) +#define BCH_STATUS0_UNCORRECTABLE (1 << 2) + +#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff +#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 + +#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff +#define BCH_ENCODEPTR_ADDR_OFFSET 0 + +#define BCH_DATAPTR_ADDR_MASK 0xffffffff +#define BCH_DATAPTR_ADDR_OFFSET 0 + +#define BCH_METAPTR_ADDR_MASK 0xffffffff +#define BCH_METAPTR_ADDR_OFFSET 0 + +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) +#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) +#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) +#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) +#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) +#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) +#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) +#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) +#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) +#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) +#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) +#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) +#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) +#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) +#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) +#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) +#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 + +#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) +#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 +#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) +#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 +#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 + +#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) +#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 +#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 + +#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) +#define BCH_DEBUG0_RSVD1_OFFSET 27 +#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) +#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) +#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) +#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) +#define BCH_DEBUG0_KES_STANDALONE (1 << 11) +#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) +#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) +#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) +#define BCH_DEBUG0_RSVD0_OFFSET 6 +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f +#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 + +#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff +#define BCH_DBGKESREAD_VALUES_OFFSET 0 + +#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff +#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 + +#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff +#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 + +#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff +#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 + +#define BCH_BLOCKNAME_NAME_MASK 0xffffffff +#define BCH_BLOCKNAME_NAME_OFFSET 0 + +#define BCH_VERSION_MAJOR_MASK (0xff << 24) +#define BCH_VERSION_MAJOR_OFFSET 24 +#define BCH_VERSION_MINOR_MASK (0xff << 16) +#define BCH_VERSION_MINOR_OFFSET 16 +#define BCH_VERSION_STEP_MASK 0xffff +#define BCH_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_BCH_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl.h new file mode 100644 index 0000000..3c4947d --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl.h @@ -0,0 +1,294 @@ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_clkctrl_regs { + mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mx28_reg_32(hw_clkctrl_etm) /* 0x130 */ + mx28_reg_32(hw_clkctrl_enet) /* 0x140 */ + mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mx28_reg_32(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-common.h b/arch/arm/include/asm/arch-mxs/regs-common.h new file mode 100644 index 0000000..d2e1953 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-common.h @@ -0,0 +1,82 @@ +/* + * Freescale i.MX28 Register Accessors + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_COMMON_H__ +#define __MX28_REGS_COMMON_H__ + +/* + * The i.MX28 has interesting feature when it comes to register access. There + * are four kinds of access to one particular register. Those are: + * + * 1) Common read/write access. To use this mode, just write to the address of + * the register. + * 2) Set bits only access. To set bits, write which bits you want to set to the + * address of the register + 0x4. + * 3) Clear bits only access. To clear bits, write which bits you want to clear + * to the address of the register + 0x8. + * 4) Toggle bits only access. To toggle bits, write which bits you want to + * toggle to the address of the register + 0xc. + * + * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits + * can be set/cleared by pure write as in access type 1, some need to be + * explicitly set/cleared by using access type 2-3. + * + * The following macros and structures allow the user to either access the + * register in all aforementioned modes (by accessing reg_name, reg_name_set, + * reg_name_clr, reg_name_tog) or pass the register structure further into + * various functions with correct type information (by accessing reg_name_reg). + * + */ + +#define __mx28_reg_8(name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ + +#define __mx28_reg_32(name) \ + uint32_t name; \ + uint32_t name##_set; \ + uint32_t name##_clr; \ + uint32_t name##_tog; + +struct mx28_register_8 { + __mx28_reg_8(reg) +}; + +struct mx28_register_32 { + __mx28_reg_32(reg) +}; + +#define mx28_reg_8(name) \ + union { \ + struct { __mx28_reg_8(name) }; \ + struct mx28_register_8 name##_reg; \ + }; + +#define mx28_reg_32(name) \ + union { \ + struct { __mx28_reg_32(name) }; \ + struct mx28_register_32 name##_reg; \ + }; + +#endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h new file mode 100644 index 0000000..9a63594 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h @@ -0,0 +1,155 @@ +/* + * Freescale i.MX28 DIGCTL Register Definitions + * + * Copyright (C) 2012 Robert Delien robert@delien.nl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_DIGCTL_H__ +#define __MX28_REGS_DIGCTL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_digctl_regs { + mx28_reg_32(hw_digctl_ctrl) /* 0x000 */ + mx28_reg_32(hw_digctl_status) /* 0x010 */ + mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */ + mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */ + mx28_reg_32(hw_digctl_emi_status) /* 0x040 */ + mx28_reg_32(hw_digctl_read_margin) /* 0x050 */ + uint32_t hw_digctl_writeonce; /* 0x060 */ + uint32_t reserved_writeonce[3]; + mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */ + mx28_reg_32(hw_digctl_bist_status) /* 0x080 */ + uint32_t hw_digctl_entropy; /* 0x090 */ + uint32_t reserved_entropy[3]; + uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ + uint32_t reserved_entropy_latched[3]; + + uint32_t reserved1[4]; + + mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + uint32_t hw_digctl_dbgrd; /* 0x0d0 */ + uint32_t reserved_hw_digctl_dbgrd[3]; + uint32_t hw_digctl_dbg; /* 0x0e0 */ + uint32_t reserved_hw_digctl_dbg[3]; + + uint32_t reserved2[4]; + + mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */ + mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */ + mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */ + mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */ + mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */ + mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */ + mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */ + mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */ + mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */ + mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */ + mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ + mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ + mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ + mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ + mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + + uint32_t reserved3[36]; + + uint32_t hw_digctl_scratch0; /* 0x280 */ + uint32_t reserved_hw_digctl_scratch0[3]; + uint32_t hw_digctl_scratch1; /* 0x290 */ + uint32_t reserved_hw_digctl_scratch1[3]; + uint32_t hw_digctl_armcache; /* 0x2a0 */ + uint32_t reserved_hw_digctl_armcache[3]; + mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; + uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; + uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; + uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; + uint32_t hw_digctl_fsl; /* 0x300 */ + uint32_t reserved_hw_digctl_fsl[3]; + uint32_t hw_digctl_chipid; /* 0x310 */ + uint32_t reserved_hw_digctl_chipid[3]; + + uint32_t reserved4[4]; + + uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ + uint32_t reserved_hw_digctl_ahb_stats_select[3]; + + uint32_t reserved5[12]; + + uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ + uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; + uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ + uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; + uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ + uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; + uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ + uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; + uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; + uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; + uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ + uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; + uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; + uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; + + uint32_t reserved6[64]; + + uint32_t hw_digctl_mpte0_loc; /* 0x500 */ + uint32_t reserved_hw_digctl_mpte0_loc[3]; + uint32_t hw_digctl_mpte1_loc; /* 0x510 */ + uint32_t reserved_hw_digctl_mpte1_loc[3]; + uint32_t hw_digctl_mpte2_loc; /* 0x520 */ + uint32_t reserved_hw_digctl_mpte2_loc[3]; + uint32_t hw_digctl_mpte3_loc; /* 0x530 */ + uint32_t reserved_hw_digctl_mpte3_loc[3]; + uint32_t hw_digctl_mpte4_loc; /* 0x540 */ + uint32_t reserved_hw_digctl_mpte4_loc[3]; + uint32_t hw_digctl_mpte5_loc; /* 0x550 */ + uint32_t reserved_hw_digctl_mpte5_loc[3]; + uint32_t hw_digctl_mpte6_loc; /* 0x560 */ + uint32_t reserved_hw_digctl_mpte6_loc[3]; + uint32_t hw_digctl_mpte7_loc; /* 0x570 */ + uint32_t reserved_hw_digctl_mpte7_loc[3]; + uint32_t hw_digctl_mpte8_loc; /* 0x580 */ + uint32_t reserved_hw_digctl_mpte8_loc[3]; + uint32_t hw_digctl_mpte9_loc; /* 0x590 */ + uint32_t reserved_hw_digctl_mpte9_loc[3]; + uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ + uint32_t reserved_hw_digctl_mpte10_loc[3]; + uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ + uint32_t reserved_hw_digctl_mpte11_loc[3]; + uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ + uint32_t reserved_hw_digctl_mpte12_loc[3]; + uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ + uint32_t reserved_hw_digctl_mpte13_loc[3]; + uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ + uint32_t reserved_hw_digctl_mpte14_loc[3]; + uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ + uint32_t reserved_hw_digctl_mpte15_loc[3]; +}; +#endif + +#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-gpmi.h b/arch/arm/include/asm/arch-mxs/regs-gpmi.h new file mode 100644 index 0000000..1b487f4 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-gpmi.h @@ -0,0 +1,222 @@ +/* + * Freescale i.MX28 GPMI Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_GPMI_H__ +#define __MX28_REGS_GPMI_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_gpmi_regs { + mx28_reg_32(hw_gpmi_ctrl0) + mx28_reg_32(hw_gpmi_compare) + mx28_reg_32(hw_gpmi_eccctrl) + mx28_reg_32(hw_gpmi_ecccount) + mx28_reg_32(hw_gpmi_payload) + mx28_reg_32(hw_gpmi_auxiliary) + mx28_reg_32(hw_gpmi_ctrl1) + mx28_reg_32(hw_gpmi_timing0) + mx28_reg_32(hw_gpmi_timing1) + + uint32_t reserved[4]; + + mx28_reg_32(hw_gpmi_data) + mx28_reg_32(hw_gpmi_stat) + mx28_reg_32(hw_gpmi_debug) + mx28_reg_32(hw_gpmi_version) +}; +#endif + +#define GPMI_CTRL0_SFTRST (1 << 31) +#define GPMI_CTRL0_CLKGATE (1 << 30) +#define GPMI_CTRL0_RUN (1 << 29) +#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) +#define GPMI_CTRL0_LOCK_CS (1 << 27) +#define GPMI_CTRL0_UDMA (1 << 26) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) +#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 +#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) +#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) +#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_CS_MASK (0x7 << 20) +#define GPMI_CTRL0_CS_OFFSET 20 +#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) +#define GPMI_CTRL0_ADDRESS_OFFSET 17 +#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) +#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff +#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 + +#define GPMI_COMPARE_MASK_MASK (0xffff << 16) +#define GPMI_COMPARE_MASK_OFFSET 16 +#define GPMI_COMPARE_REFERENCE_MASK 0xffff +#define GPMI_COMPARE_REFERENCE_OFFSET 0 + +#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) +#define GPMI_ECCCTRL_HANDLE_OFFSET 16 +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) +#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 +#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) +#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) +#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff +#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff + +#define GPMI_ECCCOUNT_COUNT_MASK 0xffff +#define GPMI_ECCCOUNT_COUNT_OFFSET 0 + +#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 + +#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 + +#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) +#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) +#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) +#define GPMI_CTRL1_BCH_MODE (1 << 18) +#define GPMI_CTRL1_DLL_ENABLE (1 << 17) +#define GPMI_CTRL1_HALF_PERIOD (1 << 16) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) +#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 +#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) +#define GPMI_CTRL1_DEV_IRQ (1 << 10) +#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) +#define GPMI_CTRL1_BURST_EN (1 << 8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 +#define GPMI_CTRL1_DEV_RESET (1 << 3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) +#define GPMI_CTRL1_CAMERA_MODE (1 << 1) +#define GPMI_CTRL1_GPMI_MODE (1 << 0) + +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) +#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 +#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 +#define GPMI_TIMING0_DATA_SETUP_MASK 0xff +#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 + +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 + +#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) +#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 +#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) +#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 +#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 +#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff +#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 + +#define GPMI_DATA_DATA_MASK 0xffffffff +#define GPMI_DATA_DATA_OFFSET 0 + +#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) +#define GPMI_STAT_READY_BUSY_OFFSET 24 +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) +#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 +#define GPMI_STAT_DEV7_ERROR (1 << 15) +#define GPMI_STAT_DEV6_ERROR (1 << 14) +#define GPMI_STAT_DEV5_ERROR (1 << 13) +#define GPMI_STAT_DEV4_ERROR (1 << 12) +#define GPMI_STAT_DEV3_ERROR (1 << 11) +#define GPMI_STAT_DEV2_ERROR (1 << 10) +#define GPMI_STAT_DEV1_ERROR (1 << 9) +#define GPMI_STAT_DEV0_ERROR (1 << 8) +#define GPMI_STAT_ATA_IRQ (1 << 4) +#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) +#define GPMI_STAT_FIFO_EMPTY (1 << 2) +#define GPMI_STAT_FIFO_FULL (1 << 1) +#define GPMI_STAT_PRESENT (1 << 0) + +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) +#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 +#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) +#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 +#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) +#define GPMI_DEBUG_DMAREQ_OFFSET 8 +#define GPMI_DEBUG_CMD_END_MASK 0xff +#define GPMI_DEBUG_CMD_END_OFFSET 0 + +#define GPMI_VERSION_MAJOR_MASK (0xff << 24) +#define GPMI_VERSION_MAJOR_OFFSET 24 +#define GPMI_VERSION_MINOR_MASK (0xff << 16) +#define GPMI_VERSION_MINOR_OFFSET 16 +#define GPMI_VERSION_STEP_MASK 0xffff +#define GPMI_VERSION_STEP_OFFSET 0 + +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) +#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 +#define GPMI_DEBUG2_BUSY (1 << 23) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) +#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 +#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) +#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 +#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) +#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 +#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) +#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) +#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) +#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) +#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f +#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 + +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) +#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff +#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 + +#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h new file mode 100644 index 0000000..2e2e814 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h @@ -0,0 +1,207 @@ +/* + * Freescale i.MX28 I2C Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_I2C_H__ +#define __MX28_REGS_I2C_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_i2c_regs { + mx28_reg_32(hw_i2c_ctrl0) + mx28_reg_32(hw_i2c_timing0) + mx28_reg_32(hw_i2c_timing1) + mx28_reg_32(hw_i2c_timing2) + mx28_reg_32(hw_i2c_ctrl1) + mx28_reg_32(hw_i2c_stat) + mx28_reg_32(hw_i2c_queuectrl) + mx28_reg_32(hw_i2c_queuestat) + mx28_reg_32(hw_i2c_queuecmd) + mx28_reg_32(hw_i2c_queuedata) + mx28_reg_32(hw_i2c_data) + mx28_reg_32(hw_i2c_debug0) + mx28_reg_32(hw_i2c_debug1) + mx28_reg_32(hw_i2c_version) +}; +#endif + +#define I2C_CTRL_SFTRST (1 << 31) +#define I2C_CTRL_CLKGATE (1 << 30) +#define I2C_CTRL_RUN (1 << 29) +#define I2C_CTRL_PREACK (1 << 27) +#define I2C_CTRL_ACKNOWLEDGE (1 << 26) +#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) +#define I2C_CTRL_MULTI_MASTER (1 << 23) +#define I2C_CTRL_CLOCK_HELD (1 << 22) +#define I2C_CTRL_RETAIN_CLOCK (1 << 21) +#define I2C_CTRL_POST_SEND_STOP (1 << 20) +#define I2C_CTRL_PRE_SEND_START (1 << 19) +#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_CTRL_MASTER_MODE (1 << 17) +#define I2C_CTRL_DIRECTION (1 << 16) +#define I2C_CTRL_XFER_COUNT_MASK 0xffff +#define I2C_CTRL_XFER_COUNT_OFFSET 0 + +#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 +#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff +#define I2C_TIMING0_RCV_COUNT_OFFSET 0 + +#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING1_LOW_COUNT_OFFSET 16 +#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff +#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 + +#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) +#define I2C_TIMING2_BUS_FREE_OFFSET 16 +#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff +#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 + +#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) +#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) +#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) +#define I2C_CTRL1_ACK_MODE (1 << 27) +#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) +#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) +#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 +#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) +#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) +#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) +#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) +#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) +#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) +#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) +#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) +#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) +#define I2C_CTRL1_SLAVE_IRQ (1 << 0) + +#define I2C_STAT_MASTER_PRESENT (1 << 31) +#define I2C_STAT_SLAVE_PRESENT (1 << 30) +#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) +#define I2C_STAT_GOT_A_NAK (1 << 28) +#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) +#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 +#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) +#define I2C_STAT_SLAVE_FOUND (1 << 14) +#define I2C_STAT_SLAVE_SEARCHING (1 << 13) +#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) +#define I2C_STAT_BUS_BUSY (1 << 11) +#define I2C_STAT_CLK_GEN_BUSY (1 << 10) +#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) +#define I2C_STAT_SLAVE_BUSY (1 << 8) +#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) +#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) +#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) +#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) +#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) +#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) +#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) +#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) + +#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) +#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 +#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) +#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 +#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) +#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) +#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) +#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) +#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) +#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) + +#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) +#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 +#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) +#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) +#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f +#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 + +#define I2C_QUEUECMD_PREACK (1 << 27) +#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) +#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) +#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) +#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) +#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) +#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) +#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) +#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_QUEUECMD_MASTER_MODE (1 << 17) +#define I2C_QUEUECMD_DIRECTION (1 << 16) +#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff +#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 + +#define I2C_QUEUEDATA_DATA_MASK 0xffffffff +#define I2C_QUEUEDATA_DATA_OFFSET 0 + +#define I2C_DATA_DATA_MASK 0xffffffff +#define I2C_DATA_DATA_OFFSET 0 + +#define I2C_DEBUG0_DMAREQ (1 << 31) +#define I2C_DEBUG0_DMAENDCMD (1 << 30) +#define I2C_DEBUG0_DMAKICK (1 << 29) +#define I2C_DEBUG0_DMATERMINATE (1 << 28) +#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) +#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 +#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) +#define I2C_DEBUG0_DMA_STATE_OFFSET 16 +#define I2C_DEBUG0_START_TOGGLE (1 << 15) +#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) +#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) +#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) +#define I2C_DEBUG0_STATE_LATCH (1 << 11) +#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) +#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff +#define I2C_DEBUG0_STATE_STATE_OFFSET 0 + +#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) +#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 +#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) +#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 +#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) +#define I2C_DEBUG1_LST_MODE_OFFSET 9 +#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) +#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) +#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) +#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) +#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) +#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) + +#define I2C_VERSION_MAJOR_MASK (0xff << 24) +#define I2C_VERSION_MAJOR_OFFSET 24 +#define I2C_VERSION_MINOR_MASK (0xff << 16) +#define I2C_VERSION_MINOR_OFFSET 16 +#define I2C_VERSION_STEP_MASK 0xffff +#define I2C_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h new file mode 100644 index 0000000..2738035 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h @@ -0,0 +1,173 @@ +/* + * Freescale i.MX28 OCOTP Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_OCOTP_H__ +#define __MX28_REGS_OCOTP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ocotp_regs { + mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */ + mx28_reg_32(hw_ocotp_data) /* 0x10 */ + mx28_reg_32(hw_ocotp_cust0) /* 0x20 */ + mx28_reg_32(hw_ocotp_cust1) /* 0x30 */ + mx28_reg_32(hw_ocotp_cust2) /* 0x40 */ + mx28_reg_32(hw_ocotp_cust3) /* 0x50 */ + mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */ + mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */ + mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */ + mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */ + mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ + mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ + mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ + mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ + mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ + mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ + mx28_reg_32(hw_ocotp_swcap) /* 0x100 */ + mx28_reg_32(hw_ocotp_custcap) /* 0x110 */ + mx28_reg_32(hw_ocotp_lock) /* 0x120 */ + mx28_reg_32(hw_ocotp_ops0) /* 0x130 */ + mx28_reg_32(hw_ocotp_ops1) /* 0x140 */ + mx28_reg_32(hw_ocotp_ops2) /* 0x150 */ + mx28_reg_32(hw_ocotp_ops3) /* 0x160 */ + mx28_reg_32(hw_ocotp_un0) /* 0x170 */ + mx28_reg_32(hw_ocotp_un1) /* 0x180 */ + mx28_reg_32(hw_ocotp_un2) /* 0x190 */ + mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */ + mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */ + mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */ + mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */ + mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */ + mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */ + mx28_reg_32(hw_ocotp_rom6) /* 0x200 */ + mx28_reg_32(hw_ocotp_rom7) /* 0x210 */ + mx28_reg_32(hw_ocotp_srk0) /* 0x220 */ + mx28_reg_32(hw_ocotp_srk1) /* 0x230 */ + mx28_reg_32(hw_ocotp_srk2) /* 0x240 */ + mx28_reg_32(hw_ocotp_srk3) /* 0x250 */ + mx28_reg_32(hw_ocotp_srk4) /* 0x260 */ + mx28_reg_32(hw_ocotp_srk5) /* 0x270 */ + mx28_reg_32(hw_ocotp_srk6) /* 0x280 */ + mx28_reg_32(hw_ocotp_srk7) /* 0x290 */ + mx28_reg_32(hw_ocotp_version) /* 0x2a0 */ +}; +#endif + +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) +#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 +#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) +#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) +#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +#define OCOTP_CTRL_ERROR (1 << 9) +#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_ADDR_MASK 0x3f +#define OCOTP_CTRL_ADDR_OFFSET 0 + +#define OCOTP_DATA_DATA_MASK 0xffffffff +#define OCOTP_DATA_DATA_OFFSET 0 + +#define OCOTP_CUST_BITS_MASK 0xffffffff +#define OCOTP_CUST_BITS_OFFSET 0 + +#define OCOTP_CRYPTO_BITS_MASK 0xffffffff +#define OCOTP_CRYPTO_BITS_OFFSET 0 + +#define OCOTP_HWCAP_BITS_MASK 0xffffffff +#define OCOTP_HWCAP_BITS_OFFSET 0 + +#define OCOTP_SWCAP_BITS_MASK 0xffffffff +#define OCOTP_SWCAP_BITS_OFFSET 0 + +#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) +#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) + +#define OCOTP_LOCK_ROM7 (1 << 31) +#define OCOTP_LOCK_ROM6 (1 << 30) +#define OCOTP_LOCK_ROM5 (1 << 29) +#define OCOTP_LOCK_ROM4 (1 << 28) +#define OCOTP_LOCK_ROM3 (1 << 27) +#define OCOTP_LOCK_ROM2 (1 << 26) +#define OCOTP_LOCK_ROM1 (1 << 25) +#define OCOTP_LOCK_ROM0 (1 << 24) +#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) +#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) +#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) +#define OCOTP_LOCK_PIN (1 << 20) +#define OCOTP_LOCK_OPS (1 << 19) +#define OCOTP_LOCK_UN2 (1 << 18) +#define OCOTP_LOCK_UN1 (1 << 17) +#define OCOTP_LOCK_UN0 (1 << 16) +#define OCOTP_LOCK_SRK (1 << 15) +#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) +#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 +#define OCOTP_LOCK_SRK_SHADOW (1 << 11) +#define OCOTP_LOCK_ROM_SHADOW (1 << 10) +#define OCOTP_LOCK_CUSTCAP (1 << 9) +#define OCOTP_LOCK_HWSW (1 << 8) +#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) +#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) +#define OCOTP_LOCK_CRYPTODCP (1 << 5) +#define OCOTP_LOCK_CRYPTOKEY (1 << 4) +#define OCOTP_LOCK_CUST3 (1 << 3) +#define OCOTP_LOCK_CUST2 (1 << 2) +#define OCOTP_LOCK_CUST1 (1 << 1) +#define OCOTP_LOCK_CUST0 (1 << 0) + +#define OCOTP_OPS_BITS_MASK 0xffffffff +#define OCOTP_OPS_BITS_OFFSET 0 + +#define OCOTP_UN_BITS_MASK 0xffffffff +#define OCOTP_UN_BITS_OFFSET 0 + +#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) +#define OCOTP_ROM_BOOT_MODE_OFFSET 24 +#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) +#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 +#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) +#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 +#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) +#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 +#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) +#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 +#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) +#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 +#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) +#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) +#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) +#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) +#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) + +#define OCOTP_SRK_BITS_MASK 0xffffffff +#define OCOTP_SRK_BITS_OFFSET 0 + +#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) +#define OCOTP_VERSION_MAJOR_OFFSET 24 +#define OCOTP_VERSION_MINOR_MASK (0xff << 16) +#define OCOTP_VERSION_MINOR_OFFSET 16 +#define OCOTP_VERSION_STEP_MASK 0xffff +#define OCOTP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h new file mode 100644 index 0000000..80dcdf6 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h @@ -0,0 +1,1284 @@ +/* + * Freescale i.MX28 PINCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_PINCTRL_H__ +#define __MX28_REGS_PINCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_pinctrl_regs { + mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */ + + uint32_t reserved1[60]; + + mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ + mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ + mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ + mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ + mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ + mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ + mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ + mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ + mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ + mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ + mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ + mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ + mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ + mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ + + uint32_t reserved2[72]; + + mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */ + mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */ + mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */ + mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */ + mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */ + mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */ + mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */ + mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */ + mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */ + mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */ + mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ + mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ + mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ + mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ + mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ + mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ + mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */ + mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */ + mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */ + mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */ + + uint32_t reserved3[112]; + + mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */ + mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */ + mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */ + mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */ + mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */ + mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */ + mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */ + + uint32_t reserved4[36]; + + mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */ + mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */ + mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */ + mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */ + mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */ + + uint32_t reserved5[108]; + + mx28_reg_32(hw_pinctrl_din0) /* 0x900 */ + mx28_reg_32(hw_pinctrl_din1) /* 0x910 */ + mx28_reg_32(hw_pinctrl_din2) /* 0x920 */ + mx28_reg_32(hw_pinctrl_din3) /* 0x930 */ + mx28_reg_32(hw_pinctrl_din4) /* 0x940 */ + + uint32_t reserved6[108]; + + mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */ + mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */ + mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */ + mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */ + mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */ + + uint32_t reserved7[300]; + + mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ + mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ + mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ + mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ + mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ + + uint32_t reserved8[44]; + + mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ + mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ + mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ + mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ + mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ + + uint32_t reserved9[44]; + + mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ + mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ + mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ + mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ + mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ + + uint32_t reserved10[44]; + + mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ + mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ + mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ + mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ + mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ + + uint32_t reserved11[44]; + + mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ + mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ + mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ + mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ + mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ + + uint32_t reserved12[380]; + + mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + + uint32_t reserved13[76]; + + mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ +}; +#endif + +#define PINCTRL_CTRL_SFTRST (1 << 31) +#define PINCTRL_CTRL_CLKGATE (1 << 30) +#define PINCTRL_CTRL_PRESENT4 (1 << 24) +#define PINCTRL_CTRL_PRESENT3 (1 << 23) +#define PINCTRL_CTRL_PRESENT2 (1 << 22) +#define PINCTRL_CTRL_PRESENT1 (1 << 21) +#define PINCTRL_CTRL_PRESENT0 (1 << 20) +#define PINCTRL_CTRL_IRQOUT4 (1 << 4) +#define PINCTRL_CTRL_IRQOUT3 (1 << 3) +#define PINCTRL_CTRL_IRQOUT2 (1 << 2) +#define PINCTRL_CTRL_IRQOUT1 (1 << 1) +#define PINCTRL_CTRL_IRQOUT0 (1 << 0) + +#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) +#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 +#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 + +#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 +#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 + +#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) +#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) +#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) +#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) +#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) +#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) +#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) +#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) +#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) +#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) +#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) +#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) +#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) +#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) +#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) +#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) +#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) +#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) +#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) +#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) +#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) + +#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) +#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) +#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) +#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) +#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) +#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) +#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) +#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) +#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) +#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) +#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) +#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) +#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) +#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) +#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) +#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) +#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) +#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) +#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) +#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) +#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) +#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) +#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) +#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) +#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) +#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) +#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) +#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) +#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) +#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) +#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) +#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) + +#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) +#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) +#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) +#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) +#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) +#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) +#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) +#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) +#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) +#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) +#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) +#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) +#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) +#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) +#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) +#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) +#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) +#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) +#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) +#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) +#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) +#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) +#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) +#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) +#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) + +#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) +#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) +#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) +#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) +#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) +#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) +#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) +#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) +#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) +#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) +#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) +#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) +#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) +#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) +#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) +#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) +#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) +#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) +#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) +#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) +#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) +#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) +#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) +#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) +#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) +#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) +#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) +#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) +#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) +#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) + +#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) +#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) +#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) +#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) +#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) +#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) +#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) +#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) +#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) +#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) +#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) +#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) +#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) +#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) +#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) +#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) +#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) +#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) + +#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) +#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) +#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) +#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) +#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) +#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) +#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) +#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) +#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) +#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) +#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) +#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) +#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) +#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) +#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) +#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) +#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) +#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) +#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) +#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) +#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) +#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) +#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) +#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) +#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) + +#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) +#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) +#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) +#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) +#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) +#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) +#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) +#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) +#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) +#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) +#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) +#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) +#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) +#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) +#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) +#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) +#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) +#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) +#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) +#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) +#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) +#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) +#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) +#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) + +#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff +#define PINCTRL_DOUT0_DOUT_OFFSET 0 + +#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff +#define PINCTRL_DOUT1_DOUT_OFFSET 0 + +#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff +#define PINCTRL_DOUT2_DOUT_OFFSET 0 + +#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff +#define PINCTRL_DOUT3_DOUT_OFFSET 0 + +#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff +#define PINCTRL_DOUT4_DOUT_OFFSET 0 + +#define PINCTRL_DIN0_DIN_MASK 0x1fffffff +#define PINCTRL_DIN0_DIN_OFFSET 0 + +#define PINCTRL_DIN1_DIN_MASK 0xffffffff +#define PINCTRL_DIN1_DIN_OFFSET 0 + +#define PINCTRL_DIN2_DIN_MASK 0xfffffff +#define PINCTRL_DIN2_DIN_OFFSET 0 + +#define PINCTRL_DIN3_DIN_MASK 0x7fffffff +#define PINCTRL_DIN3_DIN_OFFSET 0 + +#define PINCTRL_DIN4_DIN_MASK 0x1fffff +#define PINCTRL_DIN4_DIN_OFFSET 0 + +#define PINCTRL_DOE0_DOE_MASK 0x1fffffff +#define PINCTRL_DOE0_DOE_OFFSET 0 + +#define PINCTRL_DOE1_DOE_MASK 0xffffffff +#define PINCTRL_DOE1_DOE_OFFSET 0 + +#define PINCTRL_DOE2_DOE_MASK 0xfffffff +#define PINCTRL_DOE2_DOE_OFFSET 0 + +#define PINCTRL_DOE3_DOE_MASK 0x7fffffff +#define PINCTRL_DOE3_DOE_OFFSET 0 + +#define PINCTRL_DOE4_DOE_MASK 0x1fffff +#define PINCTRL_DOE4_DOE_OFFSET 0 + +#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff +#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff +#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff +#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff +#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff +#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 + +#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff +#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff +#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff +#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff +#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff +#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 + +#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff +#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff +#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff +#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff +#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff +#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff +#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff +#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff +#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff +#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff +#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff +#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff +#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff +#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff +#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff +#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 + +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 + +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 + +#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h new file mode 100644 index 0000000..8eadc6d --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -0,0 +1,413 @@ +/* + * Freescale i.MX28 Power Controller Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_POWER_H__ +#define __MX28_REGS_POWER_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_power_regs { + mx28_reg_32(hw_power_ctrl) + mx28_reg_32(hw_power_5vctrl) + mx28_reg_32(hw_power_minpwr) + mx28_reg_32(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mx28_reg_32(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mx28_reg_32(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved[4]; + + mx28_reg_32(hw_power_reset) + mx28_reg_32(hw_power_debug) + mx28_reg_32(hw_power_thermal) + mx28_reg_32(hw_power_usb1ctrl) + mx28_reg_32(hw_power_special) + mx28_reg_32(hw_power_version) + mx28_reg_32(hw_power_anaclkctrl) + mx28_reg_32(hw_power_refctrl) +}; +#endif + +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_FBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define POWER_CHARGE_LIION_4P1 (1 << 18) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) +#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) +#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define POWER_STS_THERMAL_WARNING (1 << 19) +#define POWER_STS_VDDMEM_BO (1 << 18) +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define POWER_SPEED_STATUS_MASK (0xffff << 8) +#define POWER_SPEED_STATUS_OFFSET 8 +#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) +#define POWER_SPEED_STATUS_SEL_OFFSET 6 +#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) +#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) +#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define POWER_THERMAL_TEST (1 << 8) +#define POWER_THERMAL_PWD (1 << 7) +#define POWER_THERMAL_LOW_POWER (1 << 6) +#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) +#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 +#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 + +#define POWER_USB1CTRL_AVALID1 (1 << 3) +#define POWER_USB1CTRL_BVALID1 (1 << 2) +#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) +#define POWER_USB1CTRL_SESSEND1 (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) +#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 +#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) +#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) +#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) +#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) +#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) +#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 +#define POWER_ANACLKCTRL_INDIV_MASK 0x7 +#define POWER_ANACLKCTRL_INDIV_OFFSET 0 + +#define POWER_REFCTRL_FASTSETTLING (1 << 26) +#define POWER_REFCTRL_RAISE_REF (1 << 25) +#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) +#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 +#define POWER_REFCTRL_LOW_PWR (1 << 19) +#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) +#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 +#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) +#define POWER_REFCTRL_ADJ_ANA (1 << 13) +#define POWER_REFCTRL_ADJ_VAG (1 << 12) +#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) +#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 +#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) +#define POWER_REFCTRL_VAG_VAL_OFFSET 4 + +#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h new file mode 100644 index 0000000..e605a03 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h @@ -0,0 +1,147 @@ +/* + * Freescale i.MX28 RTC Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_RTC_H__ +#define __MX28_REGS_RTC_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_rtc_regs { + mx28_reg_32(hw_rtc_ctrl) + mx28_reg_32(hw_rtc_stat) + mx28_reg_32(hw_rtc_milliseconds) + mx28_reg_32(hw_rtc_seconds) + mx28_reg_32(hw_rtc_rtc_alarm) + mx28_reg_32(hw_rtc_watchdog) + mx28_reg_32(hw_rtc_persistent0) + mx28_reg_32(hw_rtc_persistent1) + mx28_reg_32(hw_rtc_persistent2) + mx28_reg_32(hw_rtc_persistent3) + mx28_reg_32(hw_rtc_persistent4) + mx28_reg_32(hw_rtc_persistent5) + mx28_reg_32(hw_rtc_debug) + mx28_reg_32(hw_rtc_version) +}; +#endif + +#define RTC_CTRL_SFTRST (1 << 31) +#define RTC_CTRL_CLKGATE (1 << 30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) +#define RTC_CTRL_FORCE_UPDATE (1 << 5) +#define RTC_CTRL_WATCHDOGEN (1 << 4) +#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) +#define RTC_CTRL_ALARM_IRQ (1 << 2) +#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) +#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) + +#define RTC_STAT_RTC_PRESENT (1 << 31) +#define RTC_STAT_ALARM_PRESENT (1 << 30) +#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) +#define RTC_STAT_XTAL32000_PRESENT (1 << 28) +#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_MASK (0xff << 16) +#define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_MASK (0xff << 8) +#define RTC_STAT_NEW_REGS_OFFSET 8 + +#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff +#define RTC_MILLISECONDS_COUNT_OFFSET 0 + +#define RTC_SECONDS_COUNT_MASK 0xffffffff +#define RTC_SECONDS_COUNT_OFFSET 0 + +#define RTC_ALARM_VALUE_MASK 0xffffffff +#define RTC_ALARM_VALUE_OFFSET 0 + +#define RTC_WATCHDOG_COUNT_MASK 0xffffffff +#define RTC_WATCHDOG_COUNT_OFFSET 0 + +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) +#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) +#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) +#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) +#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 +#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) +#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) +#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 +#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) +#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) +#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) +#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) +#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) +#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) +#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) +#define RTC_PERSISTENT0_LCK_SECS (1 << 3) +#define RTC_PERSISTENT0_ALARM_EN (1 << 2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) +#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) + +#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT1_GENERAL_OFFSET 0 +#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 +#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 +#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 +#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 +#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 +#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 + +#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT2_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT3_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT4_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT5_GENERAL_OFFSET 0 + +#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) +#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) + +#define RTC_VERSION_MAJOR_MASK (0xff << 24) +#define RTC_VERSION_MAJOR_OFFSET 24 +#define RTC_VERSION_MINOR_MASK (0xff << 16) +#define RTC_VERSION_MINOR_OFFSET 16 +#define RTC_VERSION_STEP_MASK 0xffff +#define RTC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h new file mode 100644 index 0000000..be71d48 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -0,0 +1,349 @@ +/* + * Freescale i.MX28 SSP Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_SSP_H__ +#define __MX28_REGS_SSP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ssp_regs { + mx28_reg_32(hw_ssp_ctrl0) + mx28_reg_32(hw_ssp_cmd0) + mx28_reg_32(hw_ssp_cmd1) + mx28_reg_32(hw_ssp_xfer_size) + mx28_reg_32(hw_ssp_block_size) + mx28_reg_32(hw_ssp_compref) + mx28_reg_32(hw_ssp_compmask) + mx28_reg_32(hw_ssp_timing) + mx28_reg_32(hw_ssp_ctrl1) + mx28_reg_32(hw_ssp_data) + mx28_reg_32(hw_ssp_sdresp0) + mx28_reg_32(hw_ssp_sdresp1) + mx28_reg_32(hw_ssp_sdresp2) + mx28_reg_32(hw_ssp_sdresp3) + mx28_reg_32(hw_ssp_ddr_ctrl) + mx28_reg_32(hw_ssp_dll_ctrl) + mx28_reg_32(hw_ssp_status) + mx28_reg_32(hw_ssp_dll_sts) + mx28_reg_32(hw_ssp_debug) + mx28_reg_32(hw_ssp_version) +}; +#endif + +#define SSP_CTRL0_SFTRST (1 << 31) +#define SSP_CTRL0_CLKGATE (1 << 30) +#define SSP_CTRL0_RUN (1 << 29) +#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define SSP_CTRL0_LOCK_CS (1 << 27) +#define SSP_CTRL0_IGNORE_CRC (1 << 26) +#define SSP_CTRL0_READ (1 << 25) +#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) +#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 +#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) +#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) +#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) +#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define SSP_CTRL0_LONG_RESP (1 << 19) +#define SSP_CTRL0_CHECK_RESP (1 << 18) +#define SSP_CTRL0_GET_RESP (1 << 17) +#define SSP_CTRL0_ENABLE (1 << 16) + +#define SSP_CMD0_SOFT_TERMINATE (1 << 26) +#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) +#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) +#define SSP_CMD0_BOOT_ACK_EN (1 << 23) +#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) +#define SSP_CMD0_CONT_CLKING_EN (1 << 21) +#define SSP_CMD0_APPEND_8CYC (1 << 20) +#define SSP_CMD0_CMD_MASK 0xff +#define SSP_CMD0_CMD_OFFSET 0 +#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 +#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 +#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 +#define SSP_CMD0_CMD_MMC_SWITCH 0x06 +#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 +#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 +#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a +#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b +#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e +#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 +#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 +#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a +#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_MMC_ERASE 0x26 +#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 +#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 +#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 +#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 +#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_SD_SET_DSR 0x04 +#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 +#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 +#define SSP_CMD0_CMD_SD_SEND_CID 0x0a +#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_SD_ERASE 0x26 +#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 +#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 +#define SSP_CMD0_CMD_SD_APP_CMD 0x37 +#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 + +#define SSP_CMD1_CMD_ARG_MASK 0xffffffff +#define SSP_CMD1_CMD_ARG_OFFSET 0 + +#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff +#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 + +#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) +#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 +#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf +#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 + +#define SSP_COMPREF_REFERENCE_MASK 0xffffffff +#define SSP_COMPREF_REFERENCE_OFFSET 0 + +#define SSP_COMPMASK_MASK_MASK 0xffffffff +#define SSP_COMPMASK_MASK_OFFSET 0 + +#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) +#define SSP_TIMING_TIMEOUT_OFFSET 16 +#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) +#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 +#define SSP_TIMING_CLOCK_RATE_MASK 0xff +#define SSP_TIMING_CLOCK_RATE_OFFSET 0 + +#define SSP_CTRL1_SDIO_IRQ (1 << 31) +#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) +#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) +#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) +#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) +#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) +#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) +#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) +#define SSP_CTRL1_DMA_ENABLE (1 << 13) +#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) +#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) +#define SSP_CTRL1_PHASE (1 << 10) +#define SSP_CTRL1_POLARITY (1 << 9) +#define SSP_CTRL1_SLAVE_MODE (1 << 8) +#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) +#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 +#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) +#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) +#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) +#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) +#define SSP_CTRL1_SSP_MODE_MASK 0xf +#define SSP_CTRL1_SSP_MODE_OFFSET 0 +#define SSP_CTRL1_SSP_MODE_SPI 0x0 +#define SSP_CTRL1_SSP_MODE_SSI 0x1 +#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 +#define SSP_CTRL1_SSP_MODE_MS 0x4 + +#define SSP_DATA_DATA_MASK 0xffffffff +#define SSP_DATA_DATA_OFFSET 0 + +#define SSP_SDRESP0_RESP0_MASK 0xffffffff +#define SSP_SDRESP0_RESP0_OFFSET 0 + +#define SSP_SDRESP1_RESP1_MASK 0xffffffff +#define SSP_SDRESP1_RESP1_OFFSET 0 + +#define SSP_SDRESP2_RESP2_MASK 0xffffffff +#define SSP_SDRESP2_RESP2_OFFSET 0 + +#define SSP_SDRESP3_RESP3_MASK 0xffffffff +#define SSP_SDRESP3_RESP3_OFFSET 0 + +#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) +#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 +#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) +#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) + +#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) +#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 +#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) +#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 +#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) +#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 +#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) +#define SSP_DLL_CTRL_RESET (1 << 1) +#define SSP_DLL_CTRL_ENABLE (1 << 0) + +#define SSP_STATUS_PRESENT (1 << 31) +#define SSP_STATUS_MS_PRESENT (1 << 30) +#define SSP_STATUS_SD_PRESENT (1 << 29) +#define SSP_STATUS_CARD_DETECT (1 << 28) +#define SSP_STATUS_DMABURST (1 << 22) +#define SSP_STATUS_DMASENSE (1 << 21) +#define SSP_STATUS_DMATERM (1 << 20) +#define SSP_STATUS_DMAREQ (1 << 19) +#define SSP_STATUS_DMAEND (1 << 18) +#define SSP_STATUS_SDIO_IRQ (1 << 17) +#define SSP_STATUS_RESP_CRC_ERR (1 << 16) +#define SSP_STATUS_RESP_ERR (1 << 15) +#define SSP_STATUS_RESP_TIMEOUT (1 << 14) +#define SSP_STATUS_DATA_CRC_ERR (1 << 13) +#define SSP_STATUS_TIMEOUT (1 << 12) +#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) +#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) +#define SSP_STATUS_FIFO_OVRFLW (1 << 9) +#define SSP_STATUS_FIFO_FULL (1 << 8) +#define SSP_STATUS_FIFO_EMPTY (1 << 5) +#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) +#define SSP_STATUS_CMD_BUSY (1 << 3) +#define SSP_STATUS_DATA_BUSY (1 << 2) +#define SSP_STATUS_BUSY (1 << 0) + +#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) +#define SSP_DLL_STS_REF_SEL_OFFSET 8 +#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) +#define SSP_DLL_STS_SLV_SEL_OFFSET 2 +#define SSP_DLL_STS_REF_LOCK (1 << 1) +#define SSP_DLL_STS_SLV_LOCK (1 << 0) + +#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) +#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 +#define SSP_DEBUG_DATA_STALL (1 << 27) +#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) +#define SSP_DEBUG_DAT_SM_OFFSET 24 +#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) +#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) +#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) +#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) +#define SSP_DEBUG_MSTK_SM_OFFSET 20 +#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) +#define SSP_DEBUG_CMD_OE (1 << 19) +#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) +#define SSP_DEBUG_DMA_SM_OFFSET 16 +#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) +#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) +#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) +#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) +#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) +#define SSP_DEBUG_MMC_SM_OFFSET 12 +#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) +#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) +#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) +#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) +#define SSP_DEBUG_CMD_SM_OFFSET 10 +#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) +#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) +#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) +#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) +#define SSP_DEBUG_SSP_CMD (1 << 9) +#define SSP_DEBUG_SSP_RESP (1 << 8) +#define SSP_DEBUG_SSP_RXD_MASK 0xff +#define SSP_DEBUG_SSP_RXD_OFFSET 0 + +#define SSP_VERSION_MAJOR_MASK (0xff << 24) +#define SSP_VERSION_MAJOR_OFFSET 24 +#define SSP_VERSION_MINOR_MASK (0xff << 16) +#define SSP_VERSION_MINOR_OFFSET 16 +#define SSP_VERSION_STEP_MASK 0xffff +#define SSP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h new file mode 100644 index 0000000..3e8dfe7 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -0,0 +1,171 @@ +/* + * Freescale i.MX28 TIMROT Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_TIMROT_H__ +#define __MX28_REGS_TIMROT_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_timrot_regs { + mx28_reg_32(hw_timrot_rotctrl) + mx28_reg_32(hw_timrot_rotcount) + mx28_reg_32(hw_timrot_timctrl0) + mx28_reg_32(hw_timrot_running_count0) + mx28_reg_32(hw_timrot_fixed_count0) + mx28_reg_32(hw_timrot_match_count0) + mx28_reg_32(hw_timrot_timctrl1) + mx28_reg_32(hw_timrot_running_count1) + mx28_reg_32(hw_timrot_fixed_count1) + mx28_reg_32(hw_timrot_match_count1) + mx28_reg_32(hw_timrot_timctrl2) + mx28_reg_32(hw_timrot_running_count2) + mx28_reg_32(hw_timrot_fixed_count2) + mx28_reg_32(hw_timrot_match_count2) + mx28_reg_32(hw_timrot_timctrl3) + mx28_reg_32(hw_timrot_running_count3) + mx28_reg_32(hw_timrot_fixed_count3) + mx28_reg_32(hw_timrot_match_count3) + mx28_reg_32(hw_timrot_version) +}; +#endif + +#define TIMROT_ROTCTRL_SFTRST (1 << 31) +#define TIMROT_ROTCTRL_CLKGATE (1 << 30) +#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) +#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) +#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) +#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) +#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) +#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) +#define TIMROT_ROTCTRL_STATE_OFFSET 22 +#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) +#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 +#define TIMROT_ROTCTRL_RELATIVE (1 << 12) +#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 +#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) +#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) +#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 +#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 +#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 +#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 +#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 +#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 +#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 +#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 +#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 +#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa + +#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff +#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 + +#define TIMROT_TIMCTRLn_IRQ (1 << 15) +#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#define TIMROT_TIMCTRLn_POLARITY (1 << 8) +#define TIMROT_TIMCTRLn_UPDATE (1 << 7) +#define TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRLn_SELECT_MASK 0xf +#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 +#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 +#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 +#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf + +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 + +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 + +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 + +#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 +#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) + +#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) +#define TIMROT_VERSION_MAJOR_OFFSET 24 +#define TIMROT_VERSION_MINOR_MASK (0xff << 16) +#define TIMROT_VERSION_MINOR_OFFSET 16 +#define TIMROT_VERSION_STEP_MASK 0xffff +#define TIMROT_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usb.h b/arch/arm/include/asm/arch-mxs/regs-usb.h new file mode 100644 index 0000000..ea61de8 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-usb.h @@ -0,0 +1,178 @@ +/* + * Freescale i.MX28 USB OTG Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USB_H__ +#define __REGS_USB_H__ + +struct mx28_usb_regs { + uint32_t hw_usbctrl_id; /* 0x000 */ + uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ + uint32_t hw_usbctrl_hwhost; /* 0x008 */ + uint32_t hw_usbctrl_hwdevice; /* 0x00c */ + uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ + uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ + + uint32_t reserved1[26]; + + uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ + uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ + uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ + uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ + uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ + + uint32_t reserved2[27]; + + uint32_t hw_usbctrl_caplength; /* 0x100 */ + uint32_t hw_usbctrl_hcsparams; /* 0x104 */ + uint32_t hw_usbctrl_hccparams; /* 0x108 */ + + uint32_t reserved3[5]; + + uint32_t hw_usbctrl_dciversion; /* 0x120 */ + uint32_t hw_usbctrl_dccparams; /* 0x124 */ + + uint32_t reserved4[6]; + + uint32_t hw_usbctrl_usbcmd; /* 0x140 */ + uint32_t hw_usbctrl_usbsts; /* 0x144 */ + uint32_t hw_usbctrl_usbintr; /* 0x148 */ + uint32_t hw_usbctrl_frindex; /* 0x14c */ + + uint32_t reserved5; + + union { + uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ + uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ + }; + union { + uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ + uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ + }; + + uint32_t hw_usbctrl_ttctrl; /* 0x15c */ + uint32_t hw_usbctrl_burstsize; /* 0x160 */ + uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ + + uint32_t reserved6; + + uint32_t hw_usbctrl_ic_usb; /* 0x16c */ + uint32_t hw_usbctrl_ulpi; /* 0x170 */ + + uint32_t reserved7; + + uint32_t hw_usbctrl_endptnak; /* 0x178 */ + uint32_t hw_usbctrl_endptnaken; /* 0x17c */ + + uint32_t reserved8; + + uint32_t hw_usbctrl_portsc1; /* 0x184 */ + + uint32_t reserved9[7]; + + uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ + uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ + uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ + uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ + uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ + uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ + uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ + uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ + uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ + uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ + uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ + uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ + uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ + uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ + uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ +}; + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) + +#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 +#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) +#define HW_USBCTRL_ID_VERSION_OFFSET 25 +#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) +#define HW_USBCTRL_ID_REVISION_OFFSET 21 +#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) +#define HW_USBCTRL_ID_TAG_OFFSET 16 +#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) +#define HW_USBCTRL_ID_NID_OFFSET 8 +#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) +#define HW_USBCTRL_ID_ID_OFFSET 0 +#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) + +#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 +#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) +#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 +#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) +#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 +#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) +#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) +#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 +#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) +#define HW_USBCTRL_HWGENERAL_RT (1 << 0) + +#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 +#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) +#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 +#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) +#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 +#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) +#define HW_USBCTRL_HWHOST_HC (1 << 0) + +#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 +#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) +#define HW_USBCTRL_HWDEVICE_DC (1 << 0) + +#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) +#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 +#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) +#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 +#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 +#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff + +#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 +#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 +#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff + +#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 +#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff + +#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) +#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) +#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff + +#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 + +#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h new file mode 100644 index 0000000..0291d81 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-usbphy.h @@ -0,0 +1,151 @@ +/* + * Freescale i.MX28 USB PHY Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +struct mx28_usbphy_regs { + mx28_reg_32(hw_usbphy_pwd) + mx28_reg_32(hw_usbphy_tx) + mx28_reg_32(hw_usbphy_rx) + mx28_reg_32(hw_usbphy_ctrl) + mx28_reg_32(hw_usbphy_status) + mx28_reg_32(hw_usbphy_debug) + mx28_reg_32(hw_usbphy_debug0_status) + mx28_reg_32(hw_usbphy_debug1) + mx28_reg_32(hw_usbphy_version) + mx28_reg_32(hw_usbphy_ip) +}; + +#define USBPHY_PWD_RXPWDRX (1 << 20) +#define USBPHY_PWD_RXPWDDIFF (1 << 19) +#define USBPHY_PWD_RXPWD1PT1 (1 << 18) +#define USBPHY_PWD_RXPWDENV (1 << 17) +#define USBPHY_PWD_TXPWDV2I (1 << 12) +#define USBPHY_PWD_TXPWDIBIAS (1 << 11) +#define USBPHY_PWD_TXPWDFS (1 << 10) + +#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) +#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) +#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) +#define USBPHY_TX_TXENCAL45DP (1 << 21) +#define USBPHY_TX_TXCAL45DP_OFFSET 16 +#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) +#define USBPHY_TX_TXENCAL45DM (1 << 13) +#define USBPHY_TX_TXCAL45DM_OFFSET 8 +#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) +#define USBPHY_TX_D_CAL_OFFSET 0 +#define USBPHY_TX_D_CAL_MASK 0xf + +#define USBPHY_RX_RXDBYPASS (1 << 22) +#define USBPHY_RX_DISCONADJ_OFFSET 4 +#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) +#define USBPHY_RX_ENVADJ_OFFSET 0 +#define USBPHY_RX_ENVADJ_MASK 0x7 + +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) +#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) +#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) +#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) +#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) +#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) +#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) +#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) +#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) +#define USBPHY_CTRL_RESUME_IRQ (1 << 10) +#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) +#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) +#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) +#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) +#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) +#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) + +#define USBPHY_STATUS_RESUME_STATUS (1 << 10) +#define USBPHY_STATUS_OTGID_STATUS (1 << 8) +#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) + +#define USBPHY_DEBUG_CLKGATE (1 << 30) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) +#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) +#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) +#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) +#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) +#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) +#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) + +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff + +#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) +#define USBPHY_DEBUG1_ENTX2TX (1 << 12) +#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 +#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf + +#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) +#define USBPHY_VERSION_MAJOR_OFFSET 24 +#define USBPHY_VERSION_MINOR_MASK (0xff << 16) +#define USBPHY_VERSION_MINOR_OFFSET 16 +#define USBPHY_VERSION_STEP_MASK 0xffff +#define USBPHY_VERSION_STEP_OFFSET 0 + +#define USBPHY_IP_DIV_SEL_OFFSET 23 +#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) +#define USBPHY_IP_LFR_SEL_OFFSET 21 +#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) +#define USBPHY_IP_CP_SEL_OFFSET 19 +#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) +#define USBPHY_IP_TSTI_TX_DP (1 << 18) +#define USBPHY_IP_TSTI_TX_DM (1 << 17) +#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) +#define USBPHY_IP_EN_USB_CLKS (1 << 2) +#define USBPHY_IP_PLL_LOCKED (1 << 1) +#define USBPHY_IP_PLL_POWER (1 << 0) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h new file mode 100644 index 0000000..e701c64 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -0,0 +1,74 @@ +/* + * Freescale i.MX28 MX28 specific functions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_H__ +#define __MX28_H__ + +int mx28_reset_block(struct mx28_register_32 *reg); +int mx28_wait_mask_set(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); +int mx28_wait_mask_clr(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); + +int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/iomux-mx28.h> +void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size); +#endif + +struct mx28_pair { + uint8_t boot_pads; + uint8_t boot_mask; + const char *mode; +}; + +static const struct mx28_pair mx28_boot_modes[] = { + { 0x00, 0x0f, "USB #0" }, + { 0x01, 0x1f, "I2C #0, master, 3V3" }, + { 0x11, 0x1f, "I2C #0, master, 1V8" }, + { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, + { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, + { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, + { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, + { 0x04, 0x1f, "NAND, 3V3" }, + { 0x14, 0x1f, "NAND, 1V8" }, + { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, + { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, + { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, + { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, + { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, + { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, +}; + +struct mx28_spl_data { + uint8_t boot_mode_idx; + uint32_t mem_dram_size; +}; + +int mx28_dram_init(void); + +#endif /* __MX28_H__ */ diff --git a/boards.cfg b/boards.cfg index 6c24697..91ce997 100644 --- a/boards.cfg +++ b/boards.cfg @@ -163,8 +163,8 @@ tx25 arm arm926ejs tx25 karo zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 -m28evk arm arm926ejs - denx mx28 -mx28evk arm arm926ejs - freescale mx28 +m28evk arm arm926ejs - denx mxs m28evk +mx28evk arm arm926ejs - freescale mxs mx28evk nhk8815 arm arm926ejs nhk8815 st nomadik nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND omap5912osk arm arm926ejs - ti omap diff --git a/doc/README.m28 b/doc/README.m28 index 7dee8ce..7f13e63 100644 --- a/doc/README.m28 +++ b/doc/README.m28 @@ -4,7 +4,7 @@ DENX M28EVK Files of the M28/M28EVK port ----------------------------

-arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28 +arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28 board/denx/m28evk/ - M28EVK board specific files include/configs/m28evk.h - M28EVK configuration file diff --git a/doc/README.mx28evk b/doc/README.mx28evk index c6c3d37..8b10135 100644 --- a/doc/README.mx28evk +++ b/doc/README.mx28evk @@ -6,10 +6,10 @@ Supported hardware: only MX28EVK rev D is supported in U-boot. Files of the MX28EVK port --------------------------

-arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28 +arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28 -board/freescale/mx28evk/ - MX28EVK board specific files -include/configs/mx28evk.h - MX28EVK configuration file +board/freescale/mxsevk/ - MX28EVK board specific files +include/configs/mxsevk.h - MX28EVK configuration file

Jumper configuration --------------------- diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index ebf7e39..53b3954 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -50,8 +50,8 @@ */ #define CONFIG_SPL #define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 5ccfe70..37d58f6 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -42,8 +42,8 @@ */ #define CONFIG_SPL #define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT

-- 1.7.10

Otavio Salvador

5:51 p.m.

New subject: [U-Boot] [PATCH 6/8] mxs: reorganize source directory for easy sharing of code among i.MXS SoCs

On Fri, May 11, 2012 at 12:38 PM, Otavio Salvador otavio@ossystems.com.br wrote:

...

Most code can be shared amount i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br

This and next patches are not yet ready for merging but I'd like to get an review on the concept of it.

-- Otavio Salvador O.S. Systems E-mail: otavio@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 7/8] mxs: prefix register acessor macros with 'mxs' prefix

As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- arch/arm/cpu/arm926ejs/mxs/clock.c | 4 +- arch/arm/cpu/arm926ejs/mxs/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mxs/mx28.c | 6 +- arch/arm/include/asm/arch-mxs/regs-apbh.h | 254 +++++++++++++------------- arch/arm/include/asm/arch-mxs/regs-bch.h | 42 ++--- arch/arm/include/asm/arch-mxs/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mxs/regs-common.h | 34 ++-- arch/arm/include/asm/arch-mxs/regs-digctl.h | 50 ++--- arch/arm/include/asm/arch-mxs/regs-gpmi.h | 26 +-- arch/arm/include/asm/arch-mxs/regs-i2c.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-ocotp.h | 86 ++++----- arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 168 ++++++++--------- arch/arm/include/asm/arch-mxs/regs-power.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-rtc.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mxs/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mxs/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mxs/sys_proto.h | 6 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 20 files changed, 473 insertions(+), 473 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 0439f9c..3e29c56 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -207,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) return;

clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32));

clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) @@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) return XTAL_FREQ_KHZ;

clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32));

tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;

diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 12916b6..73f1446 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) { u32 reg, ofs, bp, bm; void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register_32 *mxs_reg; + struct mxs_register_32 *mxs_reg;

/* muxsel */ ofs = 0x100; @@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) /* vol */ if (PAD_VOL_VALID(pad)) { bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_VOL(pad)) writel(1 << bp, &mxs_reg->reg_set); else @@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs = PULL_OFFSET; ofs += PAD_BANK(pad) * 0x10; bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_PULL(pad)) writel(1 << bp, &mxs_reg->reg_set); else diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c b/arch/arm/cpu/arm926ejs/mxs/mx28.c index a82ff25..a0ec06e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mx28.c +++ b/arch/arm/cpu/arm926ejs/mxs/mx28.c @@ -81,7 +81,7 @@ void enable_caches(void) #endif }

-int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(&reg->reg) & mask) == mask) @@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; }

-int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(&reg->reg) & mask) == 0) @@ -103,7 +103,7 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; }

-int mx28_reset_block(struct mx28_register_32 *reg) +int mx28_reset_block(struct mxs_register_32 *reg) { /* Clear SFTRST */ writel(MX28_BLOCK_SFTRST, &reg->reg_clr); diff --git a/arch/arm/include/asm/arch-mxs/regs-apbh.h b/arch/arm/include/asm/arch-mxs/regs-apbh.h index 91d7bc8..7c6bd04 100644 --- a/arch/arm/include/asm/arch-mxs/regs-apbh.h +++ b/arch/arm/include/asm/arch-mxs/regs-apbh.h @@ -30,142 +30,142 @@

#ifndef __ASSEMBLY__ struct mx28_apbh_regs { - mx28_reg_32(hw_apbh_ctrl0) - mx28_reg_32(hw_apbh_ctrl1) - mx28_reg_32(hw_apbh_ctrl2) - mx28_reg_32(hw_apbh_channel_ctrl) - mx28_reg_32(hw_apbh_devsel) - mx28_reg_32(hw_apbh_dma_burst_size) - mx28_reg_32(hw_apbh_debug) + mxs_reg_32(hw_apbh_ctrl0) + mxs_reg_32(hw_apbh_ctrl1) + mxs_reg_32(hw_apbh_ctrl2) + mxs_reg_32(hw_apbh_channel_ctrl) + mxs_reg_32(hw_apbh_devsel) + mxs_reg_32(hw_apbh_dma_burst_size) + mxs_reg_32(hw_apbh_debug)

uint32_t reserved[36];

union { struct { - mx28_reg_32(hw_apbh_ch_curcmdar) - mx28_reg_32(hw_apbh_ch_nxtcmdar) - mx28_reg_32(hw_apbh_ch_cmd) - mx28_reg_32(hw_apbh_ch_bar) - mx28_reg_32(hw_apbh_ch_sema) - mx28_reg_32(hw_apbh_ch_debug1) - mx28_reg_32(hw_apbh_ch_debug2) + mxs_reg_32(hw_apbh_ch_curcmdar) + mxs_reg_32(hw_apbh_ch_nxtcmdar) + mxs_reg_32(hw_apbh_ch_cmd) + mxs_reg_32(hw_apbh_ch_bar) + mxs_reg_32(hw_apbh_ch_sema) + mxs_reg_32(hw_apbh_ch_debug1) + mxs_reg_32(hw_apbh_ch_debug2) } ch[16]; struct { - mx28_reg_32(hw_apbh_ch0_curcmdar) - mx28_reg_32(hw_apbh_ch0_nxtcmdar) - mx28_reg_32(hw_apbh_ch0_cmd) - mx28_reg_32(hw_apbh_ch0_bar) - mx28_reg_32(hw_apbh_ch0_sema) - mx28_reg_32(hw_apbh_ch0_debug1) - mx28_reg_32(hw_apbh_ch0_debug2) - mx28_reg_32(hw_apbh_ch1_curcmdar) - mx28_reg_32(hw_apbh_ch1_nxtcmdar) - mx28_reg_32(hw_apbh_ch1_cmd) - mx28_reg_32(hw_apbh_ch1_bar) - mx28_reg_32(hw_apbh_ch1_sema) - mx28_reg_32(hw_apbh_ch1_debug1) - mx28_reg_32(hw_apbh_ch1_debug2) - mx28_reg_32(hw_apbh_ch2_curcmdar) - mx28_reg_32(hw_apbh_ch2_nxtcmdar) - mx28_reg_32(hw_apbh_ch2_cmd) - mx28_reg_32(hw_apbh_ch2_bar) - mx28_reg_32(hw_apbh_ch2_sema) - mx28_reg_32(hw_apbh_ch2_debug1) - mx28_reg_32(hw_apbh_ch2_debug2) - mx28_reg_32(hw_apbh_ch3_curcmdar) - mx28_reg_32(hw_apbh_ch3_nxtcmdar) - mx28_reg_32(hw_apbh_ch3_cmd) - mx28_reg_32(hw_apbh_ch3_bar) - mx28_reg_32(hw_apbh_ch3_sema) - mx28_reg_32(hw_apbh_ch3_debug1) - mx28_reg_32(hw_apbh_ch3_debug2) - mx28_reg_32(hw_apbh_ch4_curcmdar) - mx28_reg_32(hw_apbh_ch4_nxtcmdar) - mx28_reg_32(hw_apbh_ch4_cmd) - mx28_reg_32(hw_apbh_ch4_bar) - mx28_reg_32(hw_apbh_ch4_sema) - mx28_reg_32(hw_apbh_ch4_debug1) - mx28_reg_32(hw_apbh_ch4_debug2) - mx28_reg_32(hw_apbh_ch5_curcmdar) - mx28_reg_32(hw_apbh_ch5_nxtcmdar) - mx28_reg_32(hw_apbh_ch5_cmd) - mx28_reg_32(hw_apbh_ch5_bar) - mx28_reg_32(hw_apbh_ch5_sema) - mx28_reg_32(hw_apbh_ch5_debug1) - mx28_reg_32(hw_apbh_ch5_debug2) - mx28_reg_32(hw_apbh_ch6_curcmdar) - mx28_reg_32(hw_apbh_ch6_nxtcmdar) - mx28_reg_32(hw_apbh_ch6_cmd) - mx28_reg_32(hw_apbh_ch6_bar) - mx28_reg_32(hw_apbh_ch6_sema) - mx28_reg_32(hw_apbh_ch6_debug1) - mx28_reg_32(hw_apbh_ch6_debug2) - mx28_reg_32(hw_apbh_ch7_curcmdar) - mx28_reg_32(hw_apbh_ch7_nxtcmdar) - mx28_reg_32(hw_apbh_ch7_cmd) - mx28_reg_32(hw_apbh_ch7_bar) - mx28_reg_32(hw_apbh_ch7_sema) - mx28_reg_32(hw_apbh_ch7_debug1) - mx28_reg_32(hw_apbh_ch7_debug2) - mx28_reg_32(hw_apbh_ch8_curcmdar) - mx28_reg_32(hw_apbh_ch8_nxtcmdar) - mx28_reg_32(hw_apbh_ch8_cmd) - mx28_reg_32(hw_apbh_ch8_bar) - mx28_reg_32(hw_apbh_ch8_sema) - mx28_reg_32(hw_apbh_ch8_debug1) - mx28_reg_32(hw_apbh_ch8_debug2) - mx28_reg_32(hw_apbh_ch9_curcmdar) - mx28_reg_32(hw_apbh_ch9_nxtcmdar) - mx28_reg_32(hw_apbh_ch9_cmd) - mx28_reg_32(hw_apbh_ch9_bar) - mx28_reg_32(hw_apbh_ch9_sema) - mx28_reg_32(hw_apbh_ch9_debug1) - mx28_reg_32(hw_apbh_ch9_debug2) - mx28_reg_32(hw_apbh_ch10_curcmdar) - mx28_reg_32(hw_apbh_ch10_nxtcmdar) - mx28_reg_32(hw_apbh_ch10_cmd) - mx28_reg_32(hw_apbh_ch10_bar) - mx28_reg_32(hw_apbh_ch10_sema) - mx28_reg_32(hw_apbh_ch10_debug1) - mx28_reg_32(hw_apbh_ch10_debug2) - mx28_reg_32(hw_apbh_ch11_curcmdar) - mx28_reg_32(hw_apbh_ch11_nxtcmdar) - mx28_reg_32(hw_apbh_ch11_cmd) - mx28_reg_32(hw_apbh_ch11_bar) - mx28_reg_32(hw_apbh_ch11_sema) - mx28_reg_32(hw_apbh_ch11_debug1) - mx28_reg_32(hw_apbh_ch11_debug2) - mx28_reg_32(hw_apbh_ch12_curcmdar) - mx28_reg_32(hw_apbh_ch12_nxtcmdar) - mx28_reg_32(hw_apbh_ch12_cmd) - mx28_reg_32(hw_apbh_ch12_bar) - mx28_reg_32(hw_apbh_ch12_sema) - mx28_reg_32(hw_apbh_ch12_debug1) - mx28_reg_32(hw_apbh_ch12_debug2) - mx28_reg_32(hw_apbh_ch13_curcmdar) - mx28_reg_32(hw_apbh_ch13_nxtcmdar) - mx28_reg_32(hw_apbh_ch13_cmd) - mx28_reg_32(hw_apbh_ch13_bar) - mx28_reg_32(hw_apbh_ch13_sema) - mx28_reg_32(hw_apbh_ch13_debug1) - mx28_reg_32(hw_apbh_ch13_debug2) - mx28_reg_32(hw_apbh_ch14_curcmdar) - mx28_reg_32(hw_apbh_ch14_nxtcmdar) - mx28_reg_32(hw_apbh_ch14_cmd) - mx28_reg_32(hw_apbh_ch14_bar) - mx28_reg_32(hw_apbh_ch14_sema) - mx28_reg_32(hw_apbh_ch14_debug1) - mx28_reg_32(hw_apbh_ch14_debug2) - mx28_reg_32(hw_apbh_ch15_curcmdar) - mx28_reg_32(hw_apbh_ch15_nxtcmdar) - mx28_reg_32(hw_apbh_ch15_cmd) - mx28_reg_32(hw_apbh_ch15_bar) - mx28_reg_32(hw_apbh_ch15_sema) - mx28_reg_32(hw_apbh_ch15_debug1) - mx28_reg_32(hw_apbh_ch15_debug2) + mxs_reg_32(hw_apbh_ch0_curcmdar) + mxs_reg_32(hw_apbh_ch0_nxtcmdar) + mxs_reg_32(hw_apbh_ch0_cmd) + mxs_reg_32(hw_apbh_ch0_bar) + mxs_reg_32(hw_apbh_ch0_sema) + mxs_reg_32(hw_apbh_ch0_debug1) + mxs_reg_32(hw_apbh_ch0_debug2) + mxs_reg_32(hw_apbh_ch1_curcmdar) + mxs_reg_32(hw_apbh_ch1_nxtcmdar) + mxs_reg_32(hw_apbh_ch1_cmd) + mxs_reg_32(hw_apbh_ch1_bar) + mxs_reg_32(hw_apbh_ch1_sema) + mxs_reg_32(hw_apbh_ch1_debug1) + mxs_reg_32(hw_apbh_ch1_debug2) + mxs_reg_32(hw_apbh_ch2_curcmdar) + mxs_reg_32(hw_apbh_ch2_nxtcmdar) + mxs_reg_32(hw_apbh_ch2_cmd) + mxs_reg_32(hw_apbh_ch2_bar) + mxs_reg_32(hw_apbh_ch2_sema) + mxs_reg_32(hw_apbh_ch2_debug1) + mxs_reg_32(hw_apbh_ch2_debug2) + mxs_reg_32(hw_apbh_ch3_curcmdar) + mxs_reg_32(hw_apbh_ch3_nxtcmdar) + mxs_reg_32(hw_apbh_ch3_cmd) + mxs_reg_32(hw_apbh_ch3_bar) + mxs_reg_32(hw_apbh_ch3_sema) + mxs_reg_32(hw_apbh_ch3_debug1) + mxs_reg_32(hw_apbh_ch3_debug2) + mxs_reg_32(hw_apbh_ch4_curcmdar) + mxs_reg_32(hw_apbh_ch4_nxtcmdar) + mxs_reg_32(hw_apbh_ch4_cmd) + mxs_reg_32(hw_apbh_ch4_bar) + mxs_reg_32(hw_apbh_ch4_sema) + mxs_reg_32(hw_apbh_ch4_debug1) + mxs_reg_32(hw_apbh_ch4_debug2) + mxs_reg_32(hw_apbh_ch5_curcmdar) + mxs_reg_32(hw_apbh_ch5_nxtcmdar) + mxs_reg_32(hw_apbh_ch5_cmd) + mxs_reg_32(hw_apbh_ch5_bar) + mxs_reg_32(hw_apbh_ch5_sema) + mxs_reg_32(hw_apbh_ch5_debug1) + mxs_reg_32(hw_apbh_ch5_debug2) + mxs_reg_32(hw_apbh_ch6_curcmdar) + mxs_reg_32(hw_apbh_ch6_nxtcmdar) + mxs_reg_32(hw_apbh_ch6_cmd) + mxs_reg_32(hw_apbh_ch6_bar) + mxs_reg_32(hw_apbh_ch6_sema) + mxs_reg_32(hw_apbh_ch6_debug1) + mxs_reg_32(hw_apbh_ch6_debug2) + mxs_reg_32(hw_apbh_ch7_curcmdar) + mxs_reg_32(hw_apbh_ch7_nxtcmdar) + mxs_reg_32(hw_apbh_ch7_cmd) + mxs_reg_32(hw_apbh_ch7_bar) + mxs_reg_32(hw_apbh_ch7_sema) + mxs_reg_32(hw_apbh_ch7_debug1) + mxs_reg_32(hw_apbh_ch7_debug2) + mxs_reg_32(hw_apbh_ch8_curcmdar) + mxs_reg_32(hw_apbh_ch8_nxtcmdar) + mxs_reg_32(hw_apbh_ch8_cmd) + mxs_reg_32(hw_apbh_ch8_bar) + mxs_reg_32(hw_apbh_ch8_sema) + mxs_reg_32(hw_apbh_ch8_debug1) + mxs_reg_32(hw_apbh_ch8_debug2) + mxs_reg_32(hw_apbh_ch9_curcmdar) + mxs_reg_32(hw_apbh_ch9_nxtcmdar) + mxs_reg_32(hw_apbh_ch9_cmd) + mxs_reg_32(hw_apbh_ch9_bar) + mxs_reg_32(hw_apbh_ch9_sema) + mxs_reg_32(hw_apbh_ch9_debug1) + mxs_reg_32(hw_apbh_ch9_debug2) + mxs_reg_32(hw_apbh_ch10_curcmdar) + mxs_reg_32(hw_apbh_ch10_nxtcmdar) + mxs_reg_32(hw_apbh_ch10_cmd) + mxs_reg_32(hw_apbh_ch10_bar) + mxs_reg_32(hw_apbh_ch10_sema) + mxs_reg_32(hw_apbh_ch10_debug1) + mxs_reg_32(hw_apbh_ch10_debug2) + mxs_reg_32(hw_apbh_ch11_curcmdar) + mxs_reg_32(hw_apbh_ch11_nxtcmdar) + mxs_reg_32(hw_apbh_ch11_cmd) + mxs_reg_32(hw_apbh_ch11_bar) + mxs_reg_32(hw_apbh_ch11_sema) + mxs_reg_32(hw_apbh_ch11_debug1) + mxs_reg_32(hw_apbh_ch11_debug2) + mxs_reg_32(hw_apbh_ch12_curcmdar) + mxs_reg_32(hw_apbh_ch12_nxtcmdar) + mxs_reg_32(hw_apbh_ch12_cmd) + mxs_reg_32(hw_apbh_ch12_bar) + mxs_reg_32(hw_apbh_ch12_sema) + mxs_reg_32(hw_apbh_ch12_debug1) + mxs_reg_32(hw_apbh_ch12_debug2) + mxs_reg_32(hw_apbh_ch13_curcmdar) + mxs_reg_32(hw_apbh_ch13_nxtcmdar) + mxs_reg_32(hw_apbh_ch13_cmd) + mxs_reg_32(hw_apbh_ch13_bar) + mxs_reg_32(hw_apbh_ch13_sema) + mxs_reg_32(hw_apbh_ch13_debug1) + mxs_reg_32(hw_apbh_ch13_debug2) + mxs_reg_32(hw_apbh_ch14_curcmdar) + mxs_reg_32(hw_apbh_ch14_nxtcmdar) + mxs_reg_32(hw_apbh_ch14_cmd) + mxs_reg_32(hw_apbh_ch14_bar) + mxs_reg_32(hw_apbh_ch14_sema) + mxs_reg_32(hw_apbh_ch14_debug1) + mxs_reg_32(hw_apbh_ch14_debug2) + mxs_reg_32(hw_apbh_ch15_curcmdar) + mxs_reg_32(hw_apbh_ch15_nxtcmdar) + mxs_reg_32(hw_apbh_ch15_cmd) + mxs_reg_32(hw_apbh_ch15_bar) + mxs_reg_32(hw_apbh_ch15_sema) + mxs_reg_32(hw_apbh_ch15_debug1) + mxs_reg_32(hw_apbh_ch15_debug2) }; }; - mx28_reg_32(hw_apbh_version) + mxs_reg_32(hw_apbh_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-bch.h b/arch/arm/include/asm/arch-mxs/regs-bch.h index 9243bdd..58517c4 100644 --- a/arch/arm/include/asm/arch-mxs/regs-bch.h +++ b/arch/arm/include/asm/arch-mxs/regs-bch.h @@ -30,30 +30,30 @@

#ifndef __ASSEMBLY__ struct mx28_bch_regs { - mx28_reg_32(hw_bch_ctrl) - mx28_reg_32(hw_bch_status0) - mx28_reg_32(hw_bch_mode) - mx28_reg_32(hw_bch_encodeptr) - mx28_reg_32(hw_bch_dataptr) - mx28_reg_32(hw_bch_metaptr) + mxs_reg_32(hw_bch_ctrl) + mxs_reg_32(hw_bch_status0) + mxs_reg_32(hw_bch_mode) + mxs_reg_32(hw_bch_encodeptr) + mxs_reg_32(hw_bch_dataptr) + mxs_reg_32(hw_bch_metaptr)

uint32_t reserved[4];

- mx28_reg_32(hw_bch_layoutselect) - mx28_reg_32(hw_bch_flash0layout0) - mx28_reg_32(hw_bch_flash0layout1) - mx28_reg_32(hw_bch_flash1layout0) - mx28_reg_32(hw_bch_flash1layout1) - mx28_reg_32(hw_bch_flash2layout0) - mx28_reg_32(hw_bch_flash2layout1) - mx28_reg_32(hw_bch_flash3layout0) - mx28_reg_32(hw_bch_flash3layout1) - mx28_reg_32(hw_bch_dbgkesread) - mx28_reg_32(hw_bch_dbgcsferead) - mx28_reg_32(hw_bch_dbgsyndegread) - mx28_reg_32(hw_bch_dbgahbmread) - mx28_reg_32(hw_bch_blockname) - mx28_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_layoutselect) + mxs_reg_32(hw_bch_flash0layout0) + mxs_reg_32(hw_bch_flash0layout1) + mxs_reg_32(hw_bch_flash1layout0) + mxs_reg_32(hw_bch_flash1layout1) + mxs_reg_32(hw_bch_flash2layout0) + mxs_reg_32(hw_bch_flash2layout1) + mxs_reg_32(hw_bch_flash3layout0) + mxs_reg_32(hw_bch_flash3layout1) + mxs_reg_32(hw_bch_dbgkesread) + mxs_reg_32(hw_bch_dbgcsferead) + mxs_reg_32(hw_bch_dbgsyndegread) + mxs_reg_32(hw_bch_dbgahbmread) + mxs_reg_32(hw_bch_blockname) + mxs_reg_32(hw_bch_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl.h index 3c4947d..127370b 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl.h @@ -30,38 +30,38 @@

#ifndef __ASSEMBLY__ struct mx28_clkctrl_regs { - mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ - mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ - mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mx28_reg_32(hw_clkctrl_etm) /* 0x130 */ - mx28_reg_32(hw_clkctrl_enet) /* 0x140 */ - mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ + mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ + mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */

uint32_t reserved[16];

- mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mx28_reg_32(hw_clkctrl_version) /* 0x200 */ + mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mxs_reg_32(hw_clkctrl_version) /* 0x200 */ }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-common.h b/arch/arm/include/asm/arch-mxs/regs-common.h index d2e1953..bcea419 100644 --- a/arch/arm/include/asm/arch-mxs/regs-common.h +++ b/arch/arm/include/asm/arch-mxs/regs-common.h @@ -1,5 +1,5 @@ /* - * Freescale i.MX28 Register Accessors + * Freescale i.MXS Register Accessors * * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com * on behalf of DENX Software Engineering GmbH @@ -20,11 +20,11 @@ * */

-#ifndef __MX28_REGS_COMMON_H__ -#define __MX28_REGS_COMMON_H__ +#ifndef __MXS_REGS_COMMON_H__ +#define __MXS_REGS_COMMON_H__

/* - * The i.MX28 has interesting feature when it comes to register access. There + * The i.MXS has interesting feature when it comes to register access. There * are four kinds of access to one particular register. Those are: * * 1) Common read/write access. To use this mode, just write to the address of @@ -47,36 +47,36 @@ * */

-#define __mx28_reg_8(name) \ +#define __mxs_reg_8(name) \ uint8_t name[4]; \ uint8_t name##_set[4]; \ uint8_t name##_clr[4]; \ uint8_t name##_tog[4]; \

-#define __mx28_reg_32(name) \ +#define __mxs_reg_32(name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog;

-struct mx28_register_8 { - __mx28_reg_8(reg) +struct mxs_register_8 { + __mxs_reg_8(reg) };

-struct mx28_register_32 { - __mx28_reg_32(reg) +struct mxs_register_32 { + __mxs_reg_32(reg) };

-#define mx28_reg_8(name) \ +#define mxs_reg_8(name) \ union { \ - struct { __mx28_reg_8(name) }; \ - struct mx28_register_8 name##_reg; \ + struct { __mxs_reg_8(name) }; \ + struct mxs_register_8 name##_reg; \ };

-#define mx28_reg_32(name) \ +#define mxs_reg_32(name) \ union { \ - struct { __mx28_reg_32(name) }; \ - struct mx28_register_32 name##_reg; \ + struct { __mxs_reg_32(name) }; \ + struct mxs_register_32 name##_reg; \ };

-#endif /* __MX28_REGS_COMMON_H__ */ +#endif /* __MXS_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h index 9a63594..25d318f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-digctl.h +++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h @@ -26,16 +26,16 @@

#ifndef __ASSEMBLY__ struct mx28_digctl_regs { - mx28_reg_32(hw_digctl_ctrl) /* 0x000 */ - mx28_reg_32(hw_digctl_status) /* 0x010 */ - mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mx28_reg_32(hw_digctl_emi_status) /* 0x040 */ - mx28_reg_32(hw_digctl_read_margin) /* 0x050 */ + mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ + mxs_reg_32(hw_digctl_status) /* 0x010 */ + mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ + mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ + mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ + mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ uint32_t hw_digctl_writeonce; /* 0x060 */ uint32_t reserved_writeonce[3]; - mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mx28_reg_32(hw_digctl_bist_status) /* 0x080 */ + mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ + mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ uint32_t hw_digctl_entropy; /* 0x090 */ uint32_t reserved_entropy[3]; uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ @@ -43,7 +43,7 @@ struct mx28_digctl_regs {

uint32_t reserved1[4];

- mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ uint32_t hw_digctl_dbgrd; /* 0x0d0 */ uint32_t reserved_hw_digctl_dbgrd[3]; uint32_t hw_digctl_dbg; /* 0x0e0 */ @@ -51,21 +51,21 @@ struct mx28_digctl_regs {

uint32_t reserved2[4];

- mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ + mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ + mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ + mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ + mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ + mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ + mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ + mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ + mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ + mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ + mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ + mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ + mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ + mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ + mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */

uint32_t reserved3[36];

@@ -75,7 +75,7 @@ struct mx28_digctl_regs { uint32_t reserved_hw_digctl_scratch1[3]; uint32_t hw_digctl_armcache; /* 0x2a0 */ uint32_t reserved_hw_digctl_armcache[3]; - mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ diff --git a/arch/arm/include/asm/arch-mxs/regs-gpmi.h b/arch/arm/include/asm/arch-mxs/regs-gpmi.h index 1b487f4..190a570 100644 --- a/arch/arm/include/asm/arch-mxs/regs-gpmi.h +++ b/arch/arm/include/asm/arch-mxs/regs-gpmi.h @@ -30,22 +30,22 @@

#ifndef __ASSEMBLY__ struct mx28_gpmi_regs { - mx28_reg_32(hw_gpmi_ctrl0) - mx28_reg_32(hw_gpmi_compare) - mx28_reg_32(hw_gpmi_eccctrl) - mx28_reg_32(hw_gpmi_ecccount) - mx28_reg_32(hw_gpmi_payload) - mx28_reg_32(hw_gpmi_auxiliary) - mx28_reg_32(hw_gpmi_ctrl1) - mx28_reg_32(hw_gpmi_timing0) - mx28_reg_32(hw_gpmi_timing1) + mxs_reg_32(hw_gpmi_ctrl0) + mxs_reg_32(hw_gpmi_compare) + mxs_reg_32(hw_gpmi_eccctrl) + mxs_reg_32(hw_gpmi_ecccount) + mxs_reg_32(hw_gpmi_payload) + mxs_reg_32(hw_gpmi_auxiliary) + mxs_reg_32(hw_gpmi_ctrl1) + mxs_reg_32(hw_gpmi_timing0) + mxs_reg_32(hw_gpmi_timing1)

uint32_t reserved[4];

- mx28_reg_32(hw_gpmi_data) - mx28_reg_32(hw_gpmi_stat) - mx28_reg_32(hw_gpmi_debug) - mx28_reg_32(hw_gpmi_version) + mxs_reg_32(hw_gpmi_data) + mxs_reg_32(hw_gpmi_stat) + mxs_reg_32(hw_gpmi_debug) + mxs_reg_32(hw_gpmi_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h index 2e2e814..418a3c0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h @@ -27,20 +27,20 @@

#ifndef __ASSEMBLY__ struct mx28_i2c_regs { - mx28_reg_32(hw_i2c_ctrl0) - mx28_reg_32(hw_i2c_timing0) - mx28_reg_32(hw_i2c_timing1) - mx28_reg_32(hw_i2c_timing2) - mx28_reg_32(hw_i2c_ctrl1) - mx28_reg_32(hw_i2c_stat) - mx28_reg_32(hw_i2c_queuectrl) - mx28_reg_32(hw_i2c_queuestat) - mx28_reg_32(hw_i2c_queuecmd) - mx28_reg_32(hw_i2c_queuedata) - mx28_reg_32(hw_i2c_data) - mx28_reg_32(hw_i2c_debug0) - mx28_reg_32(hw_i2c_debug1) - mx28_reg_32(hw_i2c_version) + mxs_reg_32(hw_i2c_ctrl0) + mxs_reg_32(hw_i2c_timing0) + mxs_reg_32(hw_i2c_timing1) + mxs_reg_32(hw_i2c_timing2) + mxs_reg_32(hw_i2c_ctrl1) + mxs_reg_32(hw_i2c_stat) + mxs_reg_32(hw_i2c_queuectrl) + mxs_reg_32(hw_i2c_queuestat) + mxs_reg_32(hw_i2c_queuecmd) + mxs_reg_32(hw_i2c_queuedata) + mxs_reg_32(hw_i2c_data) + mxs_reg_32(hw_i2c_debug0) + mxs_reg_32(hw_i2c_debug1) + mxs_reg_32(hw_i2c_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h index 2738035..a2ac6a2 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h @@ -30,49 +30,49 @@

#ifndef __ASSEMBLY__ struct mx28_ocotp_regs { - mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mx28_reg_32(hw_ocotp_data) /* 0x10 */ - mx28_reg_32(hw_ocotp_cust0) /* 0x20 */ - mx28_reg_32(hw_ocotp_cust1) /* 0x30 */ - mx28_reg_32(hw_ocotp_cust2) /* 0x40 */ - mx28_reg_32(hw_ocotp_cust3) /* 0x50 */ - mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mx28_reg_32(hw_ocotp_swcap) /* 0x100 */ - mx28_reg_32(hw_ocotp_custcap) /* 0x110 */ - mx28_reg_32(hw_ocotp_lock) /* 0x120 */ - mx28_reg_32(hw_ocotp_ops0) /* 0x130 */ - mx28_reg_32(hw_ocotp_ops1) /* 0x140 */ - mx28_reg_32(hw_ocotp_ops2) /* 0x150 */ - mx28_reg_32(hw_ocotp_ops3) /* 0x160 */ - mx28_reg_32(hw_ocotp_un0) /* 0x170 */ - mx28_reg_32(hw_ocotp_un1) /* 0x180 */ - mx28_reg_32(hw_ocotp_un2) /* 0x190 */ - mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mx28_reg_32(hw_ocotp_rom6) /* 0x200 */ - mx28_reg_32(hw_ocotp_rom7) /* 0x210 */ - mx28_reg_32(hw_ocotp_srk0) /* 0x220 */ - mx28_reg_32(hw_ocotp_srk1) /* 0x230 */ - mx28_reg_32(hw_ocotp_srk2) /* 0x240 */ - mx28_reg_32(hw_ocotp_srk3) /* 0x250 */ - mx28_reg_32(hw_ocotp_srk4) /* 0x260 */ - mx28_reg_32(hw_ocotp_srk5) /* 0x270 */ - mx28_reg_32(hw_ocotp_srk6) /* 0x280 */ - mx28_reg_32(hw_ocotp_srk7) /* 0x290 */ - mx28_reg_32(hw_ocotp_version) /* 0x2a0 */ + mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ + mxs_reg_32(hw_ocotp_data) /* 0x10 */ + mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ + mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ + mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ + mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ + mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ + mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ + mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ + mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ + mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ + mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ + mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ + mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ + mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ + mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ + mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ + mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ + mxs_reg_32(hw_ocotp_lock) /* 0x120 */ + mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ + mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ + mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ + mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ + mxs_reg_32(hw_ocotp_un0) /* 0x170 */ + mxs_reg_32(hw_ocotp_un1) /* 0x180 */ + mxs_reg_32(hw_ocotp_un2) /* 0x190 */ + mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ + mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ + mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ + mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ + mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ + mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ + mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ + mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ + mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ + mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ + mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ + mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ + mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ + mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ + mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ + mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ + mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h index 80dcdf6..ca1d791 100644 --- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h @@ -30,129 +30,129 @@

#ifndef __ASSEMBLY__ struct mx28_pinctrl_regs { - mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */ + mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */

uint32_t reserved1[60];

- mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ + mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ + mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ + mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ + mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ + mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ + mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ + mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ + mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ + mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ + mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ + mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ + mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ + mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ + mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */

uint32_t reserved2[72];

- mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */ + mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ + mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ + mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ + mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ + mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ + mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ + mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ + mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ + mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ + mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ + mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ + mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ + mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ + mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ + mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ + mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ + mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ + mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ + mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ + mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */

uint32_t reserved3[112];

- mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */ + mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ + mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ + mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ + mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ + mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ + mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ + mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */

uint32_t reserved4[36];

- mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */ + mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ + mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ + mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ + mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ + mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */

uint32_t reserved5[108];

- mx28_reg_32(hw_pinctrl_din0) /* 0x900 */ - mx28_reg_32(hw_pinctrl_din1) /* 0x910 */ - mx28_reg_32(hw_pinctrl_din2) /* 0x920 */ - mx28_reg_32(hw_pinctrl_din3) /* 0x930 */ - mx28_reg_32(hw_pinctrl_din4) /* 0x940 */ + mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ + mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ + mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ + mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ + mxs_reg_32(hw_pinctrl_din4) /* 0x940 */

uint32_t reserved6[108];

- mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */ + mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ + mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ + mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ + mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ + mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */

uint32_t reserved7[300];

- mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ + mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ + mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ + mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ + mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ + mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */

uint32_t reserved8[44];

- mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ + mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ + mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ + mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ + mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ + mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */

uint32_t reserved9[44];

- mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ + mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ + mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ + mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ + mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ + mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */

uint32_t reserved10[44];

- mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ + mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ + mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ + mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ + mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ + mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */

uint32_t reserved11[44];

- mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ + mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ + mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ + mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ + mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ + mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */

uint32_t reserved12[380];

- mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */

uint32_t reserved13[76];

- mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ + mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h index 8eadc6d..3c9e3b0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power.h +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -26,10 +26,10 @@

#ifndef __ASSEMBLY__ struct mx28_power_regs { - mx28_reg_32(hw_power_ctrl) - mx28_reg_32(hw_power_5vctrl) - mx28_reg_32(hw_power_minpwr) - mx28_reg_32(hw_power_charge) + mxs_reg_32(hw_power_ctrl) + mxs_reg_32(hw_power_5vctrl) + mxs_reg_32(hw_power_minpwr) + mxs_reg_32(hw_power_charge) uint32_t hw_power_vdddctrl; uint32_t reserved_vddd[3]; uint32_t hw_power_vddactrl; @@ -44,23 +44,23 @@ struct mx28_power_regs { uint32_t reserved_misc[3]; uint32_t hw_power_dclimits; uint32_t reserved_dclimits[3]; - mx28_reg_32(hw_power_loopctrl) + mxs_reg_32(hw_power_loopctrl) uint32_t hw_power_sts; uint32_t reserved_sts[3]; - mx28_reg_32(hw_power_speed) + mxs_reg_32(hw_power_speed) uint32_t hw_power_battmonitor; uint32_t reserved_battmonitor[3];

uint32_t reserved[4];

- mx28_reg_32(hw_power_reset) - mx28_reg_32(hw_power_debug) - mx28_reg_32(hw_power_thermal) - mx28_reg_32(hw_power_usb1ctrl) - mx28_reg_32(hw_power_special) - mx28_reg_32(hw_power_version) - mx28_reg_32(hw_power_anaclkctrl) - mx28_reg_32(hw_power_refctrl) + mxs_reg_32(hw_power_reset) + mxs_reg_32(hw_power_debug) + mxs_reg_32(hw_power_thermal) + mxs_reg_32(hw_power_usb1ctrl) + mxs_reg_32(hw_power_special) + mxs_reg_32(hw_power_version) + mxs_reg_32(hw_power_anaclkctrl) + mxs_reg_32(hw_power_refctrl) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h index e605a03..0b660ae 100644 --- a/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h @@ -27,20 +27,20 @@

#ifndef __ASSEMBLY__ struct mx28_rtc_regs { - mx28_reg_32(hw_rtc_ctrl) - mx28_reg_32(hw_rtc_stat) - mx28_reg_32(hw_rtc_milliseconds) - mx28_reg_32(hw_rtc_seconds) - mx28_reg_32(hw_rtc_rtc_alarm) - mx28_reg_32(hw_rtc_watchdog) - mx28_reg_32(hw_rtc_persistent0) - mx28_reg_32(hw_rtc_persistent1) - mx28_reg_32(hw_rtc_persistent2) - mx28_reg_32(hw_rtc_persistent3) - mx28_reg_32(hw_rtc_persistent4) - mx28_reg_32(hw_rtc_persistent5) - mx28_reg_32(hw_rtc_debug) - mx28_reg_32(hw_rtc_version) + mxs_reg_32(hw_rtc_ctrl) + mxs_reg_32(hw_rtc_stat) + mxs_reg_32(hw_rtc_milliseconds) + mxs_reg_32(hw_rtc_seconds) + mxs_reg_32(hw_rtc_rtc_alarm) + mxs_reg_32(hw_rtc_watchdog) + mxs_reg_32(hw_rtc_persistent0) + mxs_reg_32(hw_rtc_persistent1) + mxs_reg_32(hw_rtc_persistent2) + mxs_reg_32(hw_rtc_persistent3) + mxs_reg_32(hw_rtc_persistent4) + mxs_reg_32(hw_rtc_persistent5) + mxs_reg_32(hw_rtc_debug) + mxs_reg_32(hw_rtc_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index be71d48..85b9894 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -29,26 +29,26 @@

#ifndef __ASSEMBLY__ struct mx28_ssp_regs { - mx28_reg_32(hw_ssp_ctrl0) - mx28_reg_32(hw_ssp_cmd0) - mx28_reg_32(hw_ssp_cmd1) - mx28_reg_32(hw_ssp_xfer_size) - mx28_reg_32(hw_ssp_block_size) - mx28_reg_32(hw_ssp_compref) - mx28_reg_32(hw_ssp_compmask) - mx28_reg_32(hw_ssp_timing) - mx28_reg_32(hw_ssp_ctrl1) - mx28_reg_32(hw_ssp_data) - mx28_reg_32(hw_ssp_sdresp0) - mx28_reg_32(hw_ssp_sdresp1) - mx28_reg_32(hw_ssp_sdresp2) - mx28_reg_32(hw_ssp_sdresp3) - mx28_reg_32(hw_ssp_ddr_ctrl) - mx28_reg_32(hw_ssp_dll_ctrl) - mx28_reg_32(hw_ssp_status) - mx28_reg_32(hw_ssp_dll_sts) - mx28_reg_32(hw_ssp_debug) - mx28_reg_32(hw_ssp_version) + mxs_reg_32(hw_ssp_ctrl0) + mxs_reg_32(hw_ssp_cmd0) + mxs_reg_32(hw_ssp_cmd1) + mxs_reg_32(hw_ssp_xfer_size) + mxs_reg_32(hw_ssp_block_size) + mxs_reg_32(hw_ssp_compref) + mxs_reg_32(hw_ssp_compmask) + mxs_reg_32(hw_ssp_timing) + mxs_reg_32(hw_ssp_ctrl1) + mxs_reg_32(hw_ssp_data) + mxs_reg_32(hw_ssp_sdresp0) + mxs_reg_32(hw_ssp_sdresp1) + mxs_reg_32(hw_ssp_sdresp2) + mxs_reg_32(hw_ssp_sdresp3) + mxs_reg_32(hw_ssp_ddr_ctrl) + mxs_reg_32(hw_ssp_dll_ctrl) + mxs_reg_32(hw_ssp_status) + mxs_reg_32(hw_ssp_dll_sts) + mxs_reg_32(hw_ssp_debug) + mxs_reg_32(hw_ssp_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 3e8dfe7..332654f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -29,25 +29,25 @@

#ifndef __ASSEMBLY__ struct mx28_timrot_regs { - mx28_reg_32(hw_timrot_rotctrl) - mx28_reg_32(hw_timrot_rotcount) - mx28_reg_32(hw_timrot_timctrl0) - mx28_reg_32(hw_timrot_running_count0) - mx28_reg_32(hw_timrot_fixed_count0) - mx28_reg_32(hw_timrot_match_count0) - mx28_reg_32(hw_timrot_timctrl1) - mx28_reg_32(hw_timrot_running_count1) - mx28_reg_32(hw_timrot_fixed_count1) - mx28_reg_32(hw_timrot_match_count1) - mx28_reg_32(hw_timrot_timctrl2) - mx28_reg_32(hw_timrot_running_count2) - mx28_reg_32(hw_timrot_fixed_count2) - mx28_reg_32(hw_timrot_match_count2) - mx28_reg_32(hw_timrot_timctrl3) - mx28_reg_32(hw_timrot_running_count3) - mx28_reg_32(hw_timrot_fixed_count3) - mx28_reg_32(hw_timrot_match_count3) - mx28_reg_32(hw_timrot_version) + mxs_reg_32(hw_timrot_rotctrl) + mxs_reg_32(hw_timrot_rotcount) + mxs_reg_32(hw_timrot_timctrl0) + mxs_reg_32(hw_timrot_running_count0) + mxs_reg_32(hw_timrot_fixed_count0) + mxs_reg_32(hw_timrot_match_count0) + mxs_reg_32(hw_timrot_timctrl1) + mxs_reg_32(hw_timrot_running_count1) + mxs_reg_32(hw_timrot_fixed_count1) + mxs_reg_32(hw_timrot_match_count1) + mxs_reg_32(hw_timrot_timctrl2) + mxs_reg_32(hw_timrot_running_count2) + mxs_reg_32(hw_timrot_fixed_count2) + mxs_reg_32(hw_timrot_match_count2) + mxs_reg_32(hw_timrot_timctrl3) + mxs_reg_32(hw_timrot_running_count3) + mxs_reg_32(hw_timrot_fixed_count3) + mxs_reg_32(hw_timrot_match_count3) + mxs_reg_32(hw_timrot_version) }; #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h index 0291d81..5dd5125 100644 --- a/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ b/arch/arm/include/asm/arch-mxs/regs-usbphy.h @@ -24,16 +24,16 @@ #define __REGS_USBPHY_H__

struct mx28_usbphy_regs { - mx28_reg_32(hw_usbphy_pwd) - mx28_reg_32(hw_usbphy_tx) - mx28_reg_32(hw_usbphy_rx) - mx28_reg_32(hw_usbphy_ctrl) - mx28_reg_32(hw_usbphy_status) - mx28_reg_32(hw_usbphy_debug) - mx28_reg_32(hw_usbphy_debug0_status) - mx28_reg_32(hw_usbphy_debug1) - mx28_reg_32(hw_usbphy_version) - mx28_reg_32(hw_usbphy_ip) + mxs_reg_32(hw_usbphy_pwd) + mxs_reg_32(hw_usbphy_tx) + mxs_reg_32(hw_usbphy_rx) + mxs_reg_32(hw_usbphy_ctrl) + mxs_reg_32(hw_usbphy_status) + mxs_reg_32(hw_usbphy_debug) + mxs_reg_32(hw_usbphy_debug0_status) + mxs_reg_32(hw_usbphy_debug1) + mxs_reg_32(hw_usbphy_version) + mxs_reg_32(hw_usbphy_ip) };

#define USBPHY_PWD_RXPWDRX (1 << 20) diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index e701c64..7337458 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -23,11 +23,11 @@ #ifndef __MX28_H__ #define __MX28_H__

-int mx28_reset_block(struct mx28_register_32 *reg); -int mx28_wait_mask_set(struct mx28_register_32 *reg, +int mx28_reset_block(struct mxs_register_32 *reg); +int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout); -int mx28_wait_mask_clr(struct mx28_register_32 *reg, +int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout);

diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 38dbc81..29f19ba 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DIN(bank); - struct mx28_register_32 *reg = - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); + struct mxs_register_32 *reg = + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1; } @@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOUT(bank); - struct mx28_register_32 *reg = - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); + struct mxs_register_32 *reg = + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

if (value) writel(1 << PAD_PIN(gpio), &reg->reg_set); @@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); - struct mx28_register_32 *reg = - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); + struct mxs_register_32 *reg = + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

writel(1 << PAD_PIN(gpio), &reg->reg_clr);

@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); - struct mx28_register_32 *reg = - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); + struct mxs_register_32 *reg = + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

writel(1 << PAD_PIN(gpio), &reg->reg_set);

diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index e1bd37e..f32df51 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -75,8 +75,8 @@ int ehci_hcd_init(void)

int ret; uint32_t usb_base, cap_base; - struct mx28_register_32 *digctl_ctrl = - (struct mx28_register_32 *)HW_DIGCTL_CTRL; + struct mxs_register_32 *digctl_ctrl = + (struct mxs_register_32 *)HW_DIGCTL_CTRL; struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;

@@ -119,8 +119,8 @@ int ehci_hcd_stop(void) { int ret; uint32_t tmp; - struct mx28_register_32 *digctl_ctrl = - (struct mx28_register_32 *)HW_DIGCTL_CTRL; + struct mxs_register_32 *digctl_ctrl = + (struct mxs_register_32 *)HW_DIGCTL_CTRL; struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;

-- 1.7.10

Otavio Salvador

5:38 p.m.

New subject: [U-Boot] [PATCH 8/8] MX28: rename regs-clkctrl.h to regs-clkctrl-mx28.h

The CLKCTRL registers are SoC specific so we ought to have it clear on filename.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br --- arch/arm/include/asm/arch-mxs/imx-regs.h | 2 +- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 294 +++++++++++++++++++++ arch/arm/include/asm/arch-mxs/regs-clkctrl.h | 294 --------------------- drivers/usb/host/ehci-mxs.c | 2 +- 4 files changed, 296 insertions(+), 296 deletions(-) create mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl.h

diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index 37d0a93..5e1901e 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -26,7 +26,7 @@ #include <asm/arch/regs-apbh.h> #include <asm/arch/regs-base.h> #include <asm/arch/regs-bch.h> -#include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-clkctrl-mx28.h> #include <asm/arch/regs-digctl.h> #include <asm/arch/regs-gpmi.h> #include <asm/arch/regs-i2c.h> diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h new file mode 100644 index 0000000..127370b --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h @@ -0,0 +1,294 @@ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_clkctrl_regs { + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ + mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ + mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mxs_reg_32(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl.h deleted file mode 100644 index 127370b..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Freescale i.MX28 CLKCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __MX28_REGS_CLKCTRL_H__ -#define __MX28_REGS_CLKCTRL_H__ - -#include <asm/arch/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mx28_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ - mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ - mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ - mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ - mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ - - uint32_t reserved[16]; - - mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mxs_reg_32(hw_clkctrl_version) /* 0x200 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) -#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF1_DIV_MASK 0xffff -#define CLKCTRL_SAIF1_DIV_OFFSET 0 - -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) -#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff -#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) -#define CLKCTRL_ETM_DIV_MASK 0x7f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) -#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) -#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 -#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) -#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 -#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) -#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) -#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) -#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) - -#define CLKCTRL_HSADC_RESETB (1 << 30) -#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) -#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 - -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_IO1 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_PIX 0 -#define CLKCTRL_FRAC1_HSADC 1 -#define CLKCTRL_FRAC1_GPMI 2 - -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) - -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index f32df51..8a36513 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -23,7 +23,7 @@ #include <asm/io.h> #include <asm/arch/regs-common.h> #include <asm/arch/regs-base.h> -#include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-clkctrl-mx28.h> #include <asm/arch/regs-usb.h> #include <asm/arch/regs-usbphy.h>

-- 1.7.10

Marek Vasut

11:03 p.m.

Dear Otavio Salvador,

...

The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Marek Vasut marex@denx.de

arch/arm/include/asm/arch-mx28/regs-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 94b512d..d2e1953 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -70,7 +70,7 @@ struct mx28_register_32 { #define mx28_reg_8(name) \ union { \ struct { __mx28_reg_8(name) }; \
struct mx28_register_32 name##_reg;	\
struct mx28_register_8 name##_reg;	\
};
#define mx28_reg_32(name) \

Didn't Fabio sent in something similar already? Either way

Acked-by: Marek Vasut marex@denx.de

Best regards, Marek Vasut

Otavio Salvador

11:12 p.m.

On Fri, May 11, 2012 at 6:03 PM, Marek Vasut marex@denx.de wrote:

...

...
The macro mistakenly referred to 32bit struct instead of 8bit one.

Didn't Fabio sent in something similar already? Either way

Yes; I asked him to send my patch while I was in a client with a very restricted firewall.

Thanks by acking it.

-- Otavio Salvador O.S. Systems E-mail: otavio@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br

Stefano Babic

13 Jun 13 Jun

11:06 a.m.

On 11/05/2012 17:37, Otavio Salvador wrote:

...

The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador otavio@ossystems.com.br Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Marek Vasut marex@denx.de

Applied to u-boot-imx, thanks.

Best regards, Stefano Babic

-- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

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Marek Vasut
Otavio Salvador
Stefano Babic