Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue

Signed-off-by: Ken Lin yungching0725@gmail.com --- board/advantech/dms-ba16/dms-ba16.c | 51 +++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)

diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c index a67752f1ca..8aa7ff1659 100644 --- a/board/advantech/dms-ba16/dms-ba16.c +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -534,6 +534,54 @@ static const struct boot_mode board_boot_modes[] = { }; #endif

+void pmic_init(void) +{ + +#define DA9063_ADDR 0x58 +#define BCORE2_CONF 0x9D +#define BCORE1_CONF 0x9E +#define BPRO_CONF 0x9F +#define BIO_CONF 0xA0 +#define BMEM_CONF 0xA1 +#define BPERI_CONF 0xA2 +#define MODE_BIT_H 7 +#define MODE_BIT_L 6 + + uchar val; + i2c_set_bus_num(2); + + i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1); + +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE @@ -563,6 +611,9 @@ int board_late_init(void) setup_ba16_sata(); #endif

+ /* board specific pmic init */ + pmic_init(); + return 0; }

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet

Signed-off-by: Ken Lin yungching0725@gmail.com --- board/advantech/dms-ba16/dms-ba16.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c index 8aa7ff1659..75b0bbc2cc 100644 --- a/board/advantech/dms-ba16/dms-ba16.c +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -103,8 +103,9 @@ static void setup_iomux_enet(void)

/* Reset AR8033 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); + mdelay(1); }

static iomux_v3_cfg_t const usdhc2_pads[] = {

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin yungching0725@gmail.com --- board/advantech/dms-ba16/dms-ba16.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c index 75b0bbc2cc..91e96ab096 100644 --- a/board/advantech/dms-ba16/dms-ba16.c +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -304,7 +304,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev) /* set debug port address: SerDes Test and System Mode Control */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); /* enable rgmii tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + /* set the reserved bits to avoid board specific voltage peak issue*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);

return 0; }