Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit

Signed-off-by: Nikhil Badola nikhil.badola@freescale.com Signed-off-by: Ramneek Mehresh ramneek.mehresh@freescale.com --- Changes for v2: - Using clrsetbits_be32() instead of new API

drivers/usb/host/ehci-fsl.c | 15 ++++++++++----- include/usb/ehci-fsl.h | 2 ++ 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6cb4d98..45062e6 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,

if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) - setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); - setbits_be32(&ehci->control, UTMI_PHY_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_UTMI); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); - setbits_be32(&ehci->control, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + USB_EN); } else { - setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); - clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_ULPI); + clrsetbits_be32(&ehci->control, UTMI_PHY_EN | + CONTROL_REGISTER_W1C_MASK, USB_EN); udelay(1000); /* delay required for PHY Clk to appear */ if (!usb_phy_clk_valid(ehci)) return -EINVAL; diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index c9ee1d5..dd77ad6 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -11,6 +11,8 @@

#include <asm/processor.h>

+#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ + /* Global offsets */ #define FSL_SKIP_PCI 0x100