[U-Boot] [PATCH v1 0/24] Zynq DT changes
Hi,
this is respin of Jagan v3 series sent here http://lists.denx.de/pipermail/u-boot/2013-December/169617.html + 2 patches v4 http://lists.denx.de/pipermail/u-boot/2013-December/169753.html http://lists.denx.de/pipermail/u-boot/2013-December/169752.html
The purpose of this series was to synchronized configuration which we are using with mainline version with adding features which we are using.
The major change, which I have done, is adding DT support for all zynq boards instead of board specification configurations. I have changed serial, gem, emaclite, mmc. i2c, spi already support bus selection.
For more information please look at patches.
All series are available here for easier testing. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/z...
Thanks, Michal
Changes in v1: - Remove doc compare to origin Jagan version - Update to the latest status
Jagannadha Sutradharudu Teki (19): gpio: zynq: Add dummy gpio routines zynq: Enable CONFIG_FIT_VERBOSE zynq: Enable Boot FreeBSD/vxWorks zynq: Cleanup on miscellaneous configs zynq: Cleanup on memory configs zynq: Minor config cleanup zynq: Enable cache options zynq: serial: Simplify serial driver initialization zynq: Add GEM0, GEM1 configs support zynq-common: Define exact TEXT_BASE zynq: Add Catalyst 24WC08 EEPROM config support zynq-common: Define default environment zynq-common: Change Env. Sector size to 128Kb zynq-common: Define flash env. partition zynq-common: Define CONFIG_ENV_OVERWRITE zynq: Add support to find bootmode dts: zynq: Add fdt support zynq-common: Enable verified boot(RSA) doc: zynq: Add information on zynq u-boot
Michal Simek (5): net: emaclite: Fix OF initialization net: gem: Add OF initialization support mmc: zynq: Add OF initialization support zynq: Add OF ram initialization support serial: zynq: Add OF initialization support
arch/arm/cpu/armv7/zynq/slcr.c | 6 + arch/arm/include/asm/arch-zynq/gpio.h | 25 ++ arch/arm/include/asm/arch-zynq/hardware.h | 2 + arch/arm/include/asm/arch-zynq/sys_proto.h | 2 + board/xilinx/dts/zynq-generic.dts | 421 +++++++++++++++++++++++++++++ board/xilinx/zynq/board.c | 75 +++-- doc/README.zynq | 76 ++++++ drivers/mmc/zynq_sdhci.c | 29 ++ drivers/net/xilinx_emaclite.c | 15 +- drivers/net/zynq_gem.c | 42 +++ drivers/serial/serial_zynq.c | 62 ++++- include/configs/zynq.h | 203 +++++++++----- include/netdev.h | 2 + 13 files changed, 850 insertions(+), 110 deletions(-) create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h create mode 100644 board/xilinx/dts/zynq-generic.dts create mode 100644 doc/README.zynq
-- 1.8.2.3
- Add xilinx_emaclite_of_init to netdev.h - Remove global data pointer from the driver - Add better handling for error state.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
drivers/net/xilinx_emaclite.c | 15 ++++++++------- include/netdev.h | 1 + 2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 0a5209d..a607098 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -14,8 +14,6 @@ #include <asm/io.h> #include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR; - #undef DEBUG
#define ENET_ADDR_LENGTH 6 @@ -364,24 +362,27 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, }
#ifdef CONFIG_OF_CONTROL -int xilinx_emaclite_init(bd_t *bis) +int xilinx_emaclite_of_init(const void *blob) { int offset = 0; u32 ret = 0; u32 reg;
do { - offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + offset = fdt_node_offset_by_compatible(blob, offset, "xlnx,xps-ethernetlite-1.00.a"); if (offset != -1) { - reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg"); + reg = fdtdec_get_addr(blob, offset, "reg"); if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 rxpp = fdtdec_get_int(blob, offset, "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 txpp = fdtdec_get_int(blob, offset, "xlnx,tx-ping-pong", 0); ret |= xilinx_emaclite_initialize(bis, reg, txpp, rxpp); + } else { + debug("EMACLITE: Can't get base address\n"); + return -1; } } } while (offset != -1); diff --git a/include/netdev.h b/include/netdev.h index 47fa80d..25d1e46 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -86,6 +86,7 @@ int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr); +int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, -- 1.8.2.3
Gem can be directly initialized from DTB.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
drivers/net/zynq_gem.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/netdev.h | 1 + 2 files changed, 43 insertions(+)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 6a017a8..a673fa7 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -12,6 +12,8 @@ #include <common.h> #include <net.h> #include <config.h> +#include <fdtdec.h> +#include <libfdt.h> #include <malloc.h> #include <asm/io.h> #include <phy.h> @@ -527,3 +529,43 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
return 1; } + +#ifdef CONFIG_OF_CONTROL +int zynq_gem_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg, phy_reg; + + debug("ZYNQ GEM: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "xlnx,ps7-ethernet-1.00.a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + offset = fdtdec_lookup_phandle(blob, offset, + "phy-handle"); + if (offset != -1) + phy_reg = fdtdec_get_addr(blob, offset, + "reg"); + else + phy_reg = 0; + + debug("ZYNQ GEM: addr %x, phyaddr %x\n", + reg, phy_reg); + + ret |= zynq_gem_initialize(NULL, reg, + phy_reg, 0); + + } else { + debug("ZYNQ GEM: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/include/netdev.h b/include/netdev.h index 25d1e46..b9eab0e 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -91,6 +91,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); +int zynq_gem_of_init(const void *blob); int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio); /* * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface -- 1.8.2.3
Enable initialize sdhci from DTB.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + drivers/mmc/zynq_sdhci.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 110de90..bb089b6 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -18,5 +18,6 @@ extern void zynq_ddrc_init(void);
/* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); +extern int zynq_sdhci_of_init(const void *blob);
#endif /* _SYS_PROTO_H_ */ diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 610bef5..d39cbf0 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -7,6 +7,8 @@ */
#include <common.h> +#include <fdtdec.h> +#include <libfdt.h> #include <malloc.h> #include <sdhci.h> #include <asm/arch/sys_proto.h> @@ -31,3 +33,30 @@ int zynq_sdhci_init(u32 regbase) add_sdhci(host, 52000000, 52000000 >> 9); return 0; } + +#ifdef CONFIG_OF_CONTROL +int zynq_sdhci_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg; + + debug("ZYNQ SDHCI: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "arasan,sdhci-8.9a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + ret |= zynq_sdhci_init(reg); + } else { + debug("ZYNQ SDHCI: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif -- 1.8.2.3
Read ram size directly from DTB.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
board/xilinx/zynq/board.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5119c09..6b691f3 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <fdtdec.h> #include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> @@ -115,8 +116,27 @@ int board_mmc_init(bd_t *bd)
int dram_init(void) { +#ifdef CONFIG_OF_CONTROL + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("ZYNQ DRAM: Can't get memory node\n"); + return -1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("ZYNQ DRAM: Can't get base address or size\n"); + return -1; + } + gd->ram_size = size; +#else gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - +#endif zynq_ddrc_init();
return 0; -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
arch/arm/include/asm/arch-zynq/gpio.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h new file mode 100644 index 0000000..2dbba75 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/gpio.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_GPIO_H +#define _ZYNQ_GPIO_H + +inline int gpio_get_value(unsigned gpio) +{ + return 0; +} + +inline int gpio_set_value(unsigned gpio, int val) +{ + return 0; +} + +inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +#endif /* _ZYNQ_GPIO_H */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Enabled fit_format_{error,warning}()
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 82ec826..6019c4a 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -127,6 +127,7 @@
/* OF */ #define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT
/* Commands */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
This enabled Boot FreeBSD/vxWorks from an ELF image support
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 6019c4a..0492818 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -130,6 +130,13 @@ #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT
+/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + /* Commands */ #include <config_cmd_default.h>
-- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Cleanup on miscellaneous configurable options: - Rename SYS_PROMPT as "zynq-uboot" - Add comment - Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 0492818..e34024d 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -111,19 +111,20 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "zynq-uboot> " +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LOAD_ADDR 0 -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* OF */ #define CONFIG_FIT -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Cleanup on memory configuration options: - Add comment - Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index e34024d..8be52df 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -13,14 +13,6 @@ /* CPU clock */ #define CONFIG_CPU_FREQ_HZ 800000000
-/* Ram */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} @@ -105,11 +97,6 @@ #define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MALLOC_LEN 0x400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE)
/* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -125,7 +112,21 @@
#define CONFIG_SYS_LOAD_ADDR 0
+/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) /* OF */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Cleanups mostly on: - Add comments - Re-order configs - Remove #define CONFIG_ZYNQ_SDHCI
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 75 ++++++++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 8be52df..44ae5ed 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -7,33 +7,51 @@ #ifndef __CONFIG_ZYNQ_H #define __CONFIG_ZYNQ_H
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +/* High Level configuration Options */ +#define CONFIG_ARMV7 #define CONFIG_ZYNQ
/* CPU clock */ -#define CONFIG_CPU_FREQ_HZ 800000000 +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif
+/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-#define CONFIG_BAUDRATE 115200 - -/* XPSS Serial driver */ +/* Zynq Serial driver */ #define CONFIG_ZYNQ_SERIAL #define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 #define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + /* Ethernet driver */ #define CONFIG_NET_MULTI #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
-#define CONFIG_ZYNQ_SDHCI -#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SPI +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif + +/* NOR */ +#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_SDHCI0 /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -58,26 +76,6 @@ # define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif
-#if defined(CONFIG_ZYNQ_DCC) -# define CONFIG_ARM_DCC -# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ -#endif - -#define CONFIG_ZYNQ_SPI - -/* SPI */ -#ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH -# define CONFIG_SPI_FLASH_SST -# define CONFIG_CMD_SF -#endif - -/* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA - #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY @@ -91,12 +89,9 @@ #define CONFIG_PHY_MARVELL
/* Environment */ +#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0
/* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -110,8 +105,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LOAD_ADDR 0 - /* Physical Memory map */ #define CONFIG_SYS_TEXT_BASE 0
@@ -122,15 +115,25 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+#define CONFIG_SYS_MALLOC_LEN 0x400000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -/* OF */ + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +/* FIT support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -#define CONFIG_OF_LIBFDT
/* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
- Enable cache command - Turn-off L2 cache - Turn-on D-cache
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 44ae5ed..3938b54 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -16,6 +16,16 @@ # define CONFIG_CPU_FREQ_HZ 800000000 #endif
+/* Cache options */ +#define CONFIG_CMD_CACHE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + /* Serial drivers */ #define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Define both serial uarts in the driver and return default uart based on board configuration.
- Move baseaddresses to hardware.h - Define default baudrate and clock values
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
arch/arm/include/asm/arch-zynq/hardware.h | 2 ++ drivers/serial/serial_zynq.c | 34 ++++++++++++++++++------------- include/configs/zynq.h | 9 +++----- 3 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index cd69677..b1a7775 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H
+#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 +#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index ff28f3c..9b24af2 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> +#include <asm/arch/hardware.h>
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -33,13 +34,23 @@ struct uart_zynq { };
static struct uart_zynq *uart_zynq_ports[2] = { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 - [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, + [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, + [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +}; + +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 - [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +#endif + +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0) +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1) +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 #endif -};
struct uart_zynq_params { u32 baudrate; @@ -47,14 +58,10 @@ struct uart_zynq_params { };
static struct uart_zynq_params uart_zynq_ports_param[2] = { -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, -#endif -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, -#endif };
/* Set up the baud rate in gd struct */ @@ -186,20 +193,19 @@ struct serial_device uart_zynq_serial1_device =
__weak struct serial_device *default_serial_console(void) { +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 if (uart_zynq_ports[0]) return &uart_zynq_serial0_device; +#endif +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 if (uart_zynq_ports[1]) return &uart_zynq_serial1_device; - +#endif return NULL; }
void zynq_serial_initalize(void) { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 serial_register(&uart_zynq_serial0_device); -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 serial_register(&uart_zynq_serial1_device); -#endif } diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 3938b54..6632223 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -32,16 +32,13 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL -#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 - /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) # define CONFIG_ARM_DCC # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#else +# define CONFIG_ZYNQ_SERIAL_BASEADDR1 +# define CONFIG_ZYNQ_SERIAL #endif
/* Ethernet driver */ -- 1.8.2.3
Add console selection from DTB which is enough to have OF driven solution.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
drivers/serial/serial_zynq.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 9b24af2..3f7fcfa 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -6,12 +6,15 @@ */
#include <common.h> +#include <fdtdec.h> #include <watchdog.h> #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> #include <asm/arch/hardware.h>
+DECLARE_GLOBAL_DATA_PTR; + #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
@@ -191,6 +194,30 @@ DECLARE_PSSERIAL_FUNCTIONS(1); struct serial_device uart_zynq_serial1_device = INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+#ifdef CONFIG_OF_CONTROL +__weak struct serial_device *default_serial_console(void) +{ + const void *blob = gd->fdt_blob; + int node; + unsigned int base_addr; + + node = fdt_path_offset(blob, "serial0"); + if (node < 0) + return NULL; + + base_addr = fdtdec_get_addr(blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) + return NULL; + + if (base_addr == ZYNQ_SERIAL_BASEADDR0) + return &uart_zynq_serial0_device; + + if (base_addr == ZYNQ_SERIAL_BASEADDR1) + return &uart_zynq_serial1_device; + + return NULL; +} +#else __weak struct serial_device *default_serial_console(void) { #ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 @@ -203,6 +230,7 @@ __weak struct serial_device *default_serial_console(void) #endif return NULL; } +#endif
void zynq_serial_initalize(void) { -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Zynq ethernet controller support two GEM's like CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled both so-that the respective board will define these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 6632223..2f8f4ab 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -42,10 +42,16 @@ #endif
/* Ethernet driver */ -#define CONFIG_NET_MULTI -#define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif
#define CONFIG_ZYNQ_SPI /* SPI */ @@ -89,12 +95,6 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL
-/* MII and Phylib */ -#define CONFIG_MII -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHYLIB -#define CONFIG_PHY_MARVELL - /* Environment */ #define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Defined TEXT_BASE for u-boot starts from 0x4000000 w.r.t zynq memory-map.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 2f8f4ab..c90d4fd 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -113,7 +113,7 @@ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Physical Memory map */ -#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_SYS_TEXT_BASE 0x4000000
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0 -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Adds configurations for Catalyst 24WC08 EEPROM, which is present on the zynq boards.
Enable EEPROM support for zynq boards.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index c90d4fd..2ea5d3f 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -89,6 +89,17 @@ # define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif
+#define CONFIG_ZYNQ_EEPROM +/* EEPROM */ +#ifdef CONFIG_ZYNQ_EEPROM +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ +#endif + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Defined default env. for autoboot FIT image from respective boot devices.
Default settings: fit_image=fit.itb load_addr=0x2000000 fit_size=0x800000 flash_off=0x100000 nor_flash_off=0xE2100000
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 2ea5d3f..5a33e15 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -109,7 +109,28 @@ /* Environment */ #define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_LOAD_ADDR 0 + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fit_image=fit.itb\0" \ + "load_addr=0x2000000\0" \ + "fit_size=0x800000\0" \ + "flash_off=0x100000\0" \ + "nor_flash_off=0xE2100000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "norboot=echo Copying FIT from NOR flash to RAM... && " \ + "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ + "bootm ${load_addr}\0" \ + "sdboot=echo Copying FIT from SD to RAM... && " \ + "fatload mmc 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "jtagboot=echo TFTPing FIT to RAM... && " \ + "tftp ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
/* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Changed Env. Sector size from 0x10000 to 128Kb
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 5a33e15..a6caf0c 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -106,8 +106,10 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL
+/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE (128 << 10) + /* Environment */ -#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE
/* Default environment */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Last 128Kb sector of 1Mb flash is defined as u-boot environment partition.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index a6caf0c..2e82073 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -110,7 +110,17 @@ #define CONFIG_ENV_SIZE (128 << 10)
/* Environment */ -#define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_ENV_IS_NOWHERE +# ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_ENV_IS_IN_FLASH +# elif defined(CONFIG_SYS_NO_FLASH) +# define CONFIG_ENV_IS_NOWHERE +# endif + +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +# define CONFIG_ENV_OFFSET 0xE0000 +# define CONFIG_CMD_SAVEENV +#endif
/* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Defined CONFIG_ENV_OVERWRITE, which allow to overwrite serial baudrate and ethaddr.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 2e82073..ed7de6c 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -109,6 +109,9 @@ /* Total Size of Environment Sector */ #define CONFIG_ENV_SIZE (128 << 10)
+/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + /* Environment */ #ifndef CONFIG_ENV_IS_NOWHERE # ifndef CONFIG_SYS_NO_FLASH -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com
---
Changes in v1: - Remove doc compare to origin Jagan version
arch/arm/cpu/armv7/zynq/slcr.c | 6 ++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + board/xilinx/zynq/board.c | 25 +++++++++++++++++++++++++ include/configs/zynq.h | 1 + 4 files changed, 33 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 717ec65..b4c11c3 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void) zynq_slcr_lock(); }
+u32 zynq_slcr_get_boot_mode(void) +{ + /* Get the bootmode register value */ + return readl(&slcr_base->boot_mode); +} + u32 zynq_slcr_get_idcode(void) { return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index bb089b6..86e7db5 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void); extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 6b691f3..6629b20 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -13,6 +13,12 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0x0F +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + #ifdef CONFIG_FPGA Xilinx_desc fpga;
@@ -60,6 +66,25 @@ int board_init(void) return 0; }
+int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +}
#ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index ed7de6c..5e7adc2 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -153,6 +153,7 @@
#define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
This patch provides a basic fdt support for zynq u-boot.
zynq-generic.dts-> DTS for zc702
u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
board/xilinx/dts/zynq-generic.dts | 421 ++++++++++++++++++++++++++++++++++++++ board/xilinx/zynq/board.c | 28 +-- include/configs/zynq.h | 21 +- 3 files changed, 437 insertions(+), 33 deletions(-) create mode 100644 board/xilinx/dts/zynq-generic.dts
diff --git a/board/xilinx/dts/zynq-generic.dts b/board/xilinx/dts/zynq-generic.dts new file mode 100644 index 0000000..1524a6a --- /dev/null +++ b/board/xilinx/dts/zynq-generic.dts @@ -0,0 +1,421 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK monstr@monstr.eu + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + i2c0 = &ps7_i2c_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_0: ps7-can@e0008000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 19>, <&clkc 36>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 28 4>; + reg = <0xe0008000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + enet-reset = <&ps7_gpio_0 11 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + i2c-reset = <&ps7_gpio_0 13 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@54 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "pmbus,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "pmbus,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "pmbus,ucd9248"; + reg = <54>; + }; + }; + }; + + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; + + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr", "syscon"; + reg = <0xf8000000 0x1000>; + clkc: clkc@100 { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + reg = <0x100 0x100>; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + usb-reset = <&ps7_gpio_0 7 0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 6629b20..139e48c 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -95,28 +95,13 @@ int board_eth_init(bd_t *bis) ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, XILINX_AXIDMA_BASEADDR); #endif + #ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); + xilinx_emaclite_of_init(gd->fdt_blob); #endif
#if defined(CONFIG_ZYNQ_GEM) -# if defined(CONFIG_ZYNQ_GEM0) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM1) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); -# endif + zynq_gem_of_init(gd->fdt_blob); #endif return ret; } @@ -128,12 +113,7 @@ int board_mmc_init(bd_t *bd) int ret = 0;
#if defined(CONFIG_ZYNQ_SDHCI) -# if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); -# endif -# if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); -# endif + ret = zynq_sdhci_of_init(gd->fdt_blob); #endif return ret; } diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 5e7adc2..b21e060 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -37,16 +37,14 @@ # define CONFIG_ARM_DCC # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ #else -# define CONFIG_ZYNQ_SERIAL_BASEADDR1 # define CONFIG_ZYNQ_SERIAL #endif
+#define CONFIG_ZYNQ_GEM + /* Ethernet driver */ -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +#ifdef CONFIG_ZYNQ_GEM # define CONFIG_NET_MULTI -# define CONFIG_ZYNQ_GEM # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHYLIB @@ -64,13 +62,13 @@ /* NOR */ #define CONFIG_SYS_NO_FLASH
-#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI + /* MMC */ -#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +#if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC # define CONFIG_SDHCI -# define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC # define CONFIG_CMD_FAT # define CONFIG_SUPPORT_VFAT @@ -165,7 +163,6 @@
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) @@ -190,6 +187,12 @@ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+/* FDT support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_EMBED +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DEFAULT_DEVICE_TREE "zynq-generic" + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
CONFIG_FIT_SIGNATURE - signature node support in FIT image CONFIG_RSA - RSA lib support
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v1: None
include/configs/zynq.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index b21e060..36caa36 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -193,6 +193,10 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_DEFAULT_DEVICE_TREE "zynq-generic"
+/* RSA support */ +#define CONFIG_FIT_SIGNATURE +#define CONFIG_RSA + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- 1.8.2.3
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Information on zynq u-boot about - mainline status - TODO
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com
---
Changes in v1: - Update to the latest status
doc/README.zynq | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 doc/README.zynq
diff --git a/doc/README.zynq b/doc/README.zynq new file mode 100644 index 0000000..c046df4 --- /dev/null +++ b/doc/README.zynq @@ -0,0 +1,76 @@ +# +# Xilinx ZYNQ U-Boot +# +# (C) Copyright 2013 Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +1. About this + +This document describes the information about Xilinx Zynq U-Boot - +like supported boards, ML status and TODO list. + +2. Zynq boards + +Xilinx Zynq-7000 All Programmable SoCs enable extensive system level +differentiation, integration, and flexibility through hardware, software, +and I/O programmability. + +3. Building + + # Configure for microzed board + $ make zynq_config + Configuring for zynq board... + + # Building with zynq generic DTS file + $ make + + # Building with different DTS file placed in board/xilinx/dts/ + $ make DEVICE_TREE=zynq-XXX + +4. Bootmode + +Zynq has a facility to read the bootmode from the slcr bootmode register +once user is setting through jumpers on the board - see page no:1546 on [5] + +All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins +on [5]. + +board_late_init() will read the bootmode values using slcr bootmode register +at runtime and assign the modeboot variable to specific bootmode string which +is intern used in autoboot. + +SLCR bootmode register Bit[3:0] values +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + +"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" +bootmode strings at runtime. + +5. Mainline status + +- Added basic board configurations support. +- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq +- Added zynq boards names - zynq, zynq_dcc +- Added zynq drivers: + serial - drivers/serial/serial_zynq.c + net - drivers/net/zynq_gem.c + mmc - drivers/mmc/zynq_sdhci.c + spi- drivers/spi/zynq_spi.c + i2c - drivers/i2c/zynq_i2c.c +- Done proper cleanups on board configurations +- Added FDT support +- d-cache support for zynq_gem.c + +6. TODO + +- Add zynq qspi controller driver +- Add zynq nand controller driver + +[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm +[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm +[3] http://zedboard.org/product/zedboard +[4] http://zedboard.org/product/microzed +[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.... -- 1.8.2.3
Why are you cross posting this to linux-arm-kernel? There's already enough traffic on this list without having u-boot patches also posted here.
I think you're the only one who does this, so please refrain from doing so in the future. Those who are interested in uboot development will already be subscribed to the uboot mailing list.
Thanks.
On Fri, Jan 03, 2014 at 11:10:45AM +0100, Michal Simek wrote:
Hi,
this is respin of Jagan v3 series sent here http://lists.denx.de/pipermail/u-boot/2013-December/169617.html
- 2 patches v4
http://lists.denx.de/pipermail/u-boot/2013-December/169753.html http://lists.denx.de/pipermail/u-boot/2013-December/169752.html
The purpose of this series was to synchronized configuration which we are using with mainline version with adding features which we are using.
The major change, which I have done, is adding DT support for all zynq boards instead of board specification configurations. I have changed serial, gem, emaclite, mmc. i2c, spi already support bus selection.
For more information please look at patches.
All series are available here for easier testing. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/z...
Thanks, Michal
Changes in v1:
- Remove doc compare to origin Jagan version
- Update to the latest status
Jagannadha Sutradharudu Teki (19): gpio: zynq: Add dummy gpio routines zynq: Enable CONFIG_FIT_VERBOSE zynq: Enable Boot FreeBSD/vxWorks zynq: Cleanup on miscellaneous configs zynq: Cleanup on memory configs zynq: Minor config cleanup zynq: Enable cache options zynq: serial: Simplify serial driver initialization zynq: Add GEM0, GEM1 configs support zynq-common: Define exact TEXT_BASE zynq: Add Catalyst 24WC08 EEPROM config support zynq-common: Define default environment zynq-common: Change Env. Sector size to 128Kb zynq-common: Define flash env. partition zynq-common: Define CONFIG_ENV_OVERWRITE zynq: Add support to find bootmode dts: zynq: Add fdt support zynq-common: Enable verified boot(RSA) doc: zynq: Add information on zynq u-boot
Michal Simek (5): net: emaclite: Fix OF initialization net: gem: Add OF initialization support mmc: zynq: Add OF initialization support zynq: Add OF ram initialization support serial: zynq: Add OF initialization support
arch/arm/cpu/armv7/zynq/slcr.c | 6 + arch/arm/include/asm/arch-zynq/gpio.h | 25 ++ arch/arm/include/asm/arch-zynq/hardware.h | 2 + arch/arm/include/asm/arch-zynq/sys_proto.h | 2 + board/xilinx/dts/zynq-generic.dts | 421 +++++++++++++++++++++++++++++ board/xilinx/zynq/board.c | 75 +++-- doc/README.zynq | 76 ++++++ drivers/mmc/zynq_sdhci.c | 29 ++ drivers/net/xilinx_emaclite.c | 15 +- drivers/net/zynq_gem.c | 42 +++ drivers/serial/serial_zynq.c | 62 ++++- include/configs/zynq.h | 203 +++++++++----- include/netdev.h | 2 + 13 files changed, 850 insertions(+), 110 deletions(-) create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h create mode 100644 board/xilinx/dts/zynq-generic.dts create mode 100644 doc/README.zynq
-- 1.8.2.3
linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Michal,
On Fri, 3 Jan 2014 11:10:45 +0100, Michal Simek michal.simek@xilinx.com wrote:
Hi,
this is respin of Jagan v3 series sent here http://lists.denx.de/pipermail/u-boot/2013-December/169617.html
- 2 patches v4
http://lists.denx.de/pipermail/u-boot/2013-December/169753.html http://lists.denx.de/pipermail/u-boot/2013-December/169752.html
The purpose of this series was to synchronized configuration which we are using with mainline version with adding features which we are using.
The major change, which I have done, is adding DT support for all zynq boards instead of board specification configurations. I have changed serial, gem, emaclite, mmc. i2c, spi already support bus selection.
For more information please look at patches.
All series are available here for easier testing. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/z...
Thanks, Michal
As Jagan's series has been pulled in, can you resubmit a v2 based on current ARM ToT?
Amicalement,
Hi Albert,
On 01/14/2014 01:08 PM, Albert ARIBAUD wrote:
Hi Michal,
On Fri, 3 Jan 2014 11:10:45 +0100, Michal Simek michal.simek@xilinx.com wrote:
Hi,
this is respin of Jagan v3 series sent here http://lists.denx.de/pipermail/u-boot/2013-December/169617.html
- 2 patches v4
http://lists.denx.de/pipermail/u-boot/2013-December/169753.html http://lists.denx.de/pipermail/u-boot/2013-December/169752.html
The purpose of this series was to synchronized configuration which we are using with mainline version with adding features which we are using.
The major change, which I have done, is adding DT support for all zynq boards instead of board specification configurations. I have changed serial, gem, emaclite, mmc. i2c, spi already support bus selection.
For more information please look at patches.
All series are available here for easier testing. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/z...
Thanks, Michal
As Jagan's series has been pulled in, can you resubmit a v2 based on current ARM ToT?
yes. That was my plan.
Thanks, Michal
participants (4)
-
Albert ARIBAUD -
Michal Simek -
Michal Simek -
Russell King - ARM Linux