[PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com ---
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + &usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; }; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 {
u-boot,dm-spl;+};
+&pinctrl {
u-boot,dm-spl;+};
+&sdmmc0m1_gpio {
u-boot,dm-spl;+};
+&pcfg_pull_up_4ma {
u-boot,dm-spl;+};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd {
u-boot,dm-spl;+}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 { + u-boot,dm-spl; +};
+&pinctrl { + u-boot,dm-spl; +};
+&sdmmc0m1_gpio { + u-boot,dm-spl; +};
+&pcfg_pull_up_4ma { + u-boot,dm-spl; +};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock- rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 { + u-boot,dm-spl; +};
+&pinctrl { + u-boot,dm-spl; +};
+&sdmmc0m1_gpio { + u-boot,dm-spl; +};
+&pcfg_pull_up_4ma { + u-boot,dm-spl; +};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock- rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 {
u-boot,dm-spl;+};
+&pinctrl {
u-boot,dm-spl;+};
+&sdmmc0m1_gpio {
u-boot,dm-spl;+};
+&pcfg_pull_up_4ma {
u-boot,dm-spl;+};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd {
u-boot,dm-spl;+}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock- rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Hi Matwey,
Thank you for testing the patch. Hmm, are you building with ATF 2.3?
I’m booting from the uSD without an eMMC installed. Are you booting from the eMMC or have one installed?
Here are some background emails related to the gen3 freeze. I also included the output for when gen3 fails below and the output for my gen2 2gb and gen3 4gb with the patch.
https://marc.info/?l=u-boot&m=158550521101881&w=2 https://marc.info/?l=u-boot&m=156427088018689&w=2
Gen2 2GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 2 GiB PMIC: RK8050 (on=0x40, off=0x01) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 15 ms (10.8 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 14 ms (11.5 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB without patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 Trying to boot from MMC2 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 { + u-boot,dm-spl; +};
+&pinctrl { + u-boot,dm-spl; +};
+&sdmmc0m1_gpio { + u-boot,dm-spl; +};
+&pcfg_pull_up_4ma { + u-boot,dm-spl; +};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned- clock- rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
вт, 19 мая 2020 г. в 17:30, Kurt Miller kurt@intricatesoftware.com:
On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Hi Matwey,
Hi Kurt,
Thank you for testing the patch. Hmm, are you building with ATF 2.3?
You are right here, I was testing with ATF 2.1, while ATF 2.3 works correctly. First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE to 0x40000"). I suppose, it is worth to mention in the commit message for this patch. What do you think?
I’m booting from the uSD without an eMMC installed. Are you booting from the eMMC or have one installed?
I'm booting from uSD without eMMC installed also.
Here are some background emails related to the gen3 freeze. I also included the output for when gen3 fails below and the output for my gen2 2gb and gen3 4gb with the patch.
https://marc.info/?l=u-boot&m=158550521101881&w=2 https://marc.info/?l=u-boot&m=156427088018689&w=2
Gen2 2GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 2 GiB PMIC: RK8050 (on=0x40, off=0x01) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 15 ms (10.8 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 14 ms (11.5 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB without patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 Trying to boot from MMC2 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 {
u-boot,dm-spl;+};
+&pinctrl {
u-boot,dm-spl;+};
+&sdmmc0m1_gpio {
u-boot,dm-spl;+};
+&pcfg_pull_up_4ma {
u-boot,dm-spl;+};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd {
u-boot,dm-spl;+}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned- clock- rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
-- With best regards, Matwey V. Kornilov
On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
вт, 19 мая 2020 г. в 17:30, Kurt Miller kurt@intricatesoftware.com:
On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
Thanks. Have you already checked it on gen2? I think I have gen2 board to test.
Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Hi Matwey,
Hi Kurt,
Thank you for testing the patch. Hmm, are you building with ATF 2.3?
You are right here, I was testing with ATF 2.1, while ATF 2.3 works correctly. First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE to 0x40000"). I suppose, it is worth to mention in the commit message for this patch. What do you think?
This was already mentioned in commits such as
c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL 4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399 6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs 006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR
ChenYu
I’m booting from the uSD without an eMMC installed. Are you booting from the eMMC or have one installed?
I'm booting from uSD without eMMC installed also.
Here are some background emails related to the gen3 freeze. I also included the output for when gen3 fails below and the output for my gen2 2gb and gen3 4gb with the patch.
https://marc.info/?l=u-boot&m=158550521101881&w=2 https://marc.info/?l=u-boot&m=156427088018689&w=2
Gen2 2GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 2 GiB PMIC: RK8050 (on=0x40, off=0x01) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 15 ms (10.8 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 14 ms (11.5 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB without patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 Trying to boot from MMC2 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com: > > > > > Use the same approach as ROC-RK3328-CC which enables SPL GPIO, > pinctl and regulator support. This allows the gen3 board to > boot through SPL and does not break gen2 in the process. > > Signed-off-by: Kurt Miller kurt@intricatesoftware.com > --- > > arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ > configs/rock64-rk3328_defconfig | 7 ++++++- > 2 files changed, 27 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > index 8318bf4e60..f076075076 100644 > --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi > +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > @@ -11,6 +11,22 @@ > }; > }; > > +&gpio0 { > + u-boot,dm-spl; > +}; > + > +&pinctrl { > + u-boot,dm-spl; > +}; > + > +&sdmmc0m1_gpio { > + u-boot,dm-spl; > +}; > + > +&pcfg_pull_up_4ma { > + u-boot,dm-spl; > +}; > + > &usb_host0_xhci { > vbus-supply = <&vcc_host_5v>; > status = "okay"; > @@ -25,3 +41,8 @@ > /delete-property/ regulator-always-on; > /delete-property/ regulator-boot-on; > }; > + > +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ > +&vcc_sd { > + u-boot,dm-spl; > +}; > diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig > index 7d096d38c6..0bc2198f5c 100644 > --- a/configs/rock64-rk3328_defconfig > +++ b/configs/rock64-rk3328_defconfig > @@ -1,6 +1,7 @@ > CONFIG_ARM=y > CONFIG_ARCH_ROCKCHIP=y > CONFIG_SYS_TEXT_BASE=0x00200000 > +CONFIG_SPL_GPIO_SUPPORT=y > CONFIG_ENV_OFFSET=0x3F8000 > CONFIG_ROCKCHIP_RK3328=y > CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y > @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > CONFIG_TPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_I2C_SUPPORT=y > +CONFIG_SPL_POWER_SUPPORT=y > CONFIG_SPL_ATF=y > CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > CONFIG_CMD_BOOTZ=y > @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y > CONFIG_SPL_OF_CONTROL=y > CONFIG_TPL_OF_CONTROL=y > CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" > -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned- > clock- > rates assigned-clock-parents" > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock- > parents" > CONFIG_TPL_OF_PLATDATA=y > CONFIG_ENV_IS_IN_MMC=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y > CONFIG_SPL_PINCTRL=y > CONFIG_DM_PMIC=y > CONFIG_PMIC_RK8XX=y > +CONFIG_SPL_DM_REGULATOR=y > CONFIG_REGULATOR_PWM=y > +CONFIG_SPL_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_FIXED=y > CONFIG_REGULATOR_RK8XX=y > CONFIG_PWM_ROCKCHIP=y > -- > 2.26.0 >
-- With best regards, Matwey V. Kornilov
On Wed, 2020-05-20 at 16:30 +0800, Chen-Yu Tsai wrote:
On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
вт, 19 мая 2020 г. в 17:30, Kurt Miller kurt@intricatesoftware.com:
On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote: > > > > Thanks. Have you already checked it on gen2? I think I have gen2 board to test. Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well.
Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Hi Matwey,
Hi Kurt,
Thank you for testing the patch. Hmm, are you building with ATF 2.3?
You are right here, I was testing with ATF 2.1, while ATF 2.3 works correctly. First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE to 0x40000").
Great! I did some more gen2 testing as well. Booting with just eMMC works and with both eMMC and uSD also works for me.
I suppose, it is worth to mention in the commit message for this patch. What do you think?
This was already mentioned in commits such as
c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL 4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399 6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs 006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR
ChenYu
Yes this changed back in the 2020.01 release time-frame. If the commit message needs improvement, please suggest what you want and I can resubmit the patch.
Thanks, -Kurt
I’m booting from the uSD without an eMMC installed. Are you booting from the eMMC or have one installed?
I'm booting from uSD without eMMC installed also.
Here are some background emails related to the gen3 freeze. I also included the output for when gen3 fails below and the output for my gen2 2gb and gen3 4gb with the patch.
https://marc.info/?l=u-boot&m=158550521101881&w=2 https://marc.info/?l=u-boot&m=156427088018689&w=2
Gen2 2GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 2 GiB PMIC: RK8050 (on=0x40, off=0x01) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 15 ms (10.8 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 14 ms (11.5 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB without patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 Trying to boot from MMC2 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
> > > > > ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com: > > > > > > > > > > > > Use the same approach as ROC-RK3328-CC which enables SPL GPIO, > > pinctl and regulator support. This allows the gen3 board to > > boot through SPL and does not break gen2 in the process. > > > > Signed-off-by: Kurt Miller kurt@intricatesoftware.com > > --- > > > > arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ > > configs/rock64-rk3328_defconfig | 7 ++++++- > > 2 files changed, 27 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > index 8318bf4e60..f076075076 100644 > > --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > @@ -11,6 +11,22 @@ > > }; > > }; > > > > +&gpio0 { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl { > > + u-boot,dm-spl; > > +}; > > + > > +&sdmmc0m1_gpio { > > + u-boot,dm-spl; > > +}; > > + > > +&pcfg_pull_up_4ma { > > + u-boot,dm-spl; > > +}; > > + > > &usb_host0_xhci { > > vbus-supply = <&vcc_host_5v>; > > status = "okay"; > > @@ -25,3 +41,8 @@ > > /delete-property/ regulator-always-on; > > /delete-property/ regulator-boot-on; > > }; > > + > > +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ > > +&vcc_sd { > > + u-boot,dm-spl; > > +}; > > diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig > > index 7d096d38c6..0bc2198f5c 100644 > > --- a/configs/rock64-rk3328_defconfig > > +++ b/configs/rock64-rk3328_defconfig > > @@ -1,6 +1,7 @@ > > CONFIG_ARM=y > > CONFIG_ARCH_ROCKCHIP=y > > CONFIG_SYS_TEXT_BASE=0x00200000 > > +CONFIG_SPL_GPIO_SUPPORT=y > > CONFIG_ENV_OFFSET=0x3F8000 > > CONFIG_ROCKCHIP_RK3328=y > > CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y > > @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y > > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > CONFIG_TPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_I2C_SUPPORT=y > > +CONFIG_SPL_POWER_SUPPORT=y > > CONFIG_SPL_ATF=y > > CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > > CONFIG_CMD_BOOTZ=y > > @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y > > CONFIG_SPL_OF_CONTROL=y > > CONFIG_TPL_OF_CONTROL=y > > CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" > > -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks > > assigned- > > clock- > > rates assigned-clock-parents" > > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned- > > clock- > > parents" > > CONFIG_TPL_OF_PLATDATA=y > > CONFIG_ENV_IS_IN_MMC=y > > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y > > CONFIG_SPL_PINCTRL=y > > CONFIG_DM_PMIC=y > > CONFIG_PMIC_RK8XX=y > > +CONFIG_SPL_DM_REGULATOR=y > > CONFIG_REGULATOR_PWM=y > > +CONFIG_SPL_DM_REGULATOR_FIXED=y > > CONFIG_DM_REGULATOR_FIXED=y > > CONFIG_REGULATOR_RK8XX=y > > CONFIG_PWM_ROCKCHIP=y > > -- > > 2.26.0 > >
-- With best regards, Matwey V. Kornilov
ср, 20 мая 2020 г. в 20:41, Kurt Miller kurt@intricatesoftware.com:
On Wed, 2020-05-20 at 16:30 +0800, Chen-Yu Tsai wrote:
On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov matwey.kornilov@gmail.com wrote:
вт, 19 мая 2020 г. в 17:30, Kurt Miller kurt@intricatesoftware.com:
On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
вт, 19 мая 2020 г. в 01:06, Kurt Miller lists@intricatesoftware.com:
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote: > > > On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote: > > > > > > > > Thanks. Have you already checked it on gen2? I think I have gen2 board to test. > Yes, I have both gen3 and gen2 boards. gen2 continues to work > with this patch as well. Hi Matwey,
Hi Kurt,
Sorry for the late reply. I've just managed to apply you patch on top of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 +0300) Trying to boot from MMC1 [and nothing else happens here]
What do you think may be the reason?
Hi Matwey,
Hi Kurt,
Thank you for testing the patch. Hmm, are you building with ATF 2.3?
You are right here, I was testing with ATF 2.1, while ATF 2.3 works correctly. First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE to 0x40000").
Great! I did some more gen2 testing as well. Booting with just eMMC works and with both eMMC and uSD also works for me.
I suppose, it is worth to mention in the commit message for this patch. What do you think?
This was already mentioned in commits such as
c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL 4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399 6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs 006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR
ChenYu
Yes this changed back in the 2020.01 release time-frame. If the commit message needs improvement, please suggest what you want and I can resubmit the patch.
Well, I think it is fine anyway.
Thanks, -Kurt
I’m booting from the uSD without an eMMC installed. Are you booting from the eMMC or have one installed?
I'm booting from uSD without eMMC installed also.
Here are some background emails related to the gen3 freeze. I also included the output for when gen3 fails below and the output for my gen2 2gb and gen3 4gb with the patch.
https://marc.info/?l=u-boot&m=158550521101881&w=2 https://marc.info/?l=u-boot&m=156427088018689&w=2
Gen2 2GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 2 GiB PMIC: RK8050 (on=0x40, off=0x01) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 15 ms (10.8 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB with patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400) Trying to boot from MMC1 NOTICE: BL31: v2.3():2.3 NOTICE: BL31: Built : 11:30:57, May 15 2020 NOTICE: BL31:Rockchip release version: v1.2 INFO: ARM GICv2 driver initialized INFO: plat_rockchip_pmu_init: pd status 0xe INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9
U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
Model: Pine64 Rock64 DRAM: 4 GiB PMIC: RK8050 (on=0x40, off=0x00) MMC: mmc@ff500000: 1, mmc@ff520000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff130000 Out: serial@ff130000 Err: serial@ff130000 Model: Pine64 Rock64 Net: eth0: ethernet@ff540000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found EFI removable media binary efi/boot/bootaa64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@ff500000.blk... ** Unrecognized filesystem type ** Card did not respond to voltage select! Scanning disk mmc@ff520000.blk... Disk mmc@ff520000.blk not ready Found 3 disks BootOrder not defined EFI boot manager: Cannot load any image 169176 bytes read in 14 ms (11.5 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC disks: sd0*
Gen3 4GB without patch:
U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41) LPDDR3, 800MHz BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB Trying to boot from BOOTROM Returning to boot ROM...
U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 10:05:41 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 Trying to boot from MMC2 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Is there anything else you need to complete your review of this patch?
Thanks, -Kurt
> > > > > > > > > > > > > ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com: > > > > > > > > > > > > > > > > > > Use the same approach as ROC-RK3328-CC which enables SPL GPIO, > > > pinctl and regulator support. This allows the gen3 board to > > > boot through SPL and does not break gen2 in the process. > > > > > > Signed-off-by: Kurt Miller kurt@intricatesoftware.com > > > --- > > > > > > arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ > > > configs/rock64-rk3328_defconfig | 7 ++++++- > > > 2 files changed, 27 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > > index 8318bf4e60..f076075076 100644 > > > --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > > +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi > > > @@ -11,6 +11,22 @@ > > > }; > > > }; > > > > > > +&gpio0 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&pinctrl { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sdmmc0m1_gpio { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&pcfg_pull_up_4ma { > > > + u-boot,dm-spl; > > > +}; > > > + > > > &usb_host0_xhci { > > > vbus-supply = <&vcc_host_5v>; > > > status = "okay"; > > > @@ -25,3 +41,8 @@ > > > /delete-property/ regulator-always-on; > > > /delete-property/ regulator-boot-on; > > > }; > > > + > > > +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ > > > +&vcc_sd { > > > + u-boot,dm-spl; > > > +}; > > > diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig > > > index 7d096d38c6..0bc2198f5c 100644 > > > --- a/configs/rock64-rk3328_defconfig > > > +++ b/configs/rock64-rk3328_defconfig > > > @@ -1,6 +1,7 @@ > > > CONFIG_ARM=y > > > CONFIG_ARCH_ROCKCHIP=y > > > CONFIG_SYS_TEXT_BASE=0x00200000 > > > +CONFIG_SPL_GPIO_SUPPORT=y > > > CONFIG_ENV_OFFSET=0x3F8000 > > > CONFIG_ROCKCHIP_RK3328=y > > > CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y > > > @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y > > > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > > CONFIG_TPL_SYS_MALLOC_SIMPLE=y > > > CONFIG_SPL_STACK_R=y > > > +CONFIG_SPL_I2C_SUPPORT=y > > > +CONFIG_SPL_POWER_SUPPORT=y > > > CONFIG_SPL_ATF=y > > > CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > > > CONFIG_CMD_BOOTZ=y > > > @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y > > > CONFIG_SPL_OF_CONTROL=y > > > CONFIG_TPL_OF_CONTROL=y > > > CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" > > > -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks > > > assigned- > > > clock- > > > rates assigned-clock-parents" > > > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned- > > > clock- > > > parents" > > > CONFIG_TPL_OF_PLATDATA=y > > > CONFIG_ENV_IS_IN_MMC=y > > > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > > @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y > > > CONFIG_SPL_PINCTRL=y > > > CONFIG_DM_PMIC=y > > > CONFIG_PMIC_RK8XX=y > > > +CONFIG_SPL_DM_REGULATOR=y > > > CONFIG_REGULATOR_PWM=y > > > +CONFIG_SPL_DM_REGULATOR_FIXED=y > > > CONFIG_DM_REGULATOR_FIXED=y > > > CONFIG_REGULATOR_RK8XX=y > > > CONFIG_PWM_ROCKCHIP=y > > > -- > > > 2.26.0 > > >
-- With best regards, Matwey V. Kornilov
ср, 13 мая 2020 г. в 22:55, Kurt Miller kurt@intricatesoftware.com:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
Acked-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++- 2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 {
u-boot,dm-spl;+};
+&pinctrl {
u-boot,dm-spl;+};
+&sdmmc0m1_gpio {
u-boot,dm-spl;+};
+&pcfg_pull_up_4ma {
u-boot,dm-spl;+};
&usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd {
u-boot,dm-spl;+}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -- 2.26.0
On 2020/5/14 上午3:55, Kurt Miller wrote:
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller kurt@intricatesoftware.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ configs/rock64-rk3328_defconfig | 7 ++++++-
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; };
+&gpio0 {
- u-boot,dm-spl;
+};
+&pinctrl {
- u-boot,dm-spl;
+};
+&sdmmc0m1_gpio {
- u-boot,dm-spl;
+};
+&pcfg_pull_up_4ma {
- u-boot,dm-spl;
+};
- &usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay";
@@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; };
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd {
- u-boot,dm-spl;
+}; diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 7d096d38c6..0bc2198f5c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y
participants (5)
-
Chen-Yu Tsai -
Kever Yang -
Kurt Miller -
Kurt Miller -
Matwey V. Kornilov