[U-Boot] [PATCH] Add support for Indefia Nimbus Cloud Board
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
--- CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/indefia/nimbuscloud/Makefile | 40 ++++++ board/indefia/nimbuscloud/config.mk | 3 + board/indefia/nimbuscloud/flash.c | 225 +++++++++++++++++++++++++++++++ board/indefia/nimbuscloud/nimbuscloud.c | 167 +++++++++++++++++++++++ board/indefia/nimbuscloud/u-boot.lds | 72 ++++++++++ include/configs/nimbuscloud.h | 180 ++++++++++++++++++++++++ 10 files changed, 699 insertions(+), 0 deletions(-) create mode 100644 board/indefia/nimbuscloud/Makefile create mode 100644 board/indefia/nimbuscloud/config.mk create mode 100644 board/indefia/nimbuscloud/flash.c create mode 100644 board/indefia/nimbuscloud/nimbuscloud.c create mode 100644 board/indefia/nimbuscloud/u-boot.lds create mode 100644 include/configs/nimbuscloud.h
diff --git a/CREDITS b/CREDITS index 2471029..69a9dde 100644 --- a/CREDITS +++ b/CREDITS @@ -196,6 +196,10 @@ N: Anne-Sophie Harnois E: Anne-Sophie.Harnois@nextream.fr D: Port to Walnut405 board
+N: Semih Hazar +E: semih.hazar@indefia.com +D: Nimbus Cloud board support + N: Andreas Heppel E: aheppel@sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d..0764ee9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -880,6 +880,10 @@ Hans-Christian Egtvedt hans-christian.egtvedt@atmel.com
FAVR-32-EZKIT AT32AP7000
+Semih Hazar semih.hazar@indefia.com + + NIMBUSCLOUD AT32AP7000 + Mark Jackson mpfj@mimc.co.uk
MIMC200 AT32AP7000 diff --git a/MAKEALL b/MAKEALL index ab1bb6f..fde90ee 100755 --- a/MAKEALL +++ b/MAKEALL @@ -859,6 +859,7 @@ LIST_avr32=" \ favr-32-ezkit \ hammerhead \ mimc200 \ + nimbuscloud \ "
######################################################################### diff --git a/Makefile b/Makefile index 536ccb3..ea16786 100644 --- a/Makefile +++ b/Makefile @@ -3595,6 +3595,9 @@ hammerhead_config : unconfig mimc200_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
+nimbuscloud_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap nimbuscloud indefia at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/indefia/nimbuscloud/Makefile b/board/indefia/nimbuscloud/Makefile new file mode 100644 index 0000000..5ddc351 --- /dev/null +++ b/board/indefia/nimbuscloud/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008-2009 Indefia +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/indefia/nimbuscloud/config.mk b/board/indefia/nimbuscloud/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/indefia/nimbuscloud/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/indefia/nimbuscloud/flash.c b/board/indefia/nimbuscloud/flash.c new file mode 100644 index 0000000..04e6974 --- /dev/null +++ b/board/indefia/nimbuscloud/flash.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2009 Indefia + * + * Based on work (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/arch/cacheflush.h> +#include <asm/io.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0x90, flash); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + gd->bd->bi_flashsize = CONFIG_SYS_FLASH_SIZE; + gd->bd->bi_flashoffset = _edata - _text; + + flash_info[0].size = CONFIG_SYS_FLASH_SIZE; + flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + + flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); + + // First 8 sectors are 8k + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + + // Remaing are 64k + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CONFIG_SYS_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + if ( info->flash_id == 0x1f88c5 ) { + printf("Atmel AT49BV320C"); + } else if ( info->flash_id == 0x1f90c5 ) { + printf("Atmel AT49BV320D"); + } else if ( info->flash_id == 0x1f90c3 ) { + printf("Atmel AT49BV160D"); + } else { + printf("Manufacturer/Device ID: 0x%02x/0x%04x", + info->flash_id >> 16, info->flash_id & FLASH_TYPEMASK); + } + + printf(", Size: %ld KB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + uint16_t *fb, *sb; + unsigned int i; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + sb = (uint16_t *)uncached(info->start[i]); + printf("Erasing sector %d %p\n", i, sb); + + flags = disable_interrupts(); + + /* Unlock sector */ + writew(0x50, fb); // Clear status bit + writew(0x60, fb); // Sector unlock + writew(0xd0, sb); // confirm + + while ( ! (readw(fb) & 0x80) ); + + /* Erase sector */ + writew(0x50, fb); // Clear status bit + writew(0x20, fb); // Sector erase + writew(0xd0, sb); // confirm + + /* Wait for completion */ + do { + status = readw(fb); + } while (!(status & 0x80)); + + writew(0xff, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0x80) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + return ERR_PROG_ERROR; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0x40, base); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + do { + status = readw(p); + } while (!(status & 0x80)); + + writew(0xff, base); + readw(base); + + status= readw(p); + if (status != word) { + printf("Flash write error at address 0x%p: 0x%02x\n", + p, status); + printf("Wrote %04x Read %04x\n", word, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (flags) + enable_interrupts(); + + return ret; +} + diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c new file mode 100644 index 0000000..9027d72 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Based on atngw100.c (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/portmux.h> +#include <netdev.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +static u8 read_configsw(void) { + u8 configsw = 0; + + if ( ! gpio_get_value(GPIO_PIN_PB(13)) ) + configsw |= 1; + if ( ! gpio_get_value(GPIO_PIN_PB(14)) ) + configsw |= 2; + if ( ! gpio_get_value(GPIO_PIN_PB(15)) ) + configsw |= 4; + if ( ! gpio_get_value(GPIO_PIN_PB(16)) ) + configsw |= 8; + + return configsw; +} + + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + + /* Enable GPIO on config swicthes */ + portmux_select_gpio(PORTMUX_PORT_B, (1 << 13) | (1 << 14) | (1 << 15) | (1 << 16), + PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif + + if ( (read_configsw() & 1) == 1 ) { + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + printf("Indefia Nimbus Cloud - CPU@%d MHz, SDRAM %d MiB @%d MHz\n", + (int) (get_cpu_clk_rate()/1000000), (int) (actual_size >> 20), (int) (get_sdram_clk_rate()/1000000)); + + return actual_size; +} + +int misc_init_r(void) +{ + char buf[3]; + u8 configsw; + + configsw = read_configsw(); + + if ( (configsw & 1) == 1 ) { + setenv("bootdelay", "0"); + } + + sprintf(buf, "%d", configsw); + setenv("configsw", buf); + + return 0; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + return 0; +} + +#ifdef CONFIG_CMD_NET + +extern int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value); +extern int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value); + +int board_eth_init(bd_t *bi) +{ + u16 val; + + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + + /* PHY is in power down state initially. + Exit power-down state, write 1 to MICR (0x11) + */ + macb_miiphy_write("macb0", 1, 0x11, 0x01); + + /* Configure LEDs, read and modify PHYCR (0x19) + Left: link, right: activity + */ + macb_miiphy_read("macb0", 1, 0x19, &val); + val |= 1<<5; + macb_miiphy_write("macb0", 1, 0x19, val); + + return 0; +} +#endif + diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds new file mode 100644 index 0000000..a7243f2 --- /dev/null +++ b/board/indefia/nimbuscloud/u-boot.lds @@ -0,0 +1,72 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/nimbuscloud.h b/include/configs/nimbuscloud.h new file mode 100644 index 0000000..e12237b --- /dev/null +++ b/include/configs/nimbuscloud.h @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Configuration settings for Indefia Nimbus Cloud + * + * Based on atngw100.h (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_NIMBUSCLOUD 1 +#define CONFIG_ATNGW100 1 /* This is just for testing */ + +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 180 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_SYS_OSC0_HZ 25000000 +#define CONFIG_SYS_PLL0_DIV 5 +#define CONFIG_SYS_PLL0_MUL 36 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 // or 20 ? +#define CONFIG_SYS_CLKDIV_CPU 0 +#define CONFIG_SYS_CLKDIV_HSB 1 +#define CONFIG_SYS_CLKDIV_PBA 2 +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x05 + +#define CONFIG_USART1 1 + +/* User serviceable stuff */ + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock4 rootfstype=jffs2 fbmem=1200k" +#define CONFIG_BOOTCOMMAND \ + "cp.b 0x20000 0x90400000 0x180000; bootm 0x90400000" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +/* #define CONFIG_CMD_SF */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_SPI 1 + +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 39 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 65536 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 + +#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#define CONFIG_CMD_MII 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_DISABLE_CONSOLE 1 /* disable console */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ + + +#endif /* __CONFIG_H */
Hi,
I had sent a few patches almost a month ago about a new AVR32 board, but couldn't get a reply from anyone.
I'd appreciate if we can get these patches into the upcoming release.
Regards, Semih Hazar
Dear Semih Hazar,
In message 4B2A2E3A.4070908@indefia.com you wrote:
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
...
diff --git a/board/indefia/nimbuscloud/flash.c b/board/indefia/nimbuscloud/flash.c new file mode 100644 index 0000000..04e6974 --- /dev/null +++ b/board/indefia/nimbuscloud/flash.c
Is ther e a chance to do without this file and use the CFI driver instead?
+unsigned long flash_init(void) +{
- unsigned long addr;
- unsigned int i;
- gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- gd->bd->bi_flashsize = CONFIG_SYS_FLASH_SIZE;
- gd->bd->bi_flashoffset = _edata - _text;
- flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
- flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
- // First 8 sectors are 8k
Please do not use C++ comments.
- for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
flash_info[0].start[i] = addr;- // Remaing are 64k
Ditto. Please fix globally.
+int board_early_init_f(void) +{
- /* Enable SDRAM in the EBI mux */
- hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
- portmux_enable_usart1(PORTMUX_DRIVE_MIN);
- /* Enable GPIO on config swicthes */
- portmux_select_gpio(PORTMUX_PORT_B, (1 << 13) | (1 << 14) | (1 << 15) | (1 << 16),
Line too long. Please fix globally.
+phys_size_t initdram(int board_type) +{
- unsigned long expected_size;
- unsigned long actual_size;
- void *sdram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
- expected_size = sdram_init(sdram_base, &sdram_config);
- actual_size = get_ram_size(sdram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
- if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",actual_size >> 20, expected_size >> 20);- printf("Indefia Nimbus Cloud - CPU@%d MHz, SDRAM %d MiB @%d MHz\n",
(int) (get_cpu_clk_rate()/1000000), (int) (actual_size >> 20), (int) (get_sdram_clk_rate()/1000000));
Line too long. And please use strmhz() to print clock frequencies.
Um... this print does not belong here at all. CPU init messages and board initi messages have no place in initdram() at all.
diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds new file mode 100644 index 0000000..a7243f2 --- /dev/null +++ b/board/indefia/nimbuscloud/u-boot.lds
Do you really need a board specific linker script?
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de "The computer programmer is a creator of universes for which he alone is responsible. Universes of virtually unlimited complexity can be created in the form of computer programs." - Joseph Weizenbaum, _Computer Power and Human Reason_
Dear Wolfgang,
Please find my answers below.
Is ther e a chance to do without this file and use the CFI driver instead?
There's currently a problem with the CFI driver in AVR32 platform. There was a long discussion about it, but a solution was not available. If that issue is solved, I can submit a patch to change this to use CFI.
- // First 8 sectors are 8k
Please do not use C++ comments.
These are fixed.
- /* Enable GPIO on config swicthes */
- portmux_select_gpio(PORTMUX_PORT_B, (1 << 13) | (1 << 14) | (1 << 15) | (1 << 16),
Line too long. Please fix globally.
Fixed.
Line too long. And please use strmhz() to print clock frequencies.
Um... this print does not belong here at all. CPU init messages and board initi messages have no place in initdram() at all.
Removed it.
diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds new file mode 100644 index 0000000..a7243f2 --- /dev/null +++ b/board/indefia/nimbuscloud/u-boot.lds
Do you really need a board specific linker script?
The README file says to put a u-boot.lds file for a new board and I did so. I also looked at the other AVR32 boards and they all also have it. If there's another way, I can change it.
I'm sending the revised patch in another mail.
Best regards, Semih Hazar
Dear Semih Hazar,
In message 4B5852FF.5080709@indefia.com you wrote:
Is ther e a chance to do without this file and use the CFI driver instead?
There's currently a problem with the CFI driver in AVR32 platform. There was a long discussion about it, but a solution was not available. If that issue is solved, I can submit a patch to change this to use CFI.
Well, if we accept that everybody post-pones the real solution by adding workarounds instead, then chances are minimal that the real problem will ever be fixed.
I therefor tend to NAK this custom driver and insist on using the CFI driver for CFI conformant flashes.
Best regards,
Wolfgang Denk
Dear Wolfgang,
The problem with AVR32 and the CFI flash driver has a few possible solutions as noted by Haavard Skinnemoen in the email [1]. The only thing I can do is to go with the first alternative and set the flash address as the virtual address which is cache-disabled and works flawless with the CFI driver.
That solution can also be used by other AVR32 boards, and I _think_ it also solves the JFFS2 scanning problem which was mentioned in [2].
The only ugly thing (for me) is when using the CFI commands, the flash addresses has to be shifted by 0xa0000000. (e.g. copy to flash at 0x1000 must be written as cp.b <source> 0xa0001000 <size>).
Please find the revised patch in a separate email, which also includes a new header file per your comments in the other email.
Best Regards, Semih Hazar
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg20911.html [2] http://lists.avr32linux.org/pipermail/u-boot/2009-August/000457.html
On 2/4/10 7:13 PM, Semih Hazar wrote:
Please find the revised patch in a separate email, which also includes a new header file per your comments in the other email.
Dear Wolfgang,
It's been a while over this issue, so I wanted to ask. Did you have time to look at this?
Regards, Semih
Dear Semih Hazar,
In message 4B8BCB49.4000104@indefia.com you wrote:
It's been a while over this issue, so I wanted to ask. Did you have time to look at this?
I looked at it now. Please see my previous message.
Best regards,
Wolfgang Denk
Dear Semih Hazar,
In message 4B6B004C.1010507@indefia.com you wrote:
The problem with AVR32 and the CFI flash driver has a few possible solutions as noted by Haavard Skinnemoen in the email [1]. The only thing I can do is to go with the first alternative and set the flash address as the virtual address which is cache-disabled and works flawless with the CFI driver.
That solution can also be used by other AVR32 boards, and I _think_ it also solves the JFFS2 scanning problem which was mentioned in [2].
The only ugly thing (for me) is when using the CFI commands, the flash addresses has to be shifted by 0xa0000000. (e.g. copy to flash at 0x1000 must be written as cp.b <source> 0xa0001000 <size>).
I really dislike such an approach. From the user interface point of view this is unacceptable to me.
My understanding is that there are only three pretty local areas where uncached access to the flash is needed: initialization (i. e. probing and querying), erasing, and programming.
So it should be possible to switch off caching when entering these functions, and turn it on again upon return. Eventually other architectures might want to implement such a feature, too, so adding generic infrastructure to do that makes sense to me.
Stefan might want to comment here, too ?
In worst case (if you really cannot change the caching attributes for the flash memory region on the fly) it might even be possible to add some "address offset" which is strictly internal to the CFI driver and used for the nn-cached accesses. But in now way any of this should be visible to the end user on the command line.
Best regards,
Wolfgang Denk
Hi Wolfgang,
On Sunday 21 March 2010 17:34:50 Wolfgang Denk wrote:
The problem with AVR32 and the CFI flash driver has a few possible solutions as noted by Haavard Skinnemoen in the email [1]. The only thing I can do is to go with the first alternative and set the flash address as the virtual address which is cache-disabled and works flawless with the CFI driver.
That solution can also be used by other AVR32 boards, and I _think_ it also solves the JFFS2 scanning problem which was mentioned in [2].
The only ugly thing (for me) is when using the CFI commands, the flash addresses has to be shifted by 0xa0000000. (e.g. copy to flash at 0x1000 must be written as cp.b <source> 0xa0001000 <size>).
I really dislike such an approach. From the user interface point of view this is unacceptable to me.
My understanding is that there are only three pretty local areas where uncached access to the flash is needed: initialization (i. e. probing and querying), erasing, and programming.
Yes. If I don't miss anything then this is correct.
So it should be possible to switch off caching when entering these functions, and turn it on again upon return. Eventually other architectures might want to implement such a feature, too, so adding generic infrastructure to do that makes sense to me.
Stefan might want to comment here, too ?
Currently I see 2 approaches to support NOR FLASH mapped via a cached memory region in the common CFI driver:
a) Use write-through cache support (if possible) and add required cache handling calls (invalidate and flush) at the "correct locations" (TM) in the CFI driver.
b) Temporarily disable cache in the NOR FLASH memory region before using the CFI driver. This could be done in some generic places (like Wolfgang mentioned above) and should not require any additional user action/input.
Not all platforms will support both alternatives.
Semih, would one of the above options be possible for your platform? Does the AVR support write-through cache? Is it possible to enable such a caching attribute selectively for the NOR FLASH region?
BTW: It might be that I start working on such a cached NOR FLASH support in the next few weeks. My current preference is option a) right now.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
On 3/22/10 11:23 AM, Stefan Roese wrote:
Currently I see 2 approaches to support NOR FLASH mapped via a cached memory region in the common CFI driver:
a) Use write-through cache support (if possible) and add required cache handling calls (invalidate and flush) at the "correct locations" (TM) in the CFI driver.
b) Temporarily disable cache in the NOR FLASH memory region before using the CFI driver. This could be done in some generic places (like Wolfgang mentioned above) and should not require any additional user action/input.
Not all platforms will support both alternatives.
Semih, would one of the above options be possible for your platform? Does the AVR support write-through cache? Is it possible to enable such a caching attribute selectively for the NOR FLASH region?
I'm not the expert on the AVR32 memory architecture, but as far as I know it goes like this for the NOR Flash area: The Flash is mapped at the physical address at 0x0 and this region is cached. This same memory region is also mapped at 0xa000000 which is not cached.
Quoting directly from the architecture datasheet: "The mapping between virtual addresses and physical addresses is therefore implemented by clearing of MSBs in the virtual address."
In other words, if you want uncached access to the Flash, read/write at 0xa0000000, otherwise use 0x0.
It's not possible to simply disable caching for 0x0 region. It can be achieved using paging, but it's more complicated.
BTW: It might be that I start working on such a cached NOR FLASH support in the next few weeks. My current preference is option a) right now.
If we go with Stefan's option a, then we need to put some #ifdefs or function calls in the flash code to enable/disable cache, right? Since caching can't be enabled/disabled in AVR32, the solution Haavard proposed long time ago seems a good one, considering that you're now willing to integrate cached flash support. It was a (un)map_physmem function which returns a new address for the cached/uncached region.
I think all possible scenarios have been talked in the past. I just wanted to submit my patch, since it was way long overdue. If we can't move any further, Wolfgang, I'd like you to accept this patch as it is.
PS: Related discussions can be seen in this long thread: http://www.mail-archive.com/u-boot@lists.denx.de/msg20778.html
Best Regards, Semih Hazar
Dear Semih Hazar,
In message 4BA8FD4E.9080008@indefia.com you wrote:
I'm not the expert on the AVR32 memory architecture, but as far as I know it goes like this for the NOR Flash area: The Flash is mapped at the physical address at 0x0 and this region is cached. This same memory region is also mapped at 0xa000000 which is not cached.
We are aware of this situation, but that was not the actual question.
It's not possible to simply disable caching for 0x0 region. It can be achieved using paging, but it's more complicated.
I have three specific questions:
* Is it technically possible to set up the AVR32 memory controller such that the memory region at 0x0 is mapped uncached?
I am asking if it is possible to configure a system such that cahces are completely turned off.
* Assuming this is possible, then is there a way to reprogram (in the running system) the AVR32 memory controller from one mode (cached) to the other one (uncached) ?
* Does the AVR32 memory controller support anything like a "write-through" cache mode?
If we go with Stefan's option a, then we need to put some #ifdefs or function calls in the flash code to enable/disable cache, right?
Function calls, yes. But ideally we can use write-through, and I expect that we eventually might kept this mode always switched on.
Since caching can't be enabled/disabled in AVR32, the solution Haavard
I still don't buy this statement in this absolute form.
I think all possible scenarios have been talked in the past. I just wanted to submit my patch, since it was way long overdue. If we can't move any further, Wolfgang, I'd like you to accept this patch as it is.
Sorry, but I don't think this is a good solution yet.
Best regards,
Wolfgang Denk
Hi Wolfgang, Hi Semih,
On Tuesday 23 March 2010 21:01:12 Wolfgang Denk wrote:
It's not possible to simply disable caching for 0x0 region. It can be achieved using paging, but it's more complicated.
I have three specific questions:
Is it technically possible to set up the AVR32 memory controller such that the memory region at 0x0 is mapped uncached?
I am asking if it is possible to configure a system such that cahces are completely turned off.
Assuming this is possible, then is there a way to reprogram (in the running system) the AVR32 memory controller from one mode (cached) to the other one (uncached) ?
Does the AVR32 memory controller support anything like a "write-through" cache mode?
I had a quick glance at the AVR32 architecture manual. And it really seems that 2GB starting at address 0 are *always* cached. What I couldn't find out quickly is, if it is possible to turn on write-though support for this address range. Perhaps an AVR32 expert could enlighten us here?
If we go with Stefan's option a, then we need to put some #ifdefs or function calls in the flash code to enable/disable cache, right?
Function calls, yes. But ideally we can use write-through, and I expect that we eventually might kept this mode always switched on.
Option a) is using write-though, so the cache should always stay on in this mode (used in combination with cache flush and invalidate calls). Option b) is the alternative with temporarily disabling the caches for the erase/write operations. But since disabling cache isn't possible on AVR32, this isn't an option here.
This leads us back to these questions:
- Is it possible to turn on write-though support for the memory area starting at 0?
- Is it possible to flush and/or invalidate address ranges in this area?
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
--- CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/indefia/nimbuscloud/Makefile | 40 +++++++ board/indefia/nimbuscloud/config.mk | 3 + board/indefia/nimbuscloud/nimbuscloud.c | 165 +++++++++++++++++++++++++++ board/indefia/nimbuscloud/nimbuscloud.h | 8 ++ board/indefia/nimbuscloud/u-boot.lds | 72 ++++++++++++ include/configs/nimbuscloud.h | 184 +++++++++++++++++++++++++++++++ 10 files changed, 484 insertions(+), 0 deletions(-)
diff --git a/CREDITS b/CREDITS index 2471029..69a9dde 100644 --- a/CREDITS +++ b/CREDITS @@ -196,6 +196,10 @@ N: Anne-Sophie Harnois E: Anne-Sophie.Harnois@nextream.fr D: Port to Walnut405 board
+N: Semih Hazar +E: semih.hazar@indefia.com +D: Nimbus Cloud board support + N: Andreas Heppel E: aheppel@sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] diff --git a/MAINTAINERS b/MAINTAINERS index e8ba4bc..9202137 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -881,6 +881,10 @@ Hans-Christian Egtvedt hans-christian.egtvedt@atmel.com
FAVR-32-EZKIT AT32AP7000
+Semih Hazar semih.hazar@indefia.com + + NIMBUSCLOUD AT32AP7000 + Mark Jackson mpfj@mimc.co.uk
MIMC200 AT32AP7000 diff --git a/MAKEALL b/MAKEALL index 15e93cf..6ee30ec 100755 --- a/MAKEALL +++ b/MAKEALL @@ -866,6 +866,7 @@ LIST_avr32=" \ favr-32-ezkit \ hammerhead \ mimc200 \ + nimbuscloud \ "
######################################################################### diff --git a/Makefile b/Makefile index 69b963f..8c4e453 100644 --- a/Makefile +++ b/Makefile @@ -3593,6 +3593,9 @@ hammerhead_config : unconfig mimc200_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
+nimbuscloud_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap nimbuscloud indefia at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/indefia/nimbuscloud/Makefile b/board/indefia/nimbuscloud/Makefile new file mode 100644 index 0000000..43a9c68 --- /dev/null +++ b/board/indefia/nimbuscloud/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008-2009 Indefia +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/indefia/nimbuscloud/config.mk b/board/indefia/nimbuscloud/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/indefia/nimbuscloud/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c new file mode 100644 index 0000000..e869a97 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Based on atngw100.c (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/portmux.h> +#include <netdev.h> +#include <net.h> + +#include "nimbuscloud.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +static u8 read_configsw(void) { + u8 configsw = 0; + + if ( ! gpio_get_value(GPIO_PIN_PB(13)) ) + configsw |= 1; + if ( ! gpio_get_value(GPIO_PIN_PB(14)) ) + configsw |= 2; + if ( ! gpio_get_value(GPIO_PIN_PB(15)) ) + configsw |= 4; + if ( ! gpio_get_value(GPIO_PIN_PB(16)) ) + configsw |= 8; + + return configsw; +} + + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + + /* Enable GPIO on config swicthes */ + portmux_select_gpio( + PORTMUX_PORT_B, + (1 << 13) | (1 << 14) | (1 << 15) | (1 << 16), + PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif + + if ( (read_configsw() & 1) == 1 ) { + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int misc_init_r(void) +{ + char buf[3]; + u8 configsw; + + configsw = read_configsw(); + + if ( (configsw & 1) == 1 ) { + setenv("bootdelay", "0"); + } + + sprintf(buf, "%d", configsw); + setenv("configsw", buf); + + return 0; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + return 0; +} + +#ifdef CONFIG_CMD_NET + +int board_eth_init(bd_t *bi) +{ + u16 val; + + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + + /* PHY is in power down state initially. + Exit power-down state, write 1 to MICR (0x11) + */ + macb_miiphy_write("macb0", 1, 0x11, 0x01); + + /* Configure LEDs, read and modify PHYCR (0x19) + Left: link, right: activity + */ + macb_miiphy_read("macb0", 1, 0x19, &val); + val |= 1<<5; + macb_miiphy_write("macb0", 1, 0x19, val); + + return 0; +} +#endif + diff --git a/board/indefia/nimbuscloud/nimbuscloud.h b/board/indefia/nimbuscloud/nimbuscloud.h new file mode 100644 index 0000000..f6a0571 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.h @@ -0,0 +1,8 @@ + +#ifdef CONFIG_CMD_NET + +extern int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value); +extern int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value); + +#endif + diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds new file mode 100644 index 0000000..a7243f2 --- /dev/null +++ b/board/indefia/nimbuscloud/u-boot.lds @@ -0,0 +1,72 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/nimbuscloud.h b/include/configs/nimbuscloud.h new file mode 100644 index 0000000..8a53725 --- /dev/null +++ b/include/configs/nimbuscloud.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Configuration settings for Indefia Nimbus Cloud + * + * Based on atngw100.h (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_NIMBUSCLOUD 1 + +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 180 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_SYS_OSC0_HZ 25000000 +#define CONFIG_SYS_PLL0_DIV 5 +#define CONFIG_SYS_PLL0_MUL 36 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +#define CONFIG_SYS_CLKDIV_CPU 0 +#define CONFIG_SYS_CLKDIV_HSB 1 +#define CONFIG_SYS_CLKDIV_PBA 2 +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x05 + +#define CONFIG_USART1 1 + +/* User serviceable stuff */ + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock4 rootfstype=jffs2 fbmem=1200k" +#define CONFIG_BOOTCOMMAND \ + "cp.b 0x20000 0x90400000 0x180000; bootm 0x90400000" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +/* #define CONFIG_CMD_JFFS2 */ +#define CONFIG_CMD_MMC +/* #define CONFIG_CMD_SF */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_SYS_FLASH_BASE 0xa0000000 +#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 39 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 65536 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 + +#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#define CONFIG_CMD_MII 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_DISABLE_CONSOLE 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 + + +#endif /* __CONFIG_H */ +
Dear Semih Hazar,
In message 4B6B0058.2090809@indefia.com you wrote:
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/indefia/nimbuscloud/Makefile | 40 +++++++ board/indefia/nimbuscloud/config.mk | 3 + board/indefia/nimbuscloud/nimbuscloud.c | 165 +++++++++++++++++++++++++++ board/indefia/nimbuscloud/nimbuscloud.h | 8 ++ board/indefia/nimbuscloud/u-boot.lds | 72 ++++++++++++ include/configs/nimbuscloud.h | 184 +++++++++++++++++++++++++++++++ 10 files changed, 484 insertions(+), 0 deletions(-)
I am not sure how this patch addresses the previously discussed topic of cached/uncached accesses to the NOR flash. It does not mention the topic anywhere in the commit message or other comments, which I consider a serious flaw of the patch.
From the
#define CONFIG_SYS_FLASH_BASE 0xa0000000
I understand that this is the version where the end user has to deal with two different address ranges (i. e. "md 10000" would be used to dump the 2nd 64kB-sector, while "era A0010000" would be needed to erase the same sector.
Such behaviour is seems unacceptable to me. If my understanding is corrent, I tend to reject this patch. [Please see explanations in previous messages for other options to solve this issue.]
Best regards,
Wolfgang Denk
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
--- CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/indefia/nimbuscloud/Makefile | 40 ++++++ board/indefia/nimbuscloud/config.mk | 3 + board/indefia/nimbuscloud/flash.c | 226 +++++++++++++++++++++++++++++++ board/indefia/nimbuscloud/nimbuscloud.c | 166 +++++++++++++++++++++++ board/indefia/nimbuscloud/u-boot.lds | 72 ++++++++++ include/configs/nimbuscloud.h | 182 +++++++++++++++++++++++++ 10 files changed, 701 insertions(+), 0 deletions(-)
diff --git a/CREDITS b/CREDITS index 2471029..69a9dde 100644 --- a/CREDITS +++ b/CREDITS @@ -196,6 +196,10 @@ N: Anne-Sophie Harnois E: Anne-Sophie.Harnois@nextream.fr D: Port to Walnut405 board
+N: Semih Hazar +E: semih.hazar@indefia.com +D: Nimbus Cloud board support + N: Andreas Heppel E: aheppel@sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d..0764ee9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -880,6 +880,10 @@ Hans-Christian Egtvedt hans-christian.egtvedt@atmel.com
FAVR-32-EZKIT AT32AP7000
+Semih Hazar semih.hazar@indefia.com + + NIMBUSCLOUD AT32AP7000 + Mark Jackson mpfj@mimc.co.uk
MIMC200 AT32AP7000 diff --git a/MAKEALL b/MAKEALL index ab1bb6f..fde90ee 100755 --- a/MAKEALL +++ b/MAKEALL @@ -859,6 +859,7 @@ LIST_avr32=" \ favr-32-ezkit \ hammerhead \ mimc200 \ + nimbuscloud \ "
######################################################################### diff --git a/Makefile b/Makefile index 536ccb3..ea16786 100644 --- a/Makefile +++ b/Makefile @@ -3595,6 +3595,9 @@ hammerhead_config : unconfig mimc200_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
+nimbuscloud_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap nimbuscloud indefia at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/indefia/nimbuscloud/Makefile b/board/indefia/nimbuscloud/Makefile new file mode 100644 index 0000000..5ddc351 --- /dev/null +++ b/board/indefia/nimbuscloud/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2008-2009 Indefia +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/indefia/nimbuscloud/config.mk b/board/indefia/nimbuscloud/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/indefia/nimbuscloud/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/indefia/nimbuscloud/flash.c b/board/indefia/nimbuscloud/flash.c new file mode 100644 index 0000000..70f51b0 --- /dev/null +++ b/board/indefia/nimbuscloud/flash.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2009 Indefia + * + * Based on work (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/arch/cacheflush.h> +#include <asm/io.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0x90, flash); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + gd->bd->bi_flashsize = CONFIG_SYS_FLASH_SIZE; + gd->bd->bi_flashoffset = _edata - _text; + + flash_info[0].size = CONFIG_SYS_FLASH_SIZE; + flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + + flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); + + /* First 8 sectors are 8k */ + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + + /* Remaing are 64k */ + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CONFIG_SYS_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + if ( info->flash_id == 0x1f88c5 ) { + printf("Atmel AT49BV320C"); + } else if ( info->flash_id == 0x1f90c5 ) { + printf("Atmel AT49BV320D"); + } else if ( info->flash_id == 0x1f90c3 ) { + printf("Atmel AT49BV160D"); + } else { + printf("Manufacturer/Device ID: 0x%02x/0x%04x", + (int) (info->flash_id >> 16), + (int) (info->flash_id & FLASH_TYPEMASK)); + } + + printf(", Size: %ld KB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + uint16_t *fb, *sb; + unsigned int i; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + sb = (uint16_t *)uncached(info->start[i]); + printf("Erasing sector %d %p\n", i, sb); + + flags = disable_interrupts(); + + /* Unlock sector */ + writew(0x50, fb); /* Clear status bit */ + writew(0x60, fb); /* Sector unlock */ + writew(0xd0, sb); /* confirm */ + + while ( ! (readw(fb) & 0x80) ); + + /* Erase sector */ + writew(0x50, fb); /* Clear status bit */ + writew(0x20, fb); /* Sector erase */ + writew(0xd0, sb); /* confirm */ + + /* Wait for completion */ + do { + status = readw(fb); + } while (!(status & 0x80)); + + writew(0xff, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0x80) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + return ERR_PROG_ERROR; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0x40, base); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + do { + status = readw(p); + } while (!(status & 0x80)); + + writew(0xff, base); + readw(base); + + status= readw(p); + if (status != word) { + printf("Flash write error at address 0x%p: 0x%02x\n", + p, status); + printf("Wrote %04x Read %04x\n", word, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (flags) + enable_interrupts(); + + return ret; +} + diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c new file mode 100644 index 0000000..03fc5c9 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Based on atngw100.c (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/portmux.h> +#include <netdev.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +static u8 read_configsw(void) { + u8 configsw = 0; + + if ( ! gpio_get_value(GPIO_PIN_PB(13)) ) + configsw |= 1; + if ( ! gpio_get_value(GPIO_PIN_PB(14)) ) + configsw |= 2; + if ( ! gpio_get_value(GPIO_PIN_PB(15)) ) + configsw |= 4; + if ( ! gpio_get_value(GPIO_PIN_PB(16)) ) + configsw |= 8; + + return configsw; +} + + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + + /* Enable GPIO on config swicthes */ + portmux_select_gpio( + PORTMUX_PORT_B, + (1 << 13) | (1 << 14) | (1 << 15) | (1 << 16), + PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif + + if ( (read_configsw() & 1) == 1 ) { + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int misc_init_r(void) +{ + char buf[3]; + u8 configsw; + + configsw = read_configsw(); + + if ( (configsw & 1) == 1 ) { + setenv("bootdelay", "0"); + } + + sprintf(buf, "%d", configsw); + setenv("configsw", buf); + + return 0; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + return 0; +} + +#ifdef CONFIG_CMD_NET + +extern int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value); +extern int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value); + +int board_eth_init(bd_t *bi) +{ + u16 val; + + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + + /* PHY is in power down state initially. + Exit power-down state, write 1 to MICR (0x11) + */ + macb_miiphy_write("macb0", 1, 0x11, 0x01); + + /* Configure LEDs, read and modify PHYCR (0x19) + Left: link, right: activity + */ + macb_miiphy_read("macb0", 1, 0x19, &val); + val |= 1<<5; + macb_miiphy_write("macb0", 1, 0x19, val); + + return 0; +} +#endif + diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds new file mode 100644 index 0000000..a7243f2 --- /dev/null +++ b/board/indefia/nimbuscloud/u-boot.lds @@ -0,0 +1,72 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/nimbuscloud.h b/include/configs/nimbuscloud.h new file mode 100644 index 0000000..8c91333 --- /dev/null +++ b/include/configs/nimbuscloud.h @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2008-2009 Indefia + * + * Configuration settings for Indefia Nimbus Cloud + * + * Based on atngw100.h (c) Atmel Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_NIMBUSCLOUD 1 + +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 180 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_SYS_OSC0_HZ 25000000 +#define CONFIG_SYS_PLL0_DIV 5 +#define CONFIG_SYS_PLL0_MUL 36 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +#define CONFIG_SYS_CLKDIV_CPU 0 +#define CONFIG_SYS_CLKDIV_HSB 1 +#define CONFIG_SYS_CLKDIV_PBA 2 +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x05 + +#define CONFIG_USART1 1 + +/* User serviceable stuff */ + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock4 rootfstype=jffs2 fbmem=1200k" +#define CONFIG_BOOTCOMMAND \ + "cp.b 0x20000 0x90400000 0x180000; bootm 0x90400000" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +/* #define CONFIG_CMD_SF */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_SPI 1 + +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 39 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 65536 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 + +#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#define CONFIG_CMD_MII 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_DISABLE_CONSOLE 1 /* disable console */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ + + +#endif /* __CONFIG_H */
Dear Semih Hazar,
In message 4B585314.7010100@indefia.com you wrote:
Nimbus Cloud is an AVR32 based single board computer with 256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch screen support, VGA Output, Ethernet and offers seamless integration with Indefia's Zigbee transceivers.
CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/indefia/nimbuscloud/Makefile | 40 ++++++ board/indefia/nimbuscloud/config.mk | 3 + board/indefia/nimbuscloud/flash.c | 226 +++++++++++++++++++++++++++++++ board/indefia/nimbuscloud/nimbuscloud.c | 166 +++++++++++++++++++++++ board/indefia/nimbuscloud/u-boot.lds | 72 ++++++++++ include/configs/nimbuscloud.h | 182 +++++++++++++++++++++++++ 10 files changed, 701 insertions(+), 0 deletions(-)
As explained before:
NAK for board/indefia/nimbuscloud/flash.c
diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c new file mode 100644 index 0000000..03fc5c9 --- /dev/null +++ b/board/indefia/nimbuscloud/nimbuscloud.c
...
+#ifdef CONFIG_CMD_NET
+extern int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value); +extern int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value);
Such prototypes belong into some header file.
Best regards,
Wolfgang Denk
participants (3)
-
Semih Hazar -
Stefan Roese -
Wolfgang Denk