[PATCH 1/2] ARM: renesas: falcon: Initialize ARM generic timer and GICv3 if EL3
From: Hai Pham hai.pham.ud@renesas.com
U-Boot executes at EL3 is required to initalize those settings. In other cases, they will be done by prior-stage firmware instead.
This fixes crash when U-Boot is at non-secure exception level.
Reviewed-by: Marek Vasut marek.vasut+renesas@mailbox.org Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- board/renesas/falcon/falcon.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index b0cb4e747b6..b7e7fd9003a 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -14,6 +14,7 @@ #include <asm/mach-types.h> #include <asm/processor.h> #include <linux/errno.h> +#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -69,7 +70,8 @@ static void init_gic_v3(void)
void s_init(void) { - init_generic_timer(); + if (current_el() == 3) + init_generic_timer(); }
int board_early_init_f(void) @@ -86,7 +88,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
- init_gic_v3(); + if (current_el() == 3) + init_gic_v3();
return 0; }
From: Hai Pham hai.pham.ud@renesas.com
Enable RWDT reset on Reset Controller so that it can be used as reset trigger source for V3U Falcon.
Reviewed-by: Marek Vasut marek.vasut+renesas@mailbox.org Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org # Use one current_el() in board_init --- board/renesas/falcon/falcon.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index b7e7fd9003a..ab7464d0ee3 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -83,21 +83,27 @@ int board_early_init_f(void) return 0; }
+#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 +#define RST_WDTRSTCR (RST_BASE + 0x10) +#define RST_RWDT 0xA55A8002 + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
- if (current_el() == 3) + if (current_el() == 3) { init_gic_v3();
+ /* Enable RWDT reset */ + writel(RST_RWDT, RST_WDTRSTCR); + } + return 0; }
-#define RST_BASE 0xE6160000 /* Domain0 */ -#define RST_SRESCR0 (RST_BASE + 0x18) -#define RST_SPRES 0x5AA58000 - void reset_cpu(void) { writel(RST_SPRES, RST_SRESCR0);
participants (1)
-
Marek Vasut