Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/include/asm/armv7m.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index ebf0f17..9a6224f 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -80,7 +80,8 @@ struct v7m_mpu { #define V7M_MPU_RASR_EN (1 << 0) #define V7M_MPU_RASR_SIZE_BITS 1 #define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) -#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS) +#define V7M_MPU_RASR_SIZE_8MB (22 << V7M_MPU_RASR_SIZE_BITS) + #define V7M_MPU_RASR_TEX_SHIFT 19 #define V7M_MPU_RASR_S_SHIFT 18 #define V7M_MPU_RASR_C_SHIFT 17

Cortex-M archs support option memory protection unit (MPU). MPU is used to set the memory types, attributes, access permissions for different regions, cache policies of the device.

e.g. using MPU it is possible to configure memory region as device memory or strongly ordered, memory attributes like execute never, cache policies like write-back or write-through.

Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/cpu/armv7m/Makefile | 2 +- arch/arm/cpu/armv7m/mpu.c | 82 +++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv7m.h | 20 ---------- arch/arm/include/asm/armv7m_mpu.h | 67 ++++++++++++++++++++++++++++++++ 4 files changed, 150 insertions(+), 21 deletions(-) create mode 100644 arch/arm/cpu/armv7m/mpu.c create mode 100644 arch/arm/include/asm/armv7m_mpu.h

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 93c9085..257fc7f 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,5 +6,5 @@ #

extra-y := start.o -obj-y += cpu.o cache.o +obj-y += cpu.o cache.o mpu.o obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c new file mode 100644 index 0000000..31a243b --- /dev/null +++ b/arch/arm/cpu/armv7m/mpu.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/bitops.h> +#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> +#include <asm/io.h> + +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_DISABLE (0 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) +#define VALID_REGION (1 << 4) + +#define ENABLE_REGION (1 << 0) + +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 +#define REGION_SIZE_SHIFT 1 + +#define CACHEABLE (1 << C_SHIFT) +#define BUFFERABLE (1 << B_SHIFT) +#define SHAREABLE (1 << S_SHIFT) + +void disable_mpu(void) +{ + writel(0, &V7M_MPU->ctrl); +} + +void enable_mpu(void) +{ + writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + + /* Make sure new mpu config is effective for next memory access */ + dsb(); + isb(); /* Make sure instruction stream sees it */ +} + +void mpu_config(struct mpu_region_config *reg_config) +{ + uint32_t attr; + + switch (reg_config->mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + default: + attr = 0; /* strongly ordered */ + break; + }; + + writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, + &V7M_MPU->rbar); + + writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr + | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION + , &V7M_MPU->rasr); +} diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index 9a6224f..af8a97e 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -70,25 +70,5 @@ struct v7m_mpu { }; #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE)

-#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_DISABLE (0 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_RASR_EN (1 << 0) -#define V7M_MPU_RASR_SIZE_BITS 1 -#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) -#define V7M_MPU_RASR_SIZE_8MB (22 << V7M_MPU_RASR_SIZE_BITS) - -#define V7M_MPU_RASR_TEX_SHIFT 19 -#define V7M_MPU_RASR_S_SHIFT 18 -#define V7M_MPU_RASR_C_SHIFT 17 -#define V7M_MPU_RASR_B_SHIFT 16 -#define V7M_MPU_RASR_AP_RW_RW (3 << 24) -#define V7M_MPU_RASR_XN_ENABLE (0 << 28) -#define V7M_MPU_RASR_XN_DISABLE (1 << 28) - #endif /* !defined(__ASSEMBLY__) */ #endif /* ARMV7M_H */ diff --git a/arch/arm/include/asm/armv7m_mpu.h b/arch/arm/include/asm/armv7m_mpu.h new file mode 100644 index 0000000..d7e99b4 --- /dev/null +++ b/arch/arm/include/asm/armv7m_mpu.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +enum region_number { + REGION_0 = 0, + REGION_1, + REGION_2, + REGION_3, + REGION_4, + REGION_5, + REGION_6, + REGION_7, +}; + +enum ap { + NO_ACCESS = 0, + PRIV_RW_USR_NO, + PRIV_RW_USR_RO, + PRIV_RW_USR_RW, + UNPREDICTABLE, + PRIV_RO_USR_NO, + PRIV_RO_USR_RO, +}; + +enum mr_attr { + STRONG_ORDER = 0, + SHARED_WRITE_BUFFERED, + O_I_WT_NO_WR_ALLOC, + O_I_WB_NO_WR_ALLOC, + O_I_NON_CACHEABLE, + O_I_WB_RD_WR_ALLOC, + DEVICE_NON_SHARED, +}; +enum size { + REGION_8MB = 22, + REGION_16MB, + REGION_32MB, + REGION_64MB, + REGION_128MB, + REGION_256MB, + REGION_512MB, + REGION_1GB, + REGION_2GB, + REGION_4GB, +}; + +enum xn { + XN_DIS = 0, + XN_EN, +}; + +struct mpu_region_config { + uint32_t start_addr; + enum region_number region_no; + enum xn xn; + enum ap ap; + enum mr_attr mr_attr; + enum size reg_size; +}; + +void disable_mpu(void); +void enable_mpu(void); +void mpu_config(struct mpu_region_config *reg_config);

Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/mach-stm32/stm32f4/soc.c | 16 +++++----- arch/arm/mach-stm32/stm32f7/soc.c | 64 ++++++++------------------------------- 2 files changed, 22 insertions(+), 58 deletions(-)

diff --git a/arch/arm/mach-stm32/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c index b5d06db..3f45a25 100644 --- a/arch/arm/mach-stm32/stm32f4/soc.c +++ b/arch/arm/mach-stm32/stm32f4/soc.c @@ -7,7 +7,7 @@

#include <common.h> #include <asm/io.h> -#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> #include <asm/arch/stm32.h>

u32 get_cpu_rev(void) @@ -17,17 +17,19 @@ u32 get_cpu_rev(void)

int arch_cpu_init(void) { + struct mpu_region_config stm32_region_config[] = { + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_4GB }, + }; configure_clocks(); - /* * Configure the memory protection unit (MPU) to allow full access to * the whole 4GB address space. */ - writel(0, &V7M_MPU->rnr); - writel(0, &V7M_MPU->rbar); - writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN), &V7M_MPU->rasr); - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + disable_mpu(); + for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++) + mpu_config(&stm32_region_config[i]); + enable_mpu();

return 0; } diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 6f9704a..3586133 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -7,7 +7,7 @@

#include <common.h> #include <asm/io.h> -#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> #include <asm/arch/stm32.h>

u32 get_cpu_rev(void) @@ -17,56 +17,18 @@ u32 get_cpu_rev(void)

int arch_cpu_init(void) { - /* - * Configure the memory protection unit (MPU) - * 0x00000000 - 0xffffffff: Strong-order, Shareable - * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable - */ - - /* Disable MPU */ - writel(0, &V7M_MPU->ctrl); - - writel( - 0x00000000 /* address */ - | 1 << 4 /* VALID */ - | 0 << 0 /* REGION */ - , &V7M_MPU->rbar - ); - - /* Strong-order, Shareable */ - /* TEX=000, S=1, C=0, B=0*/ - writel( - (V7M_MPU_RASR_XN_ENABLE - | V7M_MPU_RASR_AP_RW_RW - | 0x01 << V7M_MPU_RASR_S_SHIFT - | 0x00 << V7M_MPU_RASR_TEX_SHIFT - | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN) - , &V7M_MPU->rasr - ); - - writel( - 0xC0000000 /* address */ - | 1 << 4 /* VALID */ - | 1 << 0 /* REGION */ - , &V7M_MPU->rbar - ); - - /* Normal, Outer and inner Non-cacheable */ - /* TEX=001, S=0, C=0, B=0*/ - writel( - (V7M_MPU_RASR_XN_ENABLE - | V7M_MPU_RASR_AP_RW_RW - | 0x01 << V7M_MPU_RASR_TEX_SHIFT - | 0x01 << V7M_MPU_RASR_B_SHIFT - | 0x01 << V7M_MPU_RASR_C_SHIFT - | V7M_MPU_RASR_SIZE_8MB - | V7M_MPU_RASR_EN) - , &V7M_MPU->rasr - ); - - /* Enable MPU */ - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + struct mpu_region_config stm32_region_config[] = { + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_4GB }, + + { 0xC0000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_8MB }, + }; + + disable_mpu(); + for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++) + mpu_config(&stm32_region_config[i]); + enable_mpu();

return 0; }

This configuration should be valid for all F7 family devices in general. Here is the regions info:

- Region0 : 4GB : cacheable & executable. - Region1 : 512MB : text area : strogly ordered & executable. - Region2 : 512MB : peripherals : device memory & non-executable. - Region3 : 512MB : peripherals : device memory & non-executable. - Region4 : 512MB : cortexM area: strongly ordered & non-executable.

Higher region number overrides the lower region configuration.

Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/mach-stm32/stm32f7/soc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 3586133..74a9350 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -19,10 +19,19 @@ int arch_cpu_init(void) { struct mpu_region_config stm32_region_config[] = { { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_4GB }, + O_I_WB_RD_WR_ALLOC, REGION_4GB },

- { 0xC0000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_8MB }, + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, + + { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, + + { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, + + { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, };

disable_mpu();