[U-Boot] [PATCH 00/11] ti: k3-udma: Add support for J721e
This series adds DMA support for J721e using exist K3 UDMA driver.
One main change is thati, on J721e, DMA resources such as DMA channels are shared between different entities running on different cores of the SoC. Therefore, U-Boot running on A72 core should request range of resources allocated to it from centralized resource management core (DMSC) and use only the allocated resource.
First two patches adds support for dynamically querying and using allocated resources. Remaining patches fix issues when using UDMA driver on a 32 bit core like R5. Last patch adds a new compatible for J721e
Vignesh Raghavendra (11): lib: Import few bitmap functions from Linux dma: ti: k3-udma: Query DMA channels allocated from Resource Manager soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle dma: ti: k3-udma: Get SYSFW reference from DT phandle dma: ti: k3-udma: Remove coherency check for cache ops dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfers dma: ti: k3-udma: Switch to exposed ring mode dma: ti: k3-udma: Fix ring push operation for 32 bit cores dma: ti: k3-udma: Fix build warnings when building for 32 bit platforms dma: ti: k3-udma: Add new compatible to J721e
drivers/dma/ti/k3-udma-hwdef.h | 19 +++ drivers/dma/ti/k3-udma.c | 255 ++++++++++++++++++++++-------- drivers/soc/ti/k3-navss-ringacc.c | 13 +- include/linux/bitmap.h | 133 ++++++++++++++++ include/linux/bitops.h | 12 ++ 5 files changed, 362 insertions(+), 70 deletions(-)
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}()) and their dependencies from Linux. These are required for upcoming DMA resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- include/linux/bitmap.h | 133 +++++++++++++++++++++++++++++++++++++++++ include/linux/bitops.h | 12 ++++ 2 files changed, 145 insertions(+)
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h index fbbb67c8b24e..dae4225be549 100644 --- a/include/linux/bitmap.h +++ b/include/linux/bitmap.h @@ -5,10 +5,88 @@ #include <asm/types.h> #include <linux/types.h> #include <linux/bitops.h> +#include <linux/string.h>
+#ifdef __LITTLE_ENDIAN +#define BITMAP_MEM_ALIGNMENT 8 +#else +#define BITMAP_MEM_ALIGNMENT (8 * sizeof(unsigned long)) +#endif +#define BITMAP_MEM_MASK (BITMAP_MEM_ALIGNMENT - 1) + +#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) +#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) #define small_const_nbits(nbits) \ (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+static inline void +__bitmap_or(unsigned long *dst, const unsigned long *bitmap1, + const unsigned long *bitmap2, unsigned int bits) +{ + unsigned int k; + unsigned int nr = BITS_TO_LONGS(bits); + + for (k = 0; k < nr; k++) + dst[k] = bitmap1[k] | bitmap2[k]; +} + +static inline int +__bitmap_weight(const unsigned long *bitmap, unsigned int bits) +{ + unsigned int k, lim = bits / BITS_PER_LONG; + int w = 0; + + for (k = 0; k < lim; k++) + w += hweight_long(bitmap[k]); + + if (bits % BITS_PER_LONG) + w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); + + return w; +} + +static inline void +__bitmap_set(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_set >= 0) { + *p |= mask_to_set; + len -= bits_to_set; + bits_to_set = BITS_PER_LONG; + mask_to_set = ~0UL; + p++; + } + if (len) { + mask_to_set &= BITMAP_LAST_WORD_MASK(size); + *p |= mask_to_set; + } +} + +static inline void +__bitmap_clear(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_clear = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_clear >= 0) { + *p &= ~mask_to_clear; + len -= bits_to_clear; + bits_to_clear = BITS_PER_LONG; + mask_to_clear = ~0UL; + p++; + } + if (len) { + mask_to_clear &= BITMAP_LAST_WORD_MASK(size); + *p &= ~mask_to_clear; + } +} + static inline void bitmap_zero(unsigned long *dst, int nbits) { if (small_const_nbits(nbits)) { @@ -81,4 +159,59 @@ static inline unsigned long find_first_bit(const unsigned long *addr, unsigned l (bit) < (size); \ (bit) = find_next_bit((addr), (size), (bit) + 1))
+static inline void bitmap_fill(unsigned long *dst, unsigned int nbits) +{ + if (small_const_nbits(nbits)) { + *dst = ~0UL; + } else { + unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + + memset(dst, 0xff, len); + } +} + +static inline void bitmap_or(unsigned long *dst, const unsigned long *src1, + const unsigned long *src2, unsigned int nbits) +{ + if (small_const_nbits(nbits)) + *dst = *src1 | *src2; + else + __bitmap_or(dst, src1, src2, nbits); +} + +static inline int bitmap_weight(const unsigned long *src, unsigned int nbits) +{ + if (small_const_nbits(nbits)) + return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits)); + return __bitmap_weight(src, nbits); +} + +static inline void bitmap_set(unsigned long *map, unsigned int start, + unsigned int nbits) +{ + if (__builtin_constant_p(nbits) && nbits == 1) + __set_bit(start, map); + else if (__builtin_constant_p(start & BITMAP_MEM_MASK) && + IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) && + __builtin_constant_p(nbits & BITMAP_MEM_MASK) && + IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT)) + memset((char *)map + start / 8, 0xff, nbits / 8); + else + __bitmap_set(map, start, nbits); +} + +static inline void bitmap_clear(unsigned long *map, unsigned int start, + unsigned int nbits) +{ + if (__builtin_constant_p(nbits) && nbits == 1) + __clear_bit(start, map); + else if (__builtin_constant_p(start & BITMAP_MEM_MASK) && + IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) && + __builtin_constant_p(nbits & BITMAP_MEM_MASK) && + IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT)) + memset((char *)map + start / 8, 0, nbits / 8); + else + __bitmap_clear(map, start, nbits); +} + #endif /* __LINUX_BITMAP_H */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 259df43fb00f..a07c70fd4858 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -4,6 +4,7 @@ #include <asm/types.h> #include <asm-generic/bitsperlong.h> #include <linux/compiler.h> +#include <linux/kernel.h>
#ifdef __KERNEL__ #define BIT(nr) (1UL << (nr)) @@ -133,6 +134,17 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); }
+static inline unsigned long generic_hweight64(__u64 w) +{ + return generic_hweight32((unsigned int)(w >> 32)) + + generic_hweight32((unsigned int)w); +} + +static inline unsigned long hweight_long(unsigned long w) +{ + return sizeof(w) == 4 ? generic_hweight32(w) : generic_hweight64(w); +} + #include <asm/bitops.h>
/* linux/include/asm-generic/bitops/non-atomic.h */
On Thu, Nov 14, 2019 at 02:44:22PM +0530, Vignesh Raghavendra wrote:
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}()) and their dependencies from Linux. These are required for upcoming DMA resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma-hwdef.h | 19 ++++ drivers/dma/ti/k3-udma.c | 179 ++++++++++++++++++++++++++++----- 2 files changed, 171 insertions(+), 27 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h index c88399a815ea..228a44cb73cf 100644 --- a/drivers/dma/ti/k3-udma-hwdef.h +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -181,4 +181,23 @@ #define PDMA_STATIC_TR_Z(x) \ (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
+enum udma_rm_range { + RM_RANGE_TCHAN = 0, + RM_RANGE_RCHAN, + RM_RANGE_RFLOW, + RM_RANGE_LAST, +}; + +struct udma_tisci_rm { + const struct ti_sci_handle *tisci; + const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; + u32 tisci_dev_id; + + /* tisci information for PSI-L thread pairing/unpairing */ + const struct ti_sci_rm_psil_ops *tisci_psil_ops; + u32 tisci_navss_dev_id; + + struct ti_sci_resource *rm_ranges[RM_RANGE_LAST]; +}; + #endif /* K3_NAVSS_UDMA_HWDEF_H_ */ diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a5fc7809bc41..2380780879f5 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -11,12 +11,14 @@ #include <malloc.h> #include <asm/dma-mapping.h> #include <dm.h> +#include <dm/device.h> #include <dm/read.h> #include <dm/of_access.h> #include <dma.h> #include <dma-uclass.h> #include <linux/delay.h> #include <dt-bindings/dma/k3-udma.h> +#include <linux/bitmap.h> #include <linux/soc/ti/k3-navss-ringacc.h> #include <linux/soc/ti/cppi5.h> #include <linux/soc/ti/ti-udma.h> @@ -30,6 +32,8 @@ #define RINGACC_RING_USE_PROXY (1) #endif
+#define K3_UDMA_MAX_RFLOWS 1024 + struct udma_chan;
enum udma_mmr { @@ -64,9 +68,10 @@ struct udma_rflow { };
struct udma_dev { - struct device *dev; + struct udevice *dev; void __iomem *mmrs[MMR_LAST];
+ struct udma_tisci_rm tisci_rm; struct k3_nav_ringacc *ringacc;
u32 features; @@ -78,6 +83,7 @@ struct udma_dev { unsigned long *tchan_map; unsigned long *rchan_map; unsigned long *rflow_map; + unsigned long *rflow_map_reserved;
struct udma_tchan *tchans; struct udma_rchan *rchans; @@ -535,6 +541,28 @@ static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr) } }
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id) +{ + DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS); + + if (id >= 0) { + if (test_bit(id, ud->rflow_map)) { + dev_err(ud->dev, "rflow%d is in use\n", id); + return ERR_PTR(-ENOENT); + } + } else { + bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved, + ud->rflow_cnt); + + id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt); + if (id >= ud->rflow_cnt) + return ERR_PTR(-ENOENT); + } + + __set_bit(id, ud->rflow_map); + return &ud->rflows[id]; +} + #define UDMA_RESERVE_RESOURCE(res) \ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ int id) \ @@ -557,7 +585,6 @@ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
UDMA_RESERVE_RESOURCE(tchan); UDMA_RESERVE_RESOURCE(rchan); -UDMA_RESERVE_RESOURCE(rflow);
static int udma_get_tchan(struct udma_chan *uc) { @@ -1103,14 +1130,129 @@ static int udma_get_mmrs(struct udevice *dev) return 0; }
-#define UDMA_MAX_CHANNELS 192 +static int udma_setup_resources(struct udma_dev *ud) +{ + struct udevice *dev = ud->dev; + int ch_count, i; + u32 cap2, cap3; + struct ti_sci_resource_desc *rm_desc; + struct ti_sci_resource *rm_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + static const char * const range_names[] = { "ti,sci-rm-range-tchan", + "ti,sci-rm-range-rchan", + "ti,sci-rm-range-rflow" }; + + cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); + cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); + + ud->rflow_cnt = cap3 & 0x3fff; + ud->tchan_cnt = cap2 & 0x1ff; + ud->echan_cnt = (cap2 >> 9) & 0x1ff; + ud->rchan_cnt = (cap2 >> 18) & 0x1ff; + ch_count = ud->tchan_cnt + ud->rchan_cnt; + + ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + GFP_KERNEL); + + if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map || + !ud->rflow_map_reserved || !ud->tchans || !ud->rchans || + !ud->rflows) + return -ENOMEM; + + /* + * RX flows with the same Ids as RX channels are reserved to be used + * as default flows if remote HW can't generate flow_ids. Those + * RX flows can be requested only explicitly by id. + */ + bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt); + + /* Get resource ranges from tisci */ + for (i = 0; i < RM_RANGE_LAST; i++) + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(ud->tisci, dev, + ud->tisci_dev_id, + (char *)range_names[i]); + + /* tchan ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->tchan_map, rm_desc->start, + rm_desc->num); + } + }
+ /* rchan and matching default flow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + bitmap_zero(ud->rflow_map, ud->rchan_cnt); + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + bitmap_fill(ud->rflow_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rchan_map, rm_desc->start, + rm_desc->num); + bitmap_clear(ud->rflow_map, rm_desc->start, + rm_desc->num); + } + } + + /* GP rflow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; + if (IS_ERR(rm_res)) { + bitmap_clear(ud->rflow_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + } else { + bitmap_set(ud->rflow_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rflow_map, rm_desc->start, + rm_desc->num); + } + } + + ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); + if (!ch_count) + return -ENODEV; + + ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), + GFP_KERNEL); + if (!ud->channels) + return -ENOMEM; + + dev_info(dev, + "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n", + ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt, + ud->rflow_cnt); + + return ch_count; +} static int udma_probe(struct udevice *dev) { struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct udma_dev *ud = dev_get_priv(dev); int i, ret; - u32 cap2, cap3; struct udevice *tmp; struct udevice *tisci_dev = NULL;
@@ -1170,14 +1312,10 @@ static int udma_probe(struct udevice *dev)
ud->is_coherent = dev_read_bool(dev, "dma-coherent");
- cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); - cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); - - ud->rflow_cnt = cap3 & 0x3fff; - ud->tchan_cnt = cap2 & 0x1ff; - ud->echan_cnt = (cap2 >> 9) & 0x1ff; - ud->rchan_cnt = (cap2 >> 18) & 0x1ff; - ud->ch_count = ud->tchan_cnt + ud->rchan_cnt; + ud->dev = dev; + ud->ch_count = udma_setup_resources(ud); + if (ud->ch_count <= 0) + return ud->ch_count;
dev_info(dev, "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n", @@ -1187,21 +1325,8 @@ static int udma_probe(struct udevice *dev)
ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels), GFP_KERNEL); - ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, - sizeof(*ud->tchans), GFP_KERNEL); - ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, - sizeof(*ud->rchans), GFP_KERNEL); - ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, - sizeof(*ud->rflows), GFP_KERNEL); - - if (!ud->channels || !ud->tchan_map || !ud->rchan_map || - !ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows) + + if (!ud->channels) return -ENOMEM;
for (i = 0; i < ud->tchan_cnt; i++) {
On 14/11/2019 11:14, Vignesh Raghavendra wrote:
On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
drivers/dma/ti/k3-udma-hwdef.h | 19 ++++ drivers/dma/ti/k3-udma.c | 179 ++++++++++++++++++++++++++++----- 2 files changed, 171 insertions(+), 27 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h index c88399a815ea..228a44cb73cf 100644 --- a/drivers/dma/ti/k3-udma-hwdef.h +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -181,4 +181,23 @@ #define PDMA_STATIC_TR_Z(x) \ (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
+enum udma_rm_range {
- RM_RANGE_TCHAN = 0,
- RM_RANGE_RCHAN,
- RM_RANGE_RFLOW,
- RM_RANGE_LAST,
+};
+struct udma_tisci_rm {
- const struct ti_sci_handle *tisci;
- const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
- u32 tisci_dev_id;
- /* tisci information for PSI-L thread pairing/unpairing */
- const struct ti_sci_rm_psil_ops *tisci_psil_ops;
- u32 tisci_navss_dev_id;
- struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
it looks like TBD. only rm_ranges field is used.
+};
- #endif /* K3_NAVSS_UDMA_HWDEF_H_ */
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a5fc7809bc41..2380780879f5 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -11,12 +11,14 @@ #include <malloc.h> #include <asm/dma-mapping.h> #include <dm.h> +#include <dm/device.h> #include <dm/read.h> #include <dm/of_access.h> #include <dma.h> #include <dma-uclass.h> #include <linux/delay.h> #include <dt-bindings/dma/k3-udma.h> +#include <linux/bitmap.h> #include <linux/soc/ti/k3-navss-ringacc.h> #include <linux/soc/ti/cppi5.h> #include <linux/soc/ti/ti-udma.h> @@ -30,6 +32,8 @@ #define RINGACC_RING_USE_PROXY (1) #endif
+#define K3_UDMA_MAX_RFLOWS 1024
struct udma_chan;
enum udma_mmr {
@@ -64,9 +68,10 @@ struct udma_rflow { };
struct udma_dev {
- struct device *dev;
struct udevice *dev; void __iomem *mmrs[MMR_LAST];
struct udma_tisci_rm tisci_rm; struct k3_nav_ringacc *ringacc;
u32 features;
@@ -78,6 +83,7 @@ struct udma_dev { unsigned long *tchan_map; unsigned long *rchan_map; unsigned long *rflow_map;
unsigned long *rflow_map_reserved;
struct udma_tchan *tchans; struct udma_rchan *rchans;
@@ -535,6 +541,28 @@ static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr) } }
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id) +{
- DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
- if (id >= 0) {
if (test_bit(id, ud->rflow_map)) {dev_err(ud->dev, "rflow%d is in use\n", id);return ERR_PTR(-ENOENT);}- } else {
bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,ud->rflow_cnt);id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);if (id >= ud->rflow_cnt)return ERR_PTR(-ENOENT);- }
- __set_bit(id, ud->rflow_map);
- return &ud->rflows[id];
+}
- #define UDMA_RESERVE_RESOURCE(res) \ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ int id) \
@@ -557,7 +585,6 @@ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
UDMA_RESERVE_RESOURCE(tchan); UDMA_RESERVE_RESOURCE(rchan); -UDMA_RESERVE_RESOURCE(rflow);
static int udma_get_tchan(struct udma_chan *uc) { @@ -1103,14 +1130,129 @@ static int udma_get_mmrs(struct udevice *dev) return 0; }
-#define UDMA_MAX_CHANNELS 192 +static int udma_setup_resources(struct udma_dev *ud) +{
struct udevice *dev = ud->dev;
int ch_count, i;
u32 cap2, cap3;
struct ti_sci_resource_desc *rm_desc;
struct ti_sci_resource *rm_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
static const char * const range_names[] = { "ti,sci-rm-range-tchan",
"ti,sci-rm-range-rchan","ti,sci-rm-range-rflow" };cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
ud->rflow_cnt = cap3 & 0x3fff;
ud->tchan_cnt = cap2 & 0x1ff;
ud->echan_cnt = (cap2 >> 9) & 0x1ff;
ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
ch_count = ud->tchan_cnt + ud->rchan_cnt;
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
GFP_KERNEL);ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
sizeof(unsigned long), GFP_KERNEL);ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
GFP_KERNEL);ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
sizeof(unsigned long), GFP_KERNEL);ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
sizeof(unsigned long),GFP_KERNEL);ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
GFP_KERNEL);if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
!ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||!ud->rflows)return -ENOMEM;/*
* RX flows with the same Ids as RX channels are reserved to be used* as default flows if remote HW can't generate flow_ids. Those* RX flows can be requested only explicitly by id.*/bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
/* Get resource ranges from tisci */
for (i = 0; i < RM_RANGE_LAST; i++)
tisci_rm->rm_ranges[i] =devm_ti_sci_get_of_resource(ud->tisci, dev,ud->tisci_dev_id,(char *)range_names[i]);/* tchan ranges */
rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
if (IS_ERR(rm_res)) {
bitmap_zero(ud->tchan_map, ud->tchan_cnt);} else {
bitmap_fill(ud->tchan_map, ud->tchan_cnt);for (i = 0; i < rm_res->sets; i++) {rm_desc = &rm_res->desc[i];bitmap_clear(ud->tchan_map, rm_desc->start,rm_desc->num);}}
/* rchan and matching default flow ranges */
rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
if (IS_ERR(rm_res)) {
bitmap_zero(ud->rchan_map, ud->rchan_cnt);bitmap_zero(ud->rflow_map, ud->rchan_cnt);} else {
bitmap_fill(ud->rchan_map, ud->rchan_cnt);bitmap_fill(ud->rflow_map, ud->rchan_cnt);for (i = 0; i < rm_res->sets; i++) {rm_desc = &rm_res->desc[i];bitmap_clear(ud->rchan_map, rm_desc->start,rm_desc->num);bitmap_clear(ud->rflow_map, rm_desc->start,rm_desc->num);}}
/* GP rflow ranges */
rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
if (IS_ERR(rm_res)) {
bitmap_clear(ud->rflow_map, ud->rchan_cnt,ud->rflow_cnt - ud->rchan_cnt);} else {
bitmap_set(ud->rflow_map, ud->rchan_cnt,ud->rflow_cnt - ud->rchan_cnt);for (i = 0; i < rm_res->sets; i++) {rm_desc = &rm_res->desc[i];bitmap_clear(ud->rflow_map, rm_desc->start,rm_desc->num);}}
ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
if (!ch_count)
return -ENODEV;ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
GFP_KERNEL);if (!ud->channels)
return -ENOMEM;
it will allocate ud->channels twice, right?
- dev_info(dev,
"Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,ud->rflow_cnt);- return ch_count;
+} static int udma_probe(struct udevice *dev) { struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct udma_dev *ud = dev_get_priv(dev); int i, ret;
- u32 cap2, cap3; struct udevice *tmp; struct udevice *tisci_dev = NULL;
@@ -1170,14 +1312,10 @@ static int udma_probe(struct udevice *dev)
ud->is_coherent = dev_read_bool(dev, "dma-coherent");
- cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
- cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
- ud->rflow_cnt = cap3 & 0x3fff;
- ud->tchan_cnt = cap2 & 0x1ff;
- ud->echan_cnt = (cap2 >> 9) & 0x1ff;
- ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
- ud->ch_count = ud->tchan_cnt + ud->rchan_cnt;
ud->dev = dev;
ud->ch_count = udma_setup_resources(ud);
if (ud->ch_count <= 0)
return ud->ch_count;dev_info(dev, "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
@@ -1187,21 +1325,8 @@ static int udma_probe(struct udevice *dev)
ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels), GFP_KERNEL);
^^^
- ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);- ud->tchans = devm_kcalloc(dev, ud->tchan_cnt,
sizeof(*ud->tchans), GFP_KERNEL);- ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
sizeof(unsigned long), GFP_KERNEL);- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt,
sizeof(*ud->rchans), GFP_KERNEL);- ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
sizeof(unsigned long), GFP_KERNEL);- ud->rflows = devm_kcalloc(dev, ud->rflow_cnt,
sizeof(*ud->rflows), GFP_KERNEL);- if (!ud->channels || !ud->tchan_map || !ud->rchan_map ||
!ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows)
if (!ud->channels) return -ENOMEM;
for (i = 0; i < ud->tchan_cnt; i++) {
On 19/11/19 12:57 AM, Grygorii Strashko wrote:
On 14/11/2019 11:14, Vignesh Raghavendra wrote:
On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
drivers/dma/ti/k3-udma-hwdef.h | 19 ++++ drivers/dma/ti/k3-udma.c | 179 ++++++++++++++++++++++++++++----- 2 files changed, 171 insertions(+), 27 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h index c88399a815ea..228a44cb73cf 100644 --- a/drivers/dma/ti/k3-udma-hwdef.h +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -181,4 +181,23 @@ #define PDMA_STATIC_TR_Z(x) \ (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK) +enum udma_rm_range { + RM_RANGE_TCHAN = 0, + RM_RANGE_RCHAN, + RM_RANGE_RFLOW, + RM_RANGE_LAST, +};
+struct udma_tisci_rm { + const struct ti_sci_handle *tisci; + const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; + u32 tisci_dev_id;
+ /* tisci information for PSI-L thread pairing/unpairing */ + const struct ti_sci_rm_psil_ops *tisci_psil_ops; + u32 tisci_navss_dev_id;
+ struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
it looks like TBD. only rm_ranges field is used.
Oops, we have duplicates in udma_dev struct. I will drop those and make use of above fields to be consistent with Linux UDMA driver code
+};
#endif /* K3_NAVSS_UDMA_HWDEF_H_ */ diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a5fc7809bc41..2380780879f5 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -11,12 +11,14 @@ #include <malloc.h> #include <asm/dma-mapping.h> #include <dm.h> +#include <dm/device.h> #include <dm/read.h> #include <dm/of_access.h> #include <dma.h> #include <dma-uclass.h> #include <linux/delay.h> #include <dt-bindings/dma/k3-udma.h> +#include <linux/bitmap.h> #include <linux/soc/ti/k3-navss-ringacc.h> #include <linux/soc/ti/cppi5.h> #include <linux/soc/ti/ti-udma.h> @@ -30,6 +32,8 @@ #define RINGACC_RING_USE_PROXY (1) #endif +#define K3_UDMA_MAX_RFLOWS 1024
struct udma_chan; enum udma_mmr { @@ -64,9 +68,10 @@ struct udma_rflow { }; struct udma_dev { - struct device *dev; + struct udevice *dev; void __iomem *mmrs[MMR_LAST]; + struct udma_tisci_rm tisci_rm; struct k3_nav_ringacc *ringacc; u32 features; @@ -78,6 +83,7 @@ struct udma_dev { unsigned long *tchan_map; unsigned long *rchan_map; unsigned long *rflow_map; + unsigned long *rflow_map_reserved; struct udma_tchan *tchans; struct udma_rchan *rchans; @@ -535,6 +541,28 @@ static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr) } } +static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id) +{ + DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
+ if (id >= 0) { + if (test_bit(id, ud->rflow_map)) { + dev_err(ud->dev, "rflow%d is in use\n", id); + return ERR_PTR(-ENOENT); + } + } else { + bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved, + ud->rflow_cnt);
+ id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt); + if (id >= ud->rflow_cnt) + return ERR_PTR(-ENOENT); + }
+ __set_bit(id, ud->rflow_map); + return &ud->rflows[id]; +}
#define UDMA_RESERVE_RESOURCE(res) \ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ int id) \ @@ -557,7 +585,6 @@ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \ UDMA_RESERVE_RESOURCE(tchan); UDMA_RESERVE_RESOURCE(rchan); -UDMA_RESERVE_RESOURCE(rflow); static int udma_get_tchan(struct udma_chan *uc) { @@ -1103,14 +1130,129 @@ static int udma_get_mmrs(struct udevice *dev) return 0; } -#define UDMA_MAX_CHANNELS 192 +static int udma_setup_resources(struct udma_dev *ud) +{ + struct udevice *dev = ud->dev; + int ch_count, i; + u32 cap2, cap3; + struct ti_sci_resource_desc *rm_desc; + struct ti_sci_resource *rm_res; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + static const char * const range_names[] = { "ti,sci-rm-range-tchan", + "ti,sci-rm-range-rchan", + "ti,sci-rm-range-rflow" };
+ cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); + cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+ ud->rflow_cnt = cap3 & 0x3fff; + ud->tchan_cnt = cap2 & 0x1ff; + ud->echan_cnt = (cap2 >> 9) & 0x1ff; + ud->rchan_cnt = (cap2 >> 18) & 0x1ff; + ch_count = ud->tchan_cnt + ud->rchan_cnt;
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), + GFP_KERNEL); + ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), GFP_KERNEL); + ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), + sizeof(unsigned long), + GFP_KERNEL); + ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), + GFP_KERNEL);
+ if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map || + !ud->rflow_map_reserved || !ud->tchans || !ud->rchans || + !ud->rflows) + return -ENOMEM;
+ /* + * RX flows with the same Ids as RX channels are reserved to be used + * as default flows if remote HW can't generate flow_ids. Those + * RX flows can be requested only explicitly by id. + */ + bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
+ /* Get resource ranges from tisci */ + for (i = 0; i < RM_RANGE_LAST; i++) + tisci_rm->rm_ranges[i] = + devm_ti_sci_get_of_resource(ud->tisci, dev, + ud->tisci_dev_id, + (char *)range_names[i]);
+ /* tchan ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->tchan_map, ud->tchan_cnt); + } else { + bitmap_fill(ud->tchan_map, ud->tchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->tchan_map, rm_desc->start, + rm_desc->num); + } + } + /* rchan and matching default flow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; + if (IS_ERR(rm_res)) { + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + bitmap_zero(ud->rflow_map, ud->rchan_cnt); + } else { + bitmap_fill(ud->rchan_map, ud->rchan_cnt); + bitmap_fill(ud->rflow_map, ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rchan_map, rm_desc->start, + rm_desc->num); + bitmap_clear(ud->rflow_map, rm_desc->start, + rm_desc->num); + } + }
+ /* GP rflow ranges */ + rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; + if (IS_ERR(rm_res)) { + bitmap_clear(ud->rflow_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + } else { + bitmap_set(ud->rflow_map, ud->rchan_cnt, + ud->rflow_cnt - ud->rchan_cnt); + for (i = 0; i < rm_res->sets; i++) { + rm_desc = &rm_res->desc[i]; + bitmap_clear(ud->rflow_map, rm_desc->start, + rm_desc->num); + } + }
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); + ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); + if (!ch_count) + return -ENODEV;
+ ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), + GFP_KERNEL); + if (!ud->channels) + return -ENOMEM;
it will allocate ud->channels twice, right?
Right, will drop the second allocation.
+ dev_info(dev, + "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n", + ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt, + ud->rflow_cnt);
+ return ch_count; +} static int udma_probe(struct udevice *dev) { struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct udma_dev *ud = dev_get_priv(dev); int i, ret; - u32 cap2, cap3; struct udevice *tmp; struct udevice *tisci_dev = NULL; @@ -1170,14 +1312,10 @@ static int udma_probe(struct udevice *dev) ud->is_coherent = dev_read_bool(dev, "dma-coherent"); - cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); - cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
- ud->rflow_cnt = cap3 & 0x3fff; - ud->tchan_cnt = cap2 & 0x1ff; - ud->echan_cnt = (cap2 >> 9) & 0x1ff; - ud->rchan_cnt = (cap2 >> 18) & 0x1ff; - ud->ch_count = ud->tchan_cnt + ud->rchan_cnt; + ud->dev = dev; + ud->ch_count = udma_setup_resources(ud); + if (ud->ch_count <= 0) + return ud->ch_count; dev_info(dev, "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n", @@ -1187,21 +1325,8 @@ static int udma_probe(struct udevice *dev) ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels), GFP_KERNEL);
^^^
- ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, - sizeof(*ud->tchans), GFP_KERNEL); - ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, - sizeof(*ud->rchans), GFP_KERNEL); - ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, - sizeof(*ud->rflows), GFP_KERNEL);
- if (!ud->channels || !ud->tchan_map || !ud->rchan_map || - !ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows)
+ if (!ud->channels) return -ENOMEM; for (i = 0; i < ud->tchan_cnt; i++) {
Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain.
Reviewed-by: Grygorii Strashko grygorii.strashko@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/soc/ti/k3-navss-ringacc.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index 64ebc0ba0030..08b476d21049 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -807,6 +807,11 @@ static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem)
memcpy(elem_ptr, elem, (4 << ring->elm_size));
+ flush_dcache_range((unsigned long)ring->ring_mem_virt, + ALIGN((unsigned long)ring->ring_mem_virt + + ring->size * (4 << ring->elm_size), + ARCH_DMA_MINALIGN)); + ring->windex = (ring->windex + 1) % ring->size; ring->free--; ringacc_writel(1, &ring->rt->db); @@ -823,6 +828,11 @@ static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem)
elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->rindex);
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt, + ALIGN((unsigned long)ring->ring_mem_virt + + ring->size * (4 << ring->elm_size), + ARCH_DMA_MINALIGN)); + memcpy(elem, elem_ptr, (4 << ring->elm_size));
ring->rindex = (ring->rindex + 1) % ring->size;
On Thu, Nov 14, 2019 at 02:44:24PM +0530, Vignesh Raghavendra wrote:
Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain.
Reviewed-by: Grygorii Strashko grygorii.strashko@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/soc/ti/k3-navss-ringacc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index 08b476d21049..c71f6576bdf8 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -941,7 +941,8 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc) ringacc->dma_ring_reset_quirk = dev_read_bool(dev, "ti,dma-ring-reset-quirk");
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev); + ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev, + "ti,sci", &tisci_dev); if (ret) { pr_debug("TISCI RA RM get failed (%d)\n", ret); ringacc->tisci = NULL;
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2380780879f5..b3947cbf432c 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1273,7 +1273,8 @@ static int udma_probe(struct udevice *dev) return -EINVAL; }
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev); + ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev, + "ti,sci", &tisci_dev); if (ret) { debug("TISCI RA RM get failed (%d)\n", ret); ud->tisci = NULL;
On 14/11/19 2:44 PM, Vignesh Raghavendra wrote:
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
drivers/dma/ti/k3-udma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2380780879f5..b3947cbf432c 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1273,7 +1273,8 @@ static int udma_probe(struct udevice *dev) return -EINVAL; }
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
- ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
"ti,sci", &tisci_dev);
Isn't this debug statement wrong?
Thanks and regards, Lokesh
ud->tisci = NULL;
Hi,
On 14/11/19 4:44 PM, Lokesh Vutla wrote:
On 14/11/19 2:44 PM, Vignesh Raghavendra wrote:
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
drivers/dma/ti/k3-udma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2380780879f5..b3947cbf432c 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1273,7 +1273,8 @@ static int udma_probe(struct udevice *dev) return -EINVAL; }
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
- ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
"ti,sci", &tisci_dev);Isn't this debug statement wrong?
Oops copy paste error, will for further comments before resending
Thanks and regards, Lokesh
ud->tisci = NULL;
Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 50 +++++++++++++--------------------------- 1 file changed, 16 insertions(+), 34 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index b3947cbf432c..75cd855e422b 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -98,7 +98,6 @@ struct udma_dev { const struct ti_sci_rm_psil_ops *tisci_psil_ops; u32 tisci_dev_id; u32 tisci_navss_dev_id; - bool is_coherent; };
struct udma_chan { @@ -273,11 +272,6 @@ static inline bool udma_is_chan_running(struct udma_chan *uc) return false; }
-static int udma_is_coherent(struct udma_chan *uc) -{ - return uc->ud->is_coherent; -} - static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) { struct k3_nav_ring *ring = NULL; @@ -1311,8 +1305,6 @@ static int udma_probe(struct udevice *dev) ud->tisci_psil_ops = &ud->tisci->ops.rm_psil_ops; }
- ud->is_coherent = dev_read_bool(dev, "dma-coherent"); - ud->dev = dev; ud->ch_count = udma_setup_resources(ud); if (ud->ch_count <= 0) @@ -1463,11 +1455,9 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)tr_desc, - ALIGN((u64)tr_desc + desc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)tr_desc, + ALIGN((u64)tr_desc + desc_size, + ARCH_DMA_MINALIGN));
k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc);
@@ -1632,14 +1622,12 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type); cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)dma_src, - ALIGN((u64)dma_src + len, - ARCH_DMA_MINALIGN)); - flush_dcache_range((u64)desc_tx, - ALIGN((u64)desc_tx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)dma_src, + ALIGN((u64)dma_src + len, + ARCH_DMA_MINALIGN)); + flush_dcache_range((u64)desc_tx, + ALIGN((u64)desc_tx + uc->hdesc_size, + ARCH_DMA_MINALIGN));
ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx); if (ret) { @@ -1683,19 +1671,15 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata) }
/* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)desc_rx, - (ulong)(desc_rx + uc->hdesc_size)); - } + invalidate_dcache_range((ulong)desc_rx, + (ulong)(desc_rx + uc->hdesc_size));
cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
/* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)buf_dma, - (ulong)(buf_dma + buf_dma_len)); - } + invalidate_dcache_range((ulong)buf_dma, + (ulong)(buf_dma + buf_dma_len));
cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
@@ -1800,11 +1784,9 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)desc_rx, - ALIGN((u64)desc_rx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)desc_rx, + ALIGN((u64)desc_rx + uc->hdesc_size, + ARCH_DMA_MINALIGN));
k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);
Fix up the debug prints that were dumping state of TCHAN RT registers to use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 75cd855e422b..35a16095b94f 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -426,9 +426,9 @@ static int udma_start(struct udma_chan *uc)
pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n", __func__, - udma_rchanrt_read(uc->rchan, + udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG), - udma_rchanrt_read(uc->rchan, + udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG)); break; case DMA_MEM_TO_MEM:
Exposed ring mode works well with 32 bit and 64 bit cores without need for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 35a16095b94f..0e22a08ff279 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -758,7 +758,7 @@ static int udma_alloc_tx_resources(struct udma_chan *uc) memset(&ring_cfg, 0, sizeof(ring_cfg)); ring_cfg.size = 16; ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8; - ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE; + ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg); ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg); @@ -835,7 +835,7 @@ static int udma_alloc_rx_resources(struct udma_chan *uc) memset(&ring_cfg, 0, sizeof(ring_cfg)); ring_cfg.size = 16; ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8; - ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE; + ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg); ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
UDMA always expects 64 bit address pointer of the transfer descriptor in the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size. Therefore copy over 32 bit pointer value to 64 bit variable before pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 0e22a08ff279..a562dc165b73 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1368,6 +1368,14 @@ static int udma_probe(struct udevice *dev) return ret; }
+static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem) +{ + u64 addr = 0; + + memcpy(&addr, &elem, sizeof(elem)); + return k3_nav_ringacc_ring_push(ring, &addr); +} + static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, dma_addr_t src, size_t len) { @@ -1459,7 +1467,7 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, ALIGN((u64)tr_desc + desc_size, ARCH_DMA_MINALIGN));
- k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc); + udma_push_to_ring(uc->tchan->t_ring, tr_desc);
return 0; } @@ -1629,7 +1637,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) ALIGN((u64)desc_tx + uc->hdesc_size, ARCH_DMA_MINALIGN));
- ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx); + ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx); if (ret) { dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n", dma->id, ret); @@ -1788,7 +1796,7 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) ALIGN((u64)desc_rx + uc->hdesc_size, ARCH_DMA_MINALIGN));
- k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx); + udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
uc->num_rx_bufs++; uc->desc_rx_cur++;
Cast pointers properly so as to avoid warnings when driver is built for 32 bit platforms
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a562dc165b73..ebf773d9ca67 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1463,8 +1463,8 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
- flush_dcache_range((u64)tr_desc, - ALIGN((u64)tr_desc + desc_size, + flush_dcache_range((unsigned long)tr_desc, + ALIGN((unsigned long)tr_desc + desc_size, ARCH_DMA_MINALIGN));
udma_push_to_ring(uc->tchan->t_ring, tr_desc); @@ -1630,11 +1630,11 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type); cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
- flush_dcache_range((u64)dma_src, - ALIGN((u64)dma_src + len, + flush_dcache_range((unsigned long)dma_src, + ALIGN((unsigned long)dma_src + len, ARCH_DMA_MINALIGN)); - flush_dcache_range((u64)desc_tx, - ALIGN((u64)desc_tx + uc->hdesc_size, + flush_dcache_range((unsigned long)desc_tx, + ALIGN((unsigned long)desc_tx + uc->hdesc_size, ARCH_DMA_MINALIGN));
ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx); @@ -1792,8 +1792,8 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
- flush_dcache_range((u64)desc_rx, - ALIGN((u64)desc_rx + uc->hdesc_size, + flush_dcache_range((unsigned long)desc_rx, + ALIGN((unsigned long)desc_rx + uc->hdesc_size, ARCH_DMA_MINALIGN));
udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
Add new compatible to handle UDMA support for J721e SoC
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index ebf773d9ca67..7336bad99412 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1818,6 +1818,7 @@ static const struct dma_ops udma_ops = {
static const struct udevice_id udma_ids[] = { { .compatible = "ti,k3-navss-udmap" }, + { .compatible = "ti,j721e-navss-main-udmap" }, { } };
participants (4)
-
Grygorii Strashko -
Lokesh Vutla -
Tom Rini -
Vignesh Raghavendra