Some SoCs have different endianness of QSPI IP if compared to endianness of core. The function is_controller_busy() checks if the QSPI controller is busy or not, considering the endianness of the QSPI IP.

Signed-off-by: Rajat Srivastava rajat.srivastava@nxp.com Reviewed-by: York Sun york.sun@nxp.com --- drivers/spi/fsl_qspi.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index c201c7f823..e264709a3f 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -156,6 +156,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val) out_be32(addr, val) : out_le32(addr, val); }

+static inline int is_controller_busy(const struct fsl_qspi_priv *priv) +{ + u32 val; + const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK | + QSPI_SR_IP_ACC_MASK; + unsigned int retry = 5; + + do { + val = qspi_read32(priv->flags, &priv->regs->sr); + + if ((~val & mask) == mask) + return 0; + + udelay(1); + } while (--retry); + + return -ETIMEDOUT; +} + /* QSPI support swapping the flash read/write data * in hardware for LS102xA, but not for VF610 */ static inline u32 qspi_endian_xchg(u32 data) @@ -1020,11 +1039,7 @@ static int fsl_qspi_probe(struct udevice *bus) priv->num_chipselect = plat->num_chipselect;

/* make sure controller is not busy anywhere */ - ret = wait_for_bit_le32(&priv->regs->sr, - QSPI_SR_BUSY_MASK | - QSPI_SR_AHB_ACC_MASK | - QSPI_SR_IP_ACC_MASK, - false, 100, false); + ret = is_controller_busy(priv);

if (ret) { debug("ERROR : The controller is busy\n"); @@ -1187,11 +1202,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev) priv = dev_get_priv(bus);

/* make sure controller is not busy anywhere */ - ret = wait_for_bit_le32(&priv->regs->sr, - QSPI_SR_BUSY_MASK | - QSPI_SR_AHB_ACC_MASK | - QSPI_SR_IP_ACC_MASK, - false, 100, false); + ret = is_controller_busy(priv);

if (ret) { debug("ERROR : The controller is busy\n");