[U-Boot] [PATCH 1/2] armv8-fsl-layerscape:Kconfig: Support to RGMII for ls1088aqds
Add support RGMII protocol
Freescale's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Amrita Kumari amrita.kumari@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 14 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 +++++ board/freescale/ls1088a/eth_ls1088aqds.c | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 9 ++++++++ drivers/net/ldpaa_eth/ls1088a.c | 27 ++++++++++++++++++++++ include/configs/ls1088a_common.h | 1 + include/fsl-mc/ldpaa_wriop.h | 2 ++ 9 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8270431..fcde6e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -72,6 +72,9 @@ config ARCH_LS1088A select SYS_FSL_ERRATUM_A008850 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_HAS_RGMII
config ARCH_LS2080A bool @@ -406,6 +409,17 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool
+config SYS_FSL_EC1 + bool + +config SYS_FSL_EC2 + bool + +config SYS_HAS_RGMII + bool + depends on SYS_FSL_EC1 || SYS_FSL_EC2 + + config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 33288f9..371bf12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -28,6 +28,7 @@ #endif #include <fsl_immap.h>
+ DECLARE_GLOBAL_DATA_PTR;
struct mm_region *mem_map = early_map; @@ -506,6 +507,10 @@ int arch_early_init_r(void) printf("Did not wake secondary cores\n"); }
+#ifdef CONFIG_SYS_HAS_RGMII + fsl_rgmii_init(); +#endif + #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index a2c7578..12fd6b8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_get_number(int serdes, int cfg); +void fsl_rgmii_init(void);
#ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e181ef2..98fb346 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -244,6 +244,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_EC1_REGSR 26 +#define FSL_CHASSIS3_EC2_REGSR 26 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 3e78ac7..a73896d 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis)
/* Register the real MDIO1 bus */ fm_memac_mdio_init(bis, memac_mdio0_info); - /* Register the muxing front-ends to the MDIO buses */ ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1); ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2); diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index f7f26c2..831a330 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl) } }
+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if) +{ + dpmac_info[dpmac_id].enabled = 1; + dpmac_info[dpmac_id].id = dpmac_id; + dpmac_info[dpmac_id].phy_addr = -1; + dpmac_info[dpmac_id].enet_if = enet_if; +} + + /*TODO what it do */ static int wriop_dpmac_to_index(int dpmac_id) { diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 703945c..01e8ba4 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -8,6 +8,7 @@ #include <fsl-mc/ldpaa_wriop.h> #include <asm/io.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h>
u32 dpmac_to_devdisr[] = { [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, @@ -85,3 +86,29 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) break; } } + +#ifdef CONFIG_SYS_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK; + ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK; + ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII); +#endif +} +#endif diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 5432e4f..35e806e 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -21,6 +21,7 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT
+ /* Link Definitions */ #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x20100000 diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index 8ae0fc0..0ca4956 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -69,4 +69,6 @@ void wriop_dpmac_disable(int); void wriop_dpmac_enable(int); phy_interface_t wriop_dpmac_enet_if(int, int); void wriop_init_dpmac_qsgmii(int, int); +void wriop_init_rgmii(void); +void wriop_init_dpmac_enet_if(int , phy_interface_t); #endif /* __LDPAA_WRIOP_H */
From: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com
EC1 and EC2 are RGMII interface on ls1088aqds platform. This patch add support of RGMII with PHY and MDIO
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Amrita Kumari amrita.kumari@nxp.com --- board/freescale/ls1088a/eth_ls1088aqds.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index a73896d..da94fcc 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -576,6 +576,38 @@ void ls1088a_handle_phy_interface_xsgmii(int i) break; } } + +void ls1088a_handle_phy_interface_rgmii(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 serdes1_prtcl, cfg; + struct mii_dev *bus; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); + + switch (dpmac_id) { + case 4: + wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR); + dpmac_info[dpmac_id].board_mux = EMI1_RGMII1; + bus = mii_dev_for_muxval(EMI1_RGMII1); + wriop_set_mdio(dpmac_id, bus); + break; + case 5: + wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR); + dpmac_info[dpmac_id].board_mux = EMI1_RGMII2; + bus = mii_dev_for_muxval(EMI1_RGMII2); + wriop_set_mdio(dpmac_id, bus); + break; + default: + printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } + +} #endif
int board_eth_init(bd_t *bis) @@ -604,6 +636,9 @@ int board_eth_init(bd_t *bis)
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_RGMII: + ls1088a_handle_phy_interface_rgmii(i); + break; case PHY_INTERFACE_MODE_QSGMII: ls1088a_handle_phy_interface_qsgmii(i); break;
On 04/26/2017 08:45 AM, Amrita Kumari wrote:
From: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com
EC1 and EC2 are RGMII interface on ls1088aqds platform. This patch add support of RGMII with PHY and MDIO
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Amrita Kumari amrita.kumari@nxp.com
board/freescale/ls1088a/eth_ls1088aqds.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index a73896d..da94fcc 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -576,6 +576,38 @@ void ls1088a_handle_phy_interface_xsgmii(int i) break; } }
+void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
No reason this function needs to be global. Put a static in front of it. Do not send a patch to both internal and upstream lists in the same email.
York
On 04/26/2017 08:45 AM, Amrita Kumari wrote:
Add support RGMII protocol
Freescale's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Amrita Kumari amrita.kumari@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 14 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 +++++ board/freescale/ls1088a/eth_ls1088aqds.c | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 9 ++++++++ drivers/net/ldpaa_eth/ls1088a.c | 27 ++++++++++++++++++++++ include/configs/ls1088a_common.h | 1 + include/fsl-mc/ldpaa_wriop.h | 2 ++ 9 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8270431..fcde6e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -72,6 +72,9 @@ config ARCH_LS1088A select SYS_FSL_ERRATUM_A008850 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_HAS_RGMII
config ARCH_LS2080A bool
@@ -406,6 +409,17 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool
+config SYS_FSL_EC1
- bool
+config SYS_FSL_EC2
- bool
Please add "help" to explain what these two options are. The names are not revealing much. Do not send a patch to internal and upstream list in the same email.
York
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Amrita Kumari -
York Sun