This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51.

Changed in this version: - Added #ifdef CONFIG_MX51 around the workaround

Signed-off-by: David Jander david@protonic.nl --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index ee4150d..6c66b42 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */

- cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10

/* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif

mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */