[U-Boot] [PATCH 0/6] Addition of new board Peach-Pi
Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board.
Akshay Saraswat (5): Exynos5800: Introduce new proid for Exynos5800 Exynos5800: Add DTS for new board Peach-Pi Config: Exynos5800: Enable build for Peach-Pi Config: Exynos5420: Refactor SDRAM Bank and Size Exynos5: ddr3: Choose between single or double channel config
Alim Akhtar (1): DMC: Exynos5: Enable update mode for DREX controller
arch/arm/cpu/armv7/exynos/Kconfig | 5 +- arch/arm/cpu/armv7/exynos/clock.c | 19 +-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 29 +++++ arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 10 +- arch/arm/include/asm/arch-exynos/dmc.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h | 4 +- board/samsung/smdk5420/Kconfig | 16 +++ board/samsung/smdk5420/MAINTAINERS | 2 + configs/peach-pi_defconfig | 4 + drivers/gpio/s5p_gpio.c | 2 +- include/configs/exynos5420.h | 7 +- include/configs/peach-pi.h | 39 ++++++ include/configs/peach-pit.h | 8 +- include/configs/smdk5420.h | 4 + 18 files changed, 290 insertions(+), 24 deletions(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h
This patch intends to add a new proid for Exynos5800 which is a variant of Exynos5420. Product id for Exynos5800 is 0x5422. Both Exynos5420 and Exynos5800 are pin to pin compitable. This gives us an advantage of reusing Exynos5420 clock, pinmux, memory and other settings.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 19 ++++++++++--------- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/include/asm/arch-exynos/cpu.h | 10 +++++++++- arch/arm/include/asm/arch-exynos/gpio.h | 4 ++-- drivers/gpio/s5p_gpio.c | 2 +- 6 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 7558eff..4ecce44 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420()) + else if (proid_is_exynos5250() || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { @@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { @@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); } else { @@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); } else { @@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1682,7 +1683,7 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) + else if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_lcd_clk(); } } @@ -1696,7 +1697,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } else { diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index b6a9bc1..0aff3d0 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index b929486..17ae2e6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -834,7 +834,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..7c5c4ff 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -218,6 +218,13 @@ static inline void s5p_set_cpu_id(void) /* Exynos5420 */ s5p_cpu_id = 0x5420; break; + case 0x422: + /* + * Exynos5800 is a variant of Exynos5420 + * and has product id 0x5422 + */ + s5p_cpu_id = 0x5800; + break; } }
@@ -246,6 +253,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) +IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -256,7 +264,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420()) \ + if (proid_is_exynos5420() || proid_is_exynos5800()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 8fb5c23..32e045a 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1379,7 +1379,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1396,7 +1396,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index db7b673..bcf44eb 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -57,7 +57,7 @@ static inline int s5p_name_to_gpio(const char *name) */ #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) { tabp = exynos5420_gpio_table; irregular_bank_name = 'y'; irregular_set_number = '7';
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/Kconfig | 5 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++++++++++++ board/samsung/smdk5420/Kconfig | 16 ++++ board/samsung/smdk5420/MAINTAINERS | 2 + configs/peach-pi_defconfig | 4 + include/configs/exynos5420.h | 2 +- include/configs/peach-pi.h | 35 ++++++++ 8 files changed, 221 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index b6a558b..76c0faf 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -33,9 +33,12 @@ config TARGET_SNOW config TARGET_SMDK5420 bool "SMDK5420 board"
-config TARGET_PEACH_PIT +config TARGET_PEACH_PI bool "Peach Pi board"
+config TARGET_PEACH_PIT + bool "Peach Pit board" + endchoice
config SYS_CPU diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1ccd827..36e68d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -8,7 +8,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ - exynos5420-peach-pit.dtb + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..1c6aa8f --- /dev/null +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -0,0 +1,157 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5800", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1920>; + samsung,vl-row = <1080>; + samsung,vl-width = <1920>; + samsung,vl-height = <1080>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <80>; + samsung,vl-hbpd = <172>; + samsung,vl-hfpd = <60>; + samsung,vl-vspw = <10>; + samsung,vl-vbpd = <25>; + samsung,vl-vfpd = <10>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +}; diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index fb9bedd..b88722f 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,19 @@ +if TARGET_PEACH_PI + +config SYS_BOARD + string + default "smdk5420" + +config SYS_VENDOR + string + default "samsung" + +config SYS_CONFIG_NAME + string + default "peach-pi" + +endif + if TARGET_PEACH_PIT
config SYS_BOARD diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a8..25813d5 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -2,7 +2,9 @@ SMDK5420 BOARD M: Akshay Saraswat akshay.s@samsung.com S: Maintained F: board/samsung/smdk5420/ +F: include/configs/peach-pi.h F: include/configs/peach-pit.h +F: configs/peach-pi_defconfig F: configs/peach-pit_defconfig
SMDK5420 BOARD diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig new file mode 100644 index 0000000..8cb3946 --- /dev/null +++ b/configs/peach-pi_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PI=y diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index d2a9556..9780050 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -27,7 +27,7 @@
#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" +#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_MAX_I2C_NUM 11
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h new file mode 100644 index 0000000..b66b781 --- /dev/null +++ b/include/configs/peach-pi.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#include <configs/exynos5-dt.h> + +#include <configs/exynos5420.h> + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5800-peach-pi + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SYS_PROMPT "Peach-pi # " +#define CONFIG_IDENT_STRING " for Peach-pi" + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#endif /* __CONFIG_PEACH_PI_H */
We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++++++++++++ 2 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1ccd827..36e68d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -8,7 +8,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ - exynos5420-peach-pit.dtb + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..1c6aa8f --- /dev/null +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -0,0 +1,157 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5800", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1920>; + samsung,vl-row = <1080>; + samsung,vl-width = <1920>; + samsung,vl-height = <1080>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <80>; + samsung,vl-hbpd = <172>; + samsung,vl-hfpd = <60>; + samsung,vl-vspw = <10>; + samsung,vl-vbpd = <25>; + samsung,vl-vfpd = <10>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +};
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 20 +++++++++++--------- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/include/asm/arch-exynos/cpu.h | 11 ++++++++++- arch/arm/include/asm/arch-exynos/gpio.h | 4 ++-- drivers/gpio/s5p_gpio.c | 2 +- 6 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 7558eff..9c0d507 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -118,7 +118,9 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420()) + else if (proid_is_exynos5250() + || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@ -1581,7 +1583,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { @@ -1617,7 +1619,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { @@ -1630,7 +1632,7 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); } else { @@ -1643,7 +1645,7 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); } else { @@ -1654,7 +1656,7 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1668,7 +1670,7 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1682,7 +1684,7 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) + else if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_lcd_clk(); } } @@ -1696,7 +1698,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } else { diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index b6a9bc1..0aff3d0 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index b929486..17ae2e6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -834,7 +834,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..9f3672b 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -218,6 +218,13 @@ static inline void s5p_set_cpu_id(void) /* Exynos5420 */ s5p_cpu_id = 0x5420; break; + case 0x422: + /* + * Exynos5800 is a variant of Exynos5422 + * and has the same product id + */ + s5p_cpu_id = 0x5800; + break; } }
@@ -246,6 +253,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) +IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -256,7 +264,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420()) \ + if (proid_is_exynos5420() \ + || proid_is_exynos5800()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 8fb5c23..32e045a 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1379,7 +1379,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1396,7 +1396,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index db7b673..bcf44eb 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -57,7 +57,7 @@ static inline int s5p_name_to_gpio(const char *name) */ #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) { tabp = exynos5420_gpio_table; irregular_bank_name = 'y'; irregular_set_number = '7';
This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/Kconfig | 5 ++++- board/samsung/smdk5420/Kconfig | 16 ++++++++++++++++ board/samsung/smdk5420/MAINTAINERS | 2 ++ configs/peach-pi_defconfig | 4 ++++ include/configs/exynos5420.h | 3 ++- include/configs/peach-pi.h | 35 +++++++++++++++++++++++++++++++++++ include/configs/peach-pit.h | 4 ++-- 7 files changed, 65 insertions(+), 4 deletions(-) create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index b6a558b..76c0faf 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -33,9 +33,12 @@ config TARGET_SNOW config TARGET_SMDK5420 bool "SMDK5420 board"
-config TARGET_PEACH_PIT +config TARGET_PEACH_PI bool "Peach Pi board"
+config TARGET_PEACH_PIT + bool "Peach Pit board" + endchoice
config SYS_CPU diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index fb9bedd..b88722f 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,19 @@ +if TARGET_PEACH_PI + +config SYS_BOARD + string + default "smdk5420" + +config SYS_VENDOR + string + default "samsung" + +config SYS_CONFIG_NAME + string + default "peach-pi" + +endif + if TARGET_PEACH_PIT
config SYS_BOARD diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a8..25813d5 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -2,7 +2,9 @@ SMDK5420 BOARD M: Akshay Saraswat akshay.s@samsung.com S: Maintained F: board/samsung/smdk5420/ +F: include/configs/peach-pi.h F: include/configs/peach-pit.h +F: configs/peach-pi_defconfig F: configs/peach-pit_defconfig
SMDK5420 BOARD diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig new file mode 100644 index 0000000..8cb3946 --- /dev/null +++ b/configs/peach-pi_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PI=y diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index d2a9556..b3be3e7 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -10,6 +10,7 @@ #define __CONFIG_EXYNOS5420_H
#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ +#define CONFIG_EXYNOS5800 /* A variant of Exynos5420 (Exynos5 Family) */
#define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -27,7 +28,7 @@
#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" +#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_MAX_I2C_NUM 11
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h new file mode 100644 index 0000000..4517e0a --- /dev/null +++ b/include/configs/peach-pi.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#include <configs/exynos5-dt.h> + +#include <configs/exynos5420.h> + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5800-peach-pi + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SYS_PROMPT "Peach-Pi # " +#define CONFIG_IDENT_STRING " for Peach-Pi" + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 88c093f..92edea2 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -19,8 +19,8 @@ /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */
-#define CONFIG_SYS_PROMPT "Peach # " -#define CONFIG_IDENT_STRING " for Peach" +#define CONFIG_SYS_PROMPT "Peach-Pit # " +#define CONFIG_IDENT_STRING " for Peach-Pit"
#define CONFIG_VIDEO_PARADE
From: Alim Akhtar alim.akhtar@samsung.com
As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation.
Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 +++++++++++++++++++ arch/arm/include/asm/arch-exynos/dmc.h | 1 + 2 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index b86dd2d..4d73b45 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+ /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + return 0; } #endif diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index ec3f9b6..4990a1a 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24
Since, not every board may have all memory channels configured and all available banks of DMC used, we wish to refactor configs for Memory Bank size and numbers as per board memory config. For Example, Peach-Pit has 2GB memory and will be using only 4 banks but Peach-Pi has 3.5GB memory and will be using all 7 available SDRAM banks.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- include/configs/exynos5420.h | 4 ---- include/configs/peach-pi.h | 4 ++++ include/configs/peach-pit.h | 4 ++++ include/configs/smdk5420.h | 4 ++++ 4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index b3be3e7..0bd7446 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -46,8 +46,4 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
-/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 7 -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 4517e0a..829846e 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -32,4 +32,8 @@ #define LCD_BPP LCD_COLOR16 #endif
+/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 92edea2..35960d7 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -32,4 +32,8 @@ #define LCD_BPP LCD_COLOR16 #endif
+/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 606739b..dfad24c 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -24,4 +24,8 @@ #define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420"
+/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_SMDK5420_H */
Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.
Signed-off-by: Doug Anderson dianders@chromium.org Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4d73b45..7c0b12a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) + DMC_OFFSET); pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
+ if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT);
Hi Akshay,
On 8 October 2014 02:10, Akshay Saraswat akshay.s@samsung.com wrote:
Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board.
Akshay Saraswat (5): Exynos5800: Introduce new proid for Exynos5800 Exynos5800: Add DTS for new board Peach-Pi Config: Exynos5800: Enable build for Peach-Pi Config: Exynos5420: Refactor SDRAM Bank and Size Exynos5: ddr3: Choose between single or double channel config
Alim Akhtar (1): DMC: Exynos5: Enable update mode for DREX controller
I was not able to apply this to samsung/master. I fiddled a bit and got it to build (see u-boot-x86.git branch pi-working) but it would not boot over USB A-A. It hung in SPL. I may have used an incorrect option though.
Regards, Simon
participants (2)
-
Akshay Saraswat -
Simon Glass