Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
From: Marek Vasut Date: 2015-12-23 10:07 To: ShengjiangWu CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Wednesday, December 23, 2015 9:25 AM To: 圣江 吴 Cc: u-boot@lists.denx.de; clsee@altera.com; dinguyen@opensource.altera.com; dinh.linux@gmail.com; pavel@denx.de; sr@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
On Dec 22, 2015, at 12:33 PM, Marek Vasut marex@denx.de wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.
Signed-off-by: shengjiangwu shengjiangwu@icloud.com Cc: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Dinh Nguyen dinh.linux@gmail.com Cc: Pavel Machek pavel@denx.de Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot- socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still some problems.
Best regards, Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log.
Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
[...]
Best regards, Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset resetting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272
=>
Best Regards, ShengjiangWu
On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
From: Marek Vasut Date: 2015-12-23 10:07 To: ShengjiangWu CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Wednesday, December 23, 2015 9:25 AM To: 圣江 吴 Cc: u-boot@lists.denx.de; clsee@altera.com; dinguyen@opensource.altera.com; dinh.linux@gmail.com; pavel@denx.de; sr@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
On Dec 22, 2015, at 12:33 PM, Marek Vasut marex@denx.de wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock.
Signed-off-by: shengjiangwu shengjiangwu@icloud.com Cc: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Dinh Nguyen dinh.linux@gmail.com Cc: Pavel Machek pavel@denx.de Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot- socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still some problems.
Best regards, Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log.
Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
[...]
Best regards, Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset resetting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
From: Marek Vasut Date: 2015-12-23 10:07 To: ShengjiangWu CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Wednesday, December 23, 2015 9:25 AM To: 圣江 吴 Cc: u-boot@lists.denx.de; clsee@altera.com; dinguyen@opensource.altera.com; dinh.linux@gmail.com; pavel@denx.de; sr@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
On Dec 22, 2015, at 12:33 PM, Marek Vasut marex@denx.de wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > Updated pinmux group MIXED1IO[15-20] for QSPI. > Updated QSPI clock. > > Signed-off-by: shengjiangwu shengjiangwu@icloud.com > Cc: Chin Liang See clsee@altera.com > Cc: Dinh Nguyen dinguyen@opensource.altera.com > Cc: Dinh Nguyen dinh.linux@gmail.com > Cc: Pavel Machek pavel@denx.de > Cc: Marek Vasut marex@denx.de > Cc: Stefan Roese sr@denx.de
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot- socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still some problems.
Best regards, Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log.
Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
[...]
Best regards, Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset resetting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow
Thanks Chin Liang
On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
[..]
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow
Yup, it work for me too with the pinmux change and dcache on.
U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC spl: mmc boot mode: raw
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => dcache Data (writethrough) Cache is ON => usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb info 1: Hub, USB Revision 1.10 - U-Boot Root Hub - Class: Hub - PacketSize: 8 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 0.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
2: Mass Storage, USB Revision 2.0 - USB DISK 2.0 0781076602A6 - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x13fe Product 0x1e00 Version 1.16 Configuration: 1 - Interfaces: 1 Bus Powered 200mA Interface: 0 - Alternate Setting 0, Endpoints: 2 - Class Mass Storage, Transp. SCSI, Bulk only - Endpoint 1 In Bulk MaxPacket 512 - Endpoint 2 Out Bulk MaxPacket 512
Thanks Chin Liang
Thanks Chin Liang
On Wednesday, December 23, 2015 at 03:38:25 AM, Chin Liang See wrote:
On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
[..]
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
+-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow
Yup, it work for me too with the pinmux change and dcache on.
U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC spl: mmc boot mode: raw
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => dcache Data (writethrough) Cache is ON => usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb info 1: Hub, USB Revision 1.10
- U-Boot Root Hub
- Class: Hub
- PacketSize: 8 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 0.0 Configuration: 1
- Interfaces: 1 Self Powered 0mA Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
2: Mass Storage, USB Revision 2.0
USB DISK 2.0 0781076602A6- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x13fe Product 0x1e00 Version 1.16 Configuration: 1
- Interfaces: 1 Bus Powered 200mA Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- Endpoint 1 In Bulk MaxPacket 512
- Endpoint 2 Out Bulk MaxPacket 512
Cool, I will pick the patch shortly.
participants (3)
-
Chin Liang See -
Marek Vasut -
圣江 吴