From: Haibo Chen haibo.chen@nxp.com

Currently, after config the clock rate, delay 10ms, this is quite a rough method. Check the clock stable status in the present status register is enough.

Tested-by: Ji Luo ji.luo@nxp.com Signed-off-by: Haibo Chen haibo.chen@nxp.com --- drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 788677984b..0c866b168f 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -36,6 +36,7 @@ #include <dt-structs.h> #include <mapmem.h> #include <dm/ofnode.h> +#include <linux/iopoll.h>

#if !CONFIG_IS_ENABLED(BLK) #include "mmc_private.h" @@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) { struct fsl_esdhc *regs = priv->esdhc_regs; int div = 1; + u32 tmp; + int ret; #ifdef ARCH_MXC #ifdef CONFIG_MX53 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ @@ -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)

esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

- udelay(10000); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");

#ifdef CONFIG_FSL_USDHC esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);