commit 194dd74ad919e57026f385aaab7f89acf7ea79ef (DRA7: add ABB setup for MPU voltage domain)

Made an offset typo error by using 0x4A003B24 as the efuse offset for OPP_NOM. As per TI documentation, 0x4A003B24 is for OPP_OD, and 0x4A003B20 is for OPP_NOM. Fix the same.

Reported-by: Praveen Rao prao@ti.com Signed-off-by: Nishanth Menon nm@ti.com ---

Unfortunately, this happened to slip past my results as the sample I had used happened to have the same values for both registers.

Based on u-boot-arm 5e77a74 ARM: bcm2835: fix mbox POWER_STATE_RESP_ON value arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ff32807..7292161 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -432,7 +432,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, - .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118,