[U-Boot] Vitesse Phy not recognized VSC8211
Hi all
In porting from U-Boot 1.2 to U-boot 2009 i noticed that the phys on my board was not detected and defulted to Generic/Unrecognised; while looking through my code for U-boot 1.2 I found a phy_info struct for the Vitesse phys my board has( in drivers/tsec.c). The Same struck does not appear in U-boot 2009 (drivers/net/tsec.c) I presume that my predecessor defined the struct "phy_info_VSC8211". can I simply copy the struct into the nee U-boot code and how can I confirm that the struct contains valid settings?
struct phy_info phy_info_VSC8211 = { 0xfc4b, "Vitesse VSC8211", 4, (struct phy_cmd[]) { /* config */ /* Override PHY config settings */ {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, /* Set up the interface mode */ {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, /* Configure some basic stuff */ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ /* Read the Status (2x to make sure link is right) */ {MIIM_STATUS, miim_read, NULL}, /* Auto-negotiate */ {MIIM_STATUS, miim_read, &mii_parse_sr}, /* Read the status */ {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ {miim_end,} }, };
When i included the struct as is the my board with the MPC8548 ver1 cpu worked correctly but the board with ver2 CPU does not work. A would appeciate any help
thanks Hendrik
On Fri, Feb 13, 2009 at 6:36 AM, hendrik hendrik.vastech@gmail.com wrote:
Hi all
When i included the struct as is the my board with the MPC8548 ver1 cpu worked correctly but the board with ver2 CPU does not work. A would appeciate any help
In what way does it "not work"? the cpu version shouldn't affect PHY recognition. Is the board different? Does it have different PHYs?
Andy Fleming wrote:
On Fri, Feb 13, 2009 at 6:36 AM, hendrik hendrik.vastech@gmail.com wrote:
Hi all
When i included the struct as is the my board with the MPC8548 ver1 cpu worked correctly but the board with ver2 CPU does not work. A would appeciate any help
In what way does it "not work"? the cpu version shouldn't affect PHY recognition. Is the board different? Does it have different PHYs?
On both boards (CPU v1 and CPU v2 ) the phys are detected as the Vitesse VSC821, but someware in the the "miiphy_register" function in miiphyutil.c thinkgs go wrong on the board with the v2 CPU. The first symptom was the mesage:
miiphy_register: non unique device name ""
on deeper investigation i found that the phy names were jumbled garbage, as the lines below show: the NET name should reed Tsec0.
PHY is Vitesse VSC8211 (fc4b1) miiphy_register: added '��m@��v|�� ��n', read=0x1ffb2e7c, write=0x1ffb2e14
after a bit more digging I now thing the problem is in the Memory manager of the CPU but i do not know how to go about finding the problem. My first step is to look at the DDR setup then try to understand the differences between the v1 and v2 CPUs
If you have any links or help i would greatly appreciate it.
thanks hedrik
hendrik wrote:
Andy Fleming wrote:
On Fri, Feb 13, 2009 at 6:36 AM, hendrik hendrik.vastech@gmail.com wrote:
Hi all
When i included the struct as is the my board with the MPC8548 ver1 cpu worked correctly but the board with ver2 CPU does not work. A would appeciate any help
In what way does it "not work"? the cpu version shouldn't affect PHY recognition. Is the board different? Does it have different PHYs?
On both boards (CPU v1 and CPU v2 ) the phys are detected as the Vitesse VSC821, but someware in the the "miiphy_register" function in miiphyutil.c thinkgs go wrong on the board with the v2 CPU. The first symptom was the mesage:
miiphy_register: non unique device name ""on deeper investigation i found that the phy names were jumbled garbage, as the lines below show: the NET name should reed Tsec0.
PHY is Vitesse VSC8211 (fc4b1) miiphy_register: added '��m@��v|�� ��n', read=0x1ffb2e7c, write=0x1ffb2e14after a bit more digging I now thing the problem is in the Memory manager of the CPU but i do not know how to go about finding the problem. My first step is to look at the DDR setup then try to understand the differences between the v1 and v2 CPUs
If you have any links or help i would greatly appreciate it.
thanks hedrik
The jumbled contents found when looking for the phy name does not have anything to do with the phy code, it does however relate to differences between CPU rev1 and rev2 behaviour when using the BDI debugger.
U-boot 2009 checks to see if the L2 cache is enabled ( not caring if it is configured as SRAM or cache) and then moves the L2 base address register if CONFIG_SYS_INIT_L2_ADDR is defined and if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) which is probably true when booting CPU rev using a BDI.
undefine CONFIG_SYS_INIT_L2_ADDR and your problem should disappear pieter
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Andy Fleming -
hendrik -
Pieter