[U-Boot] [[Patch V2] mips: 00/16] add mips64 support to U-Boot
This patch add mips64 support. --- Change log for V2: - move mips64 build flags to cpu/mips64.mk - add cache size probe - remove cache.S
Zhizhou Zhang (16): add mips64 standalone support add cpu/mips64/Makefile add cpu/mips64/config.mk add cpu/mips64/cpu.c add cpu/mips64/interrupts.c add cpu/mips64/start.S add cpu/mips64/time.c Let UNCACHED_SDRAM be available to mips64 add cache description struct modify io operation for mips64 Make size_t equaled to unsigned long modify u-boot.lds for mips64 add board define in boards.cfg add mips64 standalone link script add configs/qemu-mips64.h modify qemu-mips/config.mk
arch/mips/config.mk | 4 + arch/mips/cpu/mips64/Makefile | 47 +++++ arch/mips/cpu/mips64/config.mk | 39 ++++ arch/mips/cpu/mips64/cpu.c | 133 +++++++++++++ arch/mips/cpu/mips64/interrupts.c | 39 ++++ arch/mips/cpu/mips64/start.S | 373 +++++++++++++++++++++++++++++++++++ arch/mips/cpu/mips64/time.c | 86 ++++++++ arch/mips/include/asm/addrspace.h | 2 +- arch/mips/include/asm/cache.h | 11 ++ arch/mips/include/asm/io.h | 18 +- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk | 3 +- board/qemu-mips/u-boot.lds | 8 + boards.cfg | 1 + examples/standalone/mips64.lds | 59 ++++++ include/configs/qemu-mips64.h | 171 ++++++++++++++++ 16 files changed, 1000 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h
Daniel Schwierzeck told me to do it with macro, But it seems not work. For u-boot.lds was genarete by gcc. It's hard to do that without a lot modify. --- arch/mips/config.mk | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..56996cc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,11 @@
CROSS_COMPILE ?= mips_4KC-
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds -mike
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger vapier@gentoo.org wrote:
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds -mike
Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also.
I think that's not good for modified too much files.
On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote:
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote:
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds
Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also.
why ? my suggestion shouldn't affect any other cpu config.mk. -mike
On 8/18/12, Mike Frysinger vapier@gentoo.org wrote:
On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote:
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote:
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds
Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also.
why ? my suggestion shouldn't affect any other cpu config.mk. -mike
Oh, I'm so sorry, I think that you mean to replace CONFIG_STANDALONE_LOAD_ADDR by DEFAULT_MIPS_STANDALONE_LOAD_ADDR. So your idea is to keep both CONFIG_STANDALONE_LOAD_ADDR and DEFAULT_MIPS_STANDALONE_LOAD_ADDR, one for mips64, anther for mips32. Actually I haven't test standalone example. I add standalone config and build option for I would get an error if didn't do that. It brings me a lot of mess. I want to disable stanalone support in TOP Makefile, could I do that?
On Saturday 18 August 2012 22:25:24 Zhi-zhou Zhang wrote:
On 8/18/12, Mike Frysinger vapier@gentoo.org wrote:
On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote:
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote:
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds
Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also.
why ? my suggestion shouldn't affect any other cpu config.mk.
Oh, I'm so sorry, I think that you mean to replace CONFIG_STANDALONE_LOAD_ADDR by DEFAULT_MIPS_STANDALONE_LOAD_ADDR. So your idea is to keep both CONFIG_STANDALONE_LOAD_ADDR and DEFAULT_MIPS_STANDALONE_LOAD_ADDR, one for mips64, anther for mips32. Actually I haven't test standalone example. I add standalone config and build option for I would get an error if didn't do that. It brings me a lot of mess. I want to disable stanalone support in TOP Makefile, could I do that?
i don't know what you mean. you should be able to do:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,8 @@
CROSS_COMPILE ?= mips_4KC-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) +DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
then in your arch/mips/mips64/config.mk, add this one line: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds
does that not work ? -mike
On 8/18/12, Mike Frysinger vapier@gentoo.org wrote:
On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote:
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote:
On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote:
--- a/arch/mips/config.mk +++ b/arch/mips/config.mk
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff80200000 -T mips64.lds
Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also.
why ? my suggestion shouldn't affect any other cpu config.mk. -mike
Oh, I'm so sorry, I think that you mean to replace CONFIG_STANDALONE_LOAD_ADDR by DEFAULT_MIPS_STANDALONE_LOAD_ADDR. So your idea is to keep both CONFIG_STANDALONE_LOAD_ADDR and DEFAULT_MIPS_STANDALONE_LOAD_ADDR, one for mips64, anther for mips32. Actually I haven't test standalone example. I add standalone config and build option for I would get an error if didn't do that. It brings me a lot of mess. I want to disable stanalone support in TOP Makefile, could I do that?
Dear Zhizhou Zhang,
In message 1345217476-32034-2-git-send-email-etou.zh@gmail.com you wrote:
Daniel Schwierzeck told me to do it with macro, But it seems not work. For u-boot.lds was genarete by gcc. It's hard to do that without a lot modify.
arch/mips/config.mk | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..56996cc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,11 @@
CROSS_COMPILE ?= mips_4KC-
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds
Please use a consistent style, use all uper or all lower case letters, i. e. make this 0xffffffff80200000 or 0xFFFFFFFF80200000.
Aloso, please make sure your patches are bisectable. This change adds a reference to mips64.lds, but does not add this file. That's bad.
Best regards,
Wolfgang Denk
--- arch/mips/cpu/mips64/Makefile | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 0000000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS-y = cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/config.mk | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/config.mk
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 0000000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip +
On Friday 17 August 2012 11:30:46 Zhizhou Zhang wrote:
--- /dev/null +++ b/arch/mips/cpu/mips64/config.mk
+ENDIANNESS = -EL
+MIPSFLAGS += $(ENDIANNESS)
seems to me this logic should get moved out of mips32/config.mk and into the top level mips config.mk -mike
add icache and dcache probe here. but scache was not probed. For I don't know how to determine it implemented or not. Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/cpu.c | 133 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/mips/cpu/mips64/cpu.c
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 0000000..ea9c28a --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * Zhi-zhou Zhang etou.zh@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips64\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + fprintf(stderr, "*** reset failed ***\n"); + return 0; +} + +static struct cache_desc icache, dcache; + +void cache_probe() +{ + int config, lsize; + + config = read_c0_config1(); + lsize = (config >> 19) & 7; + if (lsize) { /* icache present */ + icache.linesz = 2 << lsize; + icache.sets = 32 << (((config >> 22) + 1) & 7); + icache.ways = 1 + ((config >> 16) & 7); + icache.size = icache.sets * + icache.ways * + icache.linesz; + } + + lsize = (config >> 10) & 7; + if (lsize) { /* dcache present */ + dcache.linesz = 2 << lsize; + dcache.sets = 32 << (((config >> 13) + 1) & 7); + dcache.ways = 1 + ((config >> 7) & 7); + dcache.size = dcache.sets * + dcache.ways * + dcache.linesz; + } +} + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long addr, aend; + + /* aend will be miscalculated when size is zero, so we return here */ + if (size == 0) + return; + + addr = start_addr & ~(icache.linesz - 1); + aend = (start_addr + size - 1) & ~(icache.linesz - 1); + while (1) { + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += icache.linesz; + } + + addr = start_addr & ~(dcache.linesz - 1); + aend = (start_addr + size - 1) & ~(dcache.linesz - 1); + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long addr = start_addr & ~(dcache.linesz - 1); + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long addr = start_addr & ~(dcache.linesz - 1); + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +}
On Friday 17 August 2012 11:30:47 Zhizhou Zhang wrote:
--- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c
+void __attribute__((weak)) _machine_restart(void) +{ +}
change to __weak (include linux/compiler.h if you need to).
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{
- _machine_restart();
- fprintf(stderr, "*** reset failed ***\n");
- return 0;
+}
this function should never return. add a __noreturn to machine_restart().
+void cache_probe()
(void) -mike
On Sat, Aug 18, 2012 at 3:34 AM, Mike Frysinger vapier@gentoo.org wrote:
On Friday 17 August 2012 11:30:47 Zhizhou Zhang wrote:
--- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c
+void __attribute__((weak)) _machine_restart(void) +{ +}
change to __weak (include linux/compiler.h if you need to).
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{
_machine_restart();fprintf(stderr, "*** reset failed ***\n");return 0;+}
this function should never return. add a __noreturn to machine_restart().
+void cache_probe()
(void) -mike
Thanks for your concern, I will do as said.
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/interrupts.c | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/interrupts.c
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c new file mode 100644 index 0000000..f661fb0 --- /dev/null +++ b/arch/mips/cpu/mips64/interrupts.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * Zhi-zhou Zhang etou.zh@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mipsregs.h> + +void enable_interrupts(void) +{ + int status = read_c0_status(); + write_c0_status(status | ST0_IE); +} + +int disable_interrupts(void) +{ + int status = read_c0_status(); + write_c0_status(status & ~ST0_IE); + return status | ST0_IE; +}
remove cache init Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/start.S | 373 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 373 insertions(+) create mode 100644 arch/mips/cpu/mips64/start.S
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 0000000..375f0c7 --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,373 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + +#define RVECENT(f,n) \ + b f; \ + nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0) # U-boot entry point + RVECENT(reset,1) # software reboot + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) + RVECENT(romReserved,111) + XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector + RVECENT(romReserved,113) + RVECENT(romReserved,114) + RVECENT(romReserved,115) + RVECENT(romReserved,116) + RVECENT(romReserved,116) + RVECENT(romReserved,118) + RVECENT(romReserved,119) + RVECENT(romReserved,120) + RVECENT(romReserved,121) + RVECENT(romReserved,122) + RVECENT(romReserved,123) + RVECENT(romReserved,124) + RVECENT(romReserved,125) + RVECENT(romReserved,126) + RVECENT(romReserved,127) + + /* + * We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ + .align 4 +reset: + + /* Clear watch registers */ + dmtc0 zero, CP0_WATCHLO + dmtc0 zero, CP0_WATCHHI + + /* WP(Watch Pending), SW0/1 should be cleared */ + mtc0 zero, CP0_CAUSE + + setup_c0_status_reset + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +#endif + + /* Initialize $gp */ + bal 1f + nop + .dword _gp +1: + ld gp, 0(ra) + + dla t9, cache_probe + jalr t9 + nop + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* Initialize any external memory */ + dla t9, lowlevel_init + jalr t9 + nop + + /* ... and enable them */ + li t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG +#endif + + /* Set up temporary stack */ + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + dla sp, 0(t0) + + dla t9, board_init_f + jr t9 + nop + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 # set new stack pointer + + li t0, CONFIG_SYS_MONITOR_BASE + dla t3, in_ram + ld t2, -24(t3) # t2 <-- uboot_end_data + move t1, a2 + move s2, a2 # s2 <-- destination address + + /* + * Fix $gp: + * + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address + */ + move t8, gp + dsub gp, CONFIG_SYS_MONITOR_BASE + dadd gp, a2 # gp now adjusted + dsub s1, gp, t8 # s1 <-- relocation offset + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ + + /* + * Save destination address and size for dlater usage in flush_cache() + */ + move s0, a1 # save gd in s0 + move a0, t1 # a0 <-- destination addr + dsub a1, t2, t0 # a1 <-- size + +1: + lw t3, 0(t0) + sw t3, 0(t1) + daddu t0, 4 + ble t0, t2, 1b + daddu t1, 4 + + /* If caches were enabled, we would have to flush them here. */ + + /* a0 & a1 are already set up for flush_cache(start, size) */ + dla t9, flush_cache + jalr t9 + nop + + /* Jump to where we've relocated ourselves */ + daddi t0, s2, in_ram - _start + jr t0 + nop + + .dword _gp + .dword _GLOBAL_OFFSET_TABLE_ + .dword uboot_end_data + .dword uboot_end + .dword num_got_entries + +in_ram: + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. + */ + ld t3, -8(t0) # t3 <-- num_got_entries + ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + ld t9, -40(t0) # t9 <-- _gp + dsub t8, t9 # compute offset + dadd t8, t8, gp # t8 now holds relocated _G_O_T_ + daddi t8, t8, 16 # skipping first two entries + li t2, 2 +1: + ld t1, 0(t8) + beqz t1, 2f + dadd t1, s1 + sd t1, 0(t8) +2: + daddi t2, 1 + blt t2, t3, 1b + daddi t8, 8 + + /* Clear BSS */ + ld t1, -24(t0) # t1 <-- uboot_end_data + ld t2, -16(t0) # t2 <-- uboot_end + dadd t1, s1 # adjust pointers + dadd t2, s1 + + dsub t1, 8 +1: + daddi t1, 8 + bltl t1, t2, 1b + sd zero, 0(t1) + + move a0, s0 # a0 <-- gd + dla t9, board_init_r + jr t9 + move a1, s2 + + .end relocate_code + + /* Exception handlers */ +romReserved: + b romReserved + +romExcHandle: + b romExcHandle
On Friday 17 August 2012 11:30:49 Zhizhou Zhang wrote:
remove cache init
this commit message doesn't make much sense. if it meant to be covering what changed since v1, put it below the "---" marker below.
--- /dev/null +++ b/arch/mips/cpu/mips64/start.S
- .globl _start
- .text
+_start:
include linux/linkage.h, then use: ENTRY(_start)
you'll probably want to review the .S file for other places to use ENTRY() and LENTRY() and ENDPROC() and END(). -mike
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/time.c | 86 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c new file mode 100644 index 0000000..350896a --- /dev/null +++ b/arch/mips/cpu/mips64/time.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mipsregs.h> + +static unsigned long timestamp; + +/* how many counter cycles in a jiffy */ +#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + /* Set up the timer for the first expiration. */ + timestamp = 0; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); + + return 0; +} + +ulong get_timer(ulong base) +{ + unsigned int count; + unsigned int expirelo = read_c0_compare(); + + /* Check to see if we have missed any timestamps. */ + count = read_c0_count(); + while ((count - expirelo) < 0x7fffffff) { + expirelo += CYCLES_PER_JIFFY; + timestamp++; + } + write_c0_compare(expirelo); + + return (timestamp - base); +} + +void __udelay(unsigned long usec) +{ + unsigned int tmo; + + tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000)); + while ((tmo - read_c0_count()) < 0x7fffffff) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +}
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/addrspace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/cache.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 5406d5d..45e546d 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -33,4 +33,15 @@ #define ARCH_DMA_MINALIGN 128 #endif
+/* + * Descriptor for a cache + */ +struct cache_desc { + unsigned int size; /* total size */ + unsigned int waysize; /* Bytes per way */ + unsigned short sets; /* Number of lines per set */ + unsigned char ways; /* Number of ways */ + unsigned char linesz; /* Size of line in bytes */ +}; + #endif /* __MIPS_CACHE_H__ */
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/io.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 025012a..1b82c61 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base) */ extern inline phys_addr_t virt_to_phys(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif }
extern inline void * phys_to_virt(unsigned long address) { - return (void *)KSEG0ADDR(address); +#ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif }
/* @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif }
extern inline void * bus_to_virt(unsigned long address) { +#ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif }
/*
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/posix_types.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..0da1dde 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; +#ifndef CONFIG_MIPS64 + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t;
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- board/qemu-mips/u-boot.lds | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 9460b20..06db68d 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,11 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ +#if defined(CONFIG_64BIT) +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +#else OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS @@ -63,7 +67,11 @@ SECTIONS }
uboot_end_data = .; +#if defined(CONFIG_64BIT) + num_got_entries = (__got_end - __got_start) >> 3; +#else num_got_entries = (__got_end - __got_start) >> 2; +#endif
. = ALIGN(4); .sbss : { *(.sbss*) }
Same issue here with OUTPUT_FORMAT as the other linker script. On Aug 17, 2012 10:33 AM, "Zhizhou Zhang" etou.zh@gmail.com wrote:
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com
board/qemu-mips/u-boot.lds | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 9460b20..06db68d 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,11 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ +#if defined(CONFIG_64BIT) +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +#else OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS @@ -63,7 +67,11 @@ SECTIONS }
uboot_end_data = .;+#if defined(CONFIG_64BIT)
num_got_entries = (__got_end - __got_start) >> 3;+#else num_got_entries = (__got_end - __got_start) >> 2; +#endif
. = ALIGN(4); .sbss : { *(.sbss*) }-- 1.7.9.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- boards.cfg | 1 + 1 file changed, 1 insertion(+)
diff --git a/boards.cfg b/boards.cfg index fdb84ad..a6806b8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,7 @@ M5485GFE m68k mcf547x_8x m548xevb freescale - M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mips mips mips32 qemu-mips - - qemu-mips +qemu_mips64 mips mips64 qemu-mips - - qemu-mips64 vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- examples/standalone/mips64.lds | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000..00b96da --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +OUTPUT_ARCH(mips) +SECTIONS +{ + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata*) } + + . = ALIGN(4); + __bss_start = .; + .sbss (NOLOAD) : { *(.sbss*) } + .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } + + _end = .; +}
I think the OUTPUT_FORMAT line if wrong. This will produce little endian output even if explicitly told by command line switch -EB to make big endian. On Aug 17, 2012 10:33 AM, "Zhizhou Zhang" etou.zh@gmail.com wrote:
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com
examples/standalone/mips64.lds | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000..00b96da --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/*
- (C) Copyright 2003
- Wolfgang Denk Engineering, wd@denx.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +OUTPUT_ARCH(mips) +SECTIONS +{
.text :{*(.text*)}. = ALIGN(4);.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }. = ALIGN(4);.data : { *(.data*) }. = .;_gp = ALIGN(16) + 0x7ff0;.got : {__got_start = .;*(.got)__got_end = .;}.sdata : { *(.sdata*) }. = ALIGN(4);__bss_start = .;.sbss (NOLOAD) : { *(.sbss*) }.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }_end = .;+}
1.7.9.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Sat, Aug 18, 2012 at 1:08 AM, Andrew Dyer amdyer@gmail.com wrote:
I think the OUTPUT_FORMAT line if wrong. This will produce little endian output even if explicitly told by command line switch -EB to make big endian.
Yes, But if I want make it configureable, I should modify a lot in standalone/Makefile. I'm afraid that it will affect other boards' build. actually, I want disable mips64's standalone example in top Makefile.
2012/8/18 Zhi-zhou Zhang etou.zh@gmail.com:
On Sat, Aug 18, 2012 at 1:08 AM, Andrew Dyer amdyer@gmail.com wrote:
I think the OUTPUT_FORMAT line if wrong. This will produce little endian output even if explicitly told by command line switch -EB to make big endian.
Yes, But if I want make it configureable, I should modify a lot in standalone/Makefile. I'm afraid that it will affect other boards' build. actually, I want disable mips64's standalone example in top Makefile.
no, this is not necessary. Endianess handling for MIPS u-boot and standalone binaries is fixed since commit 6cb461b4f1531dbae5c0bae857f649b7943114ec
-- Regards, Zhizhou Zhang
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
2012/8/17 Zhizhou Zhang etou.zh@gmail.com:
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com
examples/standalone/mips64.lds | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000..00b96da --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/*
- (C) Copyright 2003
- Wolfgang Denk Engineering, wd@denx.de
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips")
this should be OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
anyway you should add this line to the existing mips.lds and wrap it with #ifdef CONFIG_64BIT
+OUTPUT_ARCH(mips) +SECTIONS +{
.text :{*(.text*)}. = ALIGN(4);.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }. = ALIGN(4);.data : { *(.data*) }. = .;_gp = ALIGN(16) + 0x7ff0;.got : {__got_start = .;*(.got)__got_end = .;}.sdata : { *(.sdata*) }. = ALIGN(4);__bss_start = .;.sbss (NOLOAD) : { *(.sbss*) }.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }_end = .;+}
1.7.9.5
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 include/configs/qemu-mips64.h
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h new file mode 100644 index 0000000..2f39494 --- /dev/null +++ b/include/configs/qemu-mips64.h @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for qemu-mips64 target. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS64 1 /* MIPS64 CPU core */ +#define CONFIG_64BIT 1 +#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MISC_INIT_R + +/*IP address is default used by Qemu*/ +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */ + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux\0" \ + "load=tftp ffffffff80500000 ${u-boot}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_DP83902A + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8) +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0) +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170) +#define CONFIG_SYS_ATA_DATA_OFFSET (0) +#define CONFIG_SYS_ATA_REG_OFFSET (0) +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000) + +#define CONFIG_SYS_IDE_MAXDEVICE (4) + +#define CONFIG_CMD_RARP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */ + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +#define CONFIG_SYS_MALLOC_LEN 128*1024 + +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 + +#define CONFIG_SYS_MHZ 132 + +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */ + +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_CMD_NO_FLASH +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +/* The following #defines are needed to get flash environment right */ +#undef CONFIG_SYS_TEXT_BASE +//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */ +#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x8000 + +#define CONFIG_ENV_OVERWRITE 1 + +#define MEM_SIZE 128 + +#undef CONFIG_MEMSIZE_IN_BYTES + +#define CONFIG_LZA + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */
2012/8/17 Zhizhou Zhang etou.zh@gmail.com:
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 include/configs/qemu-mips64.h
you should merge this patch with patch 13 with a commit message like
MIPS: add board support for qemu_mips64
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h new file mode 100644 index 0000000..2f39494 --- /dev/null +++ b/include/configs/qemu-mips64.h @@ -0,0 +1,171 @@ +/*
- (C) Copyright 2003
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/*
- This file contains the configuration parameters for qemu-mips64 target.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */ +#define CONFIG_64BIT 1 +#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MISC_INIT_R
+/*IP address is default used by Qemu*/ +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+#define CONFIG_BAUDRATE 115200
+/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs ${bootargs} " \"console=ttyS0,${baudrate} " \"panic=1\0" \"bootfile=/tftpboot/vmlinux\0" \"load=tftp ffffffff80500000 ${u-boot}\0" \""+#define CONFIG_BOOTCOMMAND ""
+/*
- BOOTP options
- */
+#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME
+/*
- Command line configuration.
- */
+#include <config_cmd_default.h> +#define CONFIG_DP83902A
+#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP
+#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300)
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8) +#define CONFIG_CONS_INDEX 1
+#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0) +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170) +#define CONFIG_SYS_ATA_DATA_OFFSET (0) +#define CONFIG_SYS_ATA_REG_OFFSET (0) +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+#define CONFIG_CMD_RARP
+/*
- Miscellaneous configurable options
- */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */
+#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+#define CONFIG_SYS_MHZ 132
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+/*-----------------------------------------------------------------------
- FLASH and environment organization
- */
+#define CONFIG_CMD_NO_FLASH +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS
+/* The following #defines are needed to get flash environment right */ +#undef CONFIG_SYS_TEXT_BASE +//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */ +#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_ENV_IS_NOWHERE 1
+/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_OVERWRITE 1
+#define MEM_SIZE 128
+#undef CONFIG_MEMSIZE_IN_BYTES
+#define CONFIG_LZA
+/*-----------------------------------------------------------------------
- Cache Configuration
- */
+#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif /* __CONFIG_H */
1.7.9.5
Though I defined CONFIG_SYS_TEXT_BASE in configs/qemu-mips64.h, but the value is still affected by this file. Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- board/qemu-mips/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..a1514a0 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,10 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # - +ifeq "$(CPU)" "mips" # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc00000
# RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif
2012/8/17 Zhizhou Zhang etou.zh@gmail.com:
Though I defined CONFIG_SYS_TEXT_BASE in configs/qemu-mips64.h, but the value is still affected by this file.
you should delete all CONFIG_SYS_TEXT_BASE definitions from this file. The board specific config header file is the only right place.
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com
board/qemu-mips/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..a1514a0 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,10 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu #
+ifeq "$(CPU)" "mips" # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc00000
# RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000
+endif
1.7.9.5
This patch add mips64 support. --- Change log for V2: - move mips64 build flags to cpu/mips64.mk - add cache size probe - remove cache.S
Zhizhou Zhang (16): add mips64 standalone support add cpu/mips64/Makefile add cpu/mips64/config.mk add cpu/mips64/cpu.c add cpu/mips64/interrupts.c add cpu/mips64/start.S add cpu/mips64/time.c Let UNCACHED_SDRAM be available to mips64 add cache description struct modify io operation for mips64 Make size_t equaled to unsigned long modify u-boot.lds for mips64 add board define in boards.cfg add mips64 standalone link script add configs/qemu-mips64.h modify qemu-mips/config.mk
arch/mips/config.mk | 4 + arch/mips/cpu/mips64/Makefile | 47 +++++ arch/mips/cpu/mips64/config.mk | 39 ++++ arch/mips/cpu/mips64/cpu.c | 133 +++++++++++++ arch/mips/cpu/mips64/interrupts.c | 39 ++++ arch/mips/cpu/mips64/start.S | 373 +++++++++++++++++++++++++++++++++++ arch/mips/cpu/mips64/time.c | 86 ++++++++ arch/mips/include/asm/addrspace.h | 2 +- arch/mips/include/asm/cache.h | 11 ++ arch/mips/include/asm/io.h | 18 +- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk | 3 +- board/qemu-mips/u-boot.lds | 8 + boards.cfg | 1 + examples/standalone/mips64.lds | 59 ++++++ include/configs/qemu-mips64.h | 171 ++++++++++++++++ 16 files changed, 1000 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h
Hi,
2012/8/17 Zhizhou Zhang etou.zh@gmail.com:
This patch add mips64 support.
Change log for V2:
- move mips64 build flags to cpu/mips64.mk
- add cache size probe
- remove cache.S
please add changelogs to the patches which you have changed since the previous submission
Zhizhou Zhang (16): add mips64 standalone support
please add the prefix "MIPS:" to all commit messages. That is what I actually meant in the other mail. Then you can simply do a git format-patches --subject-prefix "PATCH vN" ...
add cpu/mips64/Makefile add cpu/mips64/config.mk add cpu/mips64/cpu.c add cpu/mips64/interrupts.c add cpu/mips64/start.S add cpu/mips64/time.c
I think those patches could be squashed to a single patch with a commit message like:
MIPS: add support for MIPS64 CPUs
Let UNCACHED_SDRAM be available to mips64 add cache description struct modify io operation for mips64 Make size_t equaled to unsigned long modify u-boot.lds for mips64 add board define in boards.cfg add mips64 standalone link script add configs/qemu-mips64.h modify qemu-mips/config.mk
please use more descriptive commit messages for your changes. It should be clear what you have changed and why.
arch/mips/config.mk | 4 + arch/mips/cpu/mips64/Makefile | 47 +++++ arch/mips/cpu/mips64/config.mk | 39 ++++ arch/mips/cpu/mips64/cpu.c | 133 +++++++++++++ arch/mips/cpu/mips64/interrupts.c | 39 ++++ arch/mips/cpu/mips64/start.S | 373 +++++++++++++++++++++++++++++++++++ arch/mips/cpu/mips64/time.c | 86 ++++++++ arch/mips/include/asm/addrspace.h | 2 +- arch/mips/include/asm/cache.h | 11 ++ arch/mips/include/asm/io.h | 18 +- arch/mips/include/asm/posix_types.h | 12 +- board/qemu-mips/config.mk | 3 +- board/qemu-mips/u-boot.lds | 8 + boards.cfg | 1 + examples/standalone/mips64.lds | 59 ++++++ include/configs/qemu-mips64.h | 171 ++++++++++++++++ 16 files changed, 1000 insertions(+), 6 deletions(-) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h
-- 1.7.9.5
Daniel Schwierzeck told me to do it with macro, But it seems not work. For u-boot.lds was genarete by gcc. It's hard to do that without a lot modify. --- arch/mips/config.mk | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..56996cc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,11 @@
CROSS_COMPILE ?= mips_4KC-
+ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +endif
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
--- arch/mips/cpu/mips64/Makefile | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 0000000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS-y = cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/config.mk | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/config.mk
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 0000000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip +
add icache and dcache probe here. but scache was not probed. For I don't know how to determine it implemented or not. Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/cpu.c | 133 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/mips/cpu/mips64/cpu.c
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 0000000..ea9c28a --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * Zhi-zhou Zhang etou.zh@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips64\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + fprintf(stderr, "*** reset failed ***\n"); + return 0; +} + +static struct cache_desc icache, dcache; + +void cache_probe() +{ + int config, lsize; + + config = read_c0_config1(); + lsize = (config >> 19) & 7; + if (lsize) { /* icache present */ + icache.linesz = 2 << lsize; + icache.sets = 32 << (((config >> 22) + 1) & 7); + icache.ways = 1 + ((config >> 16) & 7); + icache.size = icache.sets * + icache.ways * + icache.linesz; + } + + lsize = (config >> 10) & 7; + if (lsize) { /* dcache present */ + dcache.linesz = 2 << lsize; + dcache.sets = 32 << (((config >> 13) + 1) & 7); + dcache.ways = 1 + ((config >> 7) & 7); + dcache.size = dcache.sets * + dcache.ways * + dcache.linesz; + } +} + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long addr, aend; + + /* aend will be miscalculated when size is zero, so we return here */ + if (size == 0) + return; + + addr = start_addr & ~(icache.linesz - 1); + aend = (start_addr + size - 1) & ~(icache.linesz - 1); + while (1) { + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += icache.linesz; + } + + addr = start_addr & ~(dcache.linesz - 1); + aend = (start_addr + size - 1) & ~(dcache.linesz - 1); + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long addr = start_addr & ~(dcache.linesz - 1); + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long addr = start_addr & ~(dcache.linesz - 1); + unsigned long aend = (stop - 1) & ~(dcache.linesz - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += dcache.linesz; + } +}
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/interrupts.c | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 arch/mips/cpu/mips64/interrupts.c
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c new file mode 100644 index 0000000..f661fb0 --- /dev/null +++ b/arch/mips/cpu/mips64/interrupts.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * Zhi-zhou Zhang etou.zh@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mipsregs.h> + +void enable_interrupts(void) +{ + int status = read_c0_status(); + write_c0_status(status | ST0_IE); +} + +int disable_interrupts(void) +{ + int status = read_c0_status(); + write_c0_status(status & ~ST0_IE); + return status | ST0_IE; +}
remove cache init Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/start.S | 373 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 373 insertions(+) create mode 100644 arch/mips/cpu/mips64/start.S
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 0000000..375f0c7 --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,373 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + +#define RVECENT(f,n) \ + b f; \ + nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0) # U-boot entry point + RVECENT(reset,1) # software reboot + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) + RVECENT(romReserved,111) + XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector + RVECENT(romReserved,113) + RVECENT(romReserved,114) + RVECENT(romReserved,115) + RVECENT(romReserved,116) + RVECENT(romReserved,116) + RVECENT(romReserved,118) + RVECENT(romReserved,119) + RVECENT(romReserved,120) + RVECENT(romReserved,121) + RVECENT(romReserved,122) + RVECENT(romReserved,123) + RVECENT(romReserved,124) + RVECENT(romReserved,125) + RVECENT(romReserved,126) + RVECENT(romReserved,127) + + /* + * We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ + .align 4 +reset: + + /* Clear watch registers */ + dmtc0 zero, CP0_WATCHLO + dmtc0 zero, CP0_WATCHHI + + /* WP(Watch Pending), SW0/1 should be cleared */ + mtc0 zero, CP0_CAUSE + + setup_c0_status_reset + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +#endif + + /* Initialize $gp */ + bal 1f + nop + .dword _gp +1: + ld gp, 0(ra) + + dla t9, cache_probe + jalr t9 + nop + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* Initialize any external memory */ + dla t9, lowlevel_init + jalr t9 + nop + + /* ... and enable them */ + li t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG +#endif + + /* Set up temporary stack */ + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + dla sp, 0(t0) + + dla t9, board_init_f + jr t9 + nop + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 # set new stack pointer + + li t0, CONFIG_SYS_MONITOR_BASE + dla t3, in_ram + ld t2, -24(t3) # t2 <-- uboot_end_data + move t1, a2 + move s2, a2 # s2 <-- destination address + + /* + * Fix $gp: + * + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address + */ + move t8, gp + dsub gp, CONFIG_SYS_MONITOR_BASE + dadd gp, a2 # gp now adjusted + dsub s1, gp, t8 # s1 <-- relocation offset + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ + + /* + * Save destination address and size for dlater usage in flush_cache() + */ + move s0, a1 # save gd in s0 + move a0, t1 # a0 <-- destination addr + dsub a1, t2, t0 # a1 <-- size + +1: + lw t3, 0(t0) + sw t3, 0(t1) + daddu t0, 4 + ble t0, t2, 1b + daddu t1, 4 + + /* If caches were enabled, we would have to flush them here. */ + + /* a0 & a1 are already set up for flush_cache(start, size) */ + dla t9, flush_cache + jalr t9 + nop + + /* Jump to where we've relocated ourselves */ + daddi t0, s2, in_ram - _start + jr t0 + nop + + .dword _gp + .dword _GLOBAL_OFFSET_TABLE_ + .dword uboot_end_data + .dword uboot_end + .dword num_got_entries + +in_ram: + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. + */ + ld t3, -8(t0) # t3 <-- num_got_entries + ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + ld t9, -40(t0) # t9 <-- _gp + dsub t8, t9 # compute offset + dadd t8, t8, gp # t8 now holds relocated _G_O_T_ + daddi t8, t8, 16 # skipping first two entries + li t2, 2 +1: + ld t1, 0(t8) + beqz t1, 2f + dadd t1, s1 + sd t1, 0(t8) +2: + daddi t2, 1 + blt t2, t3, 1b + daddi t8, 8 + + /* Clear BSS */ + ld t1, -24(t0) # t1 <-- uboot_end_data + ld t2, -16(t0) # t2 <-- uboot_end + dadd t1, s1 # adjust pointers + dadd t2, s1 + + dsub t1, 8 +1: + daddi t1, 8 + bltl t1, t2, 1b + sd zero, 0(t1) + + move a0, s0 # a0 <-- gd + dla t9, board_init_r + jr t9 + move a1, s2 + + .end relocate_code + + /* Exception handlers */ +romReserved: + b romReserved + +romExcHandle: + b romExcHandle
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/cpu/mips64/time.c | 86 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/mips/cpu/mips64/time.c
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c new file mode 100644 index 0000000..350896a --- /dev/null +++ b/arch/mips/cpu/mips64/time.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mipsregs.h> + +static unsigned long timestamp; + +/* how many counter cycles in a jiffy */ +#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + /* Set up the timer for the first expiration. */ + timestamp = 0; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); + + return 0; +} + +ulong get_timer(ulong base) +{ + unsigned int count; + unsigned int expirelo = read_c0_compare(); + + /* Check to see if we have missed any timestamps. */ + count = read_c0_count(); + while ((count - expirelo) < 0x7fffffff) { + expirelo += CYCLES_PER_JIFFY; + timestamp++; + } + write_c0_compare(expirelo); + + return (timestamp - base); +} + +void __udelay(unsigned long usec) +{ + unsigned int tmo; + + tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000)); + while ((tmo - read_c0_count()) < 0x7fffffff) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +}
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/addrspace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/cache.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 5406d5d..45e546d 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -33,4 +33,15 @@ #define ARCH_DMA_MINALIGN 128 #endif
+/* + * Descriptor for a cache + */ +struct cache_desc { + unsigned int size; /* total size */ + unsigned int waysize; /* Bytes per way */ + unsigned short sets; /* Number of lines per set */ + unsigned char ways; /* Number of ways */ + unsigned char linesz; /* Size of line in bytes */ +}; + #endif /* __MIPS_CACHE_H__ */
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/io.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 025012a..1b82c61 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base) */ extern inline phys_addr_t virt_to_phys(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif }
extern inline void * phys_to_virt(unsigned long address) { - return (void *)KSEG0ADDR(address); +#ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif }
/* @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif }
extern inline void * bus_to_virt(unsigned long address) { +#ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif }
/*
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- arch/mips/include/asm/posix_types.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..0da1dde 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; +#ifndef CONFIG_MIPS64 + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t;
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- board/qemu-mips/u-boot.lds | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 9460b20..06db68d 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,11 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ +#if defined(CONFIG_64BIT) +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +#else OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS @@ -63,7 +67,11 @@ SECTIONS }
uboot_end_data = .; +#if defined(CONFIG_64BIT) + num_got_entries = (__got_end - __got_start) >> 3; +#else num_got_entries = (__got_end - __got_start) >> 2; +#endif
. = ALIGN(4); .sbss : { *(.sbss*) }
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- boards.cfg | 1 + 1 file changed, 1 insertion(+)
diff --git a/boards.cfg b/boards.cfg index fdb84ad..a6806b8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,7 @@ M5485GFE m68k mcf547x_8x m548xevb freescale - M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mips mips mips32 qemu-mips - - qemu-mips +qemu_mips64 mips mips64 qemu-mips - - qemu-mips64 vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- examples/standalone/mips64.lds | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 examples/standalone/mips64.lds
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000..00b96da --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +OUTPUT_ARCH(mips) +SECTIONS +{ + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata*) } + + . = ALIGN(4); + __bss_start = .; + .sbss (NOLOAD) : { *(.sbss*) } + .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } + + _end = .; +}
Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 include/configs/qemu-mips64.h
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h new file mode 100644 index 0000000..2f39494 --- /dev/null +++ b/include/configs/qemu-mips64.h @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for qemu-mips64 target. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS64 1 /* MIPS64 CPU core */ +#define CONFIG_64BIT 1 +#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MISC_INIT_R + +/*IP address is default used by Qemu*/ +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */ + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux\0" \ + "load=tftp ffffffff80500000 ${u-boot}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_DP83902A + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE (0xffffffffb4000300) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8) +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0) +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170) +#define CONFIG_SYS_ATA_DATA_OFFSET (0) +#define CONFIG_SYS_ATA_REG_OFFSET (0) +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000) + +#define CONFIG_SYS_IDE_MAXDEVICE (4) + +#define CONFIG_CMD_RARP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_SYS_PROMPT "qemu-mips64 # " /* Monitor Command Prompt */ + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +#define CONFIG_SYS_MALLOC_LEN 128*1024 + +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 + +#define CONFIG_SYS_MHZ 132 + +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 /* Cached addr */ + +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_CMD_NO_FLASH +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +/* The following #defines are needed to get flash environment right */ +#undef CONFIG_SYS_TEXT_BASE +//#define CONFIG_SYS_TEXT_BASE 0xFfffFfffbfc00000 /* ROM Version */ +#define CONFIG_SYS_TEXT_BASE 0xffffffff80200000 /* RAM Version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x8000 + +#define CONFIG_ENV_OVERWRITE 1 + +#define MEM_SIZE 128 + +#undef CONFIG_MEMSIZE_IN_BYTES + +#define CONFIG_LZA + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */
Though I defined CONFIG_SYS_TEXT_BASE in configs/qemu-mips64.h, but the value is still affected by this file. Signed-off-by: Zhizhou Zhang etou.zh@gmail.com --- board/qemu-mips/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..a1514a0 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,10 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # - +ifeq "$(CPU)" "mips" # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc00000
# RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif
participants (6)
-
Andrew Dyer -
Daniel Schwierzeck -
Mike Frysinger -
Wolfgang Denk -
Zhi-zhou Zhang -
Zhizhou Zhang