[U-Boot] [PATCH 00/10] usb: dwc3: rework DWC3 and convert UniPhier xHCI driver to DM
Masahiro Yamada (10): usb: xhci: add struct devrequest declaration to xhci.h usb: dwc3: make DWC3 core support code into a driver usb: dwc3: add UniPhier specific glue layer ARM: uniphier: switch over to USB DM ARM: uniphier: enable DWC3 xHCI driver usb: uniphier: remove UniPhier xHCI driver ARM: uniphier: delete unnecessary xHCI pin-mux settings ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG ARM: dts: uniphier: add/update xHCI nodes ARM: uniphier: enable Generic EHCI for PH1-Pro4
arch/arm/Kconfig | 1 + arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 ++++ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 4 + arch/arm/dts/uniphier-ph1-pro4.dtsi | 32 ++++++-- arch/arm/dts/uniphier-ph1-pro5.dtsi | 32 ++++++-- arch/arm/dts/uniphier-proxstream2.dtsi | 32 ++++++-- arch/arm/mach-uniphier/clk/clk-pro4.c | 6 +- arch/arm/mach-uniphier/clk/clk-pro5.c | 6 +- arch/arm/mach-uniphier/clk/clk-pxs2.c | 6 +- arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12 --- arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 11 --- arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c | 7 -- arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c | 7 -- arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 11 --- configs/uniphier_ld20_defconfig | 1 + configs/uniphier_pro4_defconfig | 3 + configs/uniphier_pxs2_ld6b_defconfig | 1 + drivers/usb/host/Kconfig | 10 +-- drivers/usb/host/Makefile | 2 +- drivers/usb/host/dwc3-uniphier.c | 110 ++++++++++++++++++++++++++ drivers/usb/host/xhci-dwc3.c | 71 ++++++++++++++++- drivers/usb/host/xhci-uniphier.c | 85 -------------------- drivers/usb/host/xhci.h | 2 + include/configs/uniphier.h | 4 + include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 26 files changed, 300 insertions(+), 175 deletions(-) create mode 100644 drivers/usb/host/dwc3-uniphier.c delete mode 100644 drivers/usb/host/xhci-uniphier.c
If xhci.h is included without include/usb.h, the compiler complains like follows: warning: 'struct devrequest' declared inside parameter list
Teach the compiler that devrequest is a structure. I found no reason include include/usb.h from xhci.h.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/usb/host/xhci.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2afa386..16dd61a 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1252,6 +1252,8 @@ void xhci_acknowledge_event(struct xhci_ctrl *ctrl); union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int length, void *buffer); + +struct devrequest; int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, struct devrequest *req, int length, void *buffer); int xhci_check_maxpacket(struct usb_device *udev);
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
If xhci.h is included without include/usb.h, the compiler complains like follows: warning: 'struct devrequest' declared inside parameter list
Teach the compiler that devrequest is a structure. I found no reason include include/usb.h from xhci.h.
I still don't like the fact that you would now have to include usb.h in each driver instead of including it in xhci.h once.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
drivers/usb/host/xhci.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2afa386..16dd61a 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1252,6 +1252,8 @@ void xhci_acknowledge_event(struct xhci_ctrl *ctrl); union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int length, void *buffer);
+struct devrequest; int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, struct devrequest *req, int length, void *buffer); int xhci_check_maxpacket(struct usb_device *udev);
Synopsys DWC3 IP generally works with an SoC-specific glue layer. DT binding for that is like this:
usb3_glue { compatible = "foo,dwc3"; ...
usb3: usb3 { compatible = "snps,dwc3"; ... }; };
The glue layer initializes some SoC-specific parts, then populates the child DWC3 core. To see how it works, refer to
drivers/usb/dwc3/dwc3-exynos.c drivers/usb/dwc3/dwc3-keystone.c drivers/usb/dwc3/dwc3-omap.c drivers/usb/dwc3/dwc3-st.c
of Linux Kernel.
This commit implements a driver for "snps,dwc3", which allows to use the same binding in U-Boot. The glue layer can be simply implemented based on Simple Bus Uclass.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/usb/host/xhci-dwc3.c | 71 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 33961cd..c7c8324 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -9,8 +9,13 @@ */
#include <common.h> -#include <asm/io.h> +#include <dm/device.h> +#include <mapmem.h> +#include <linux/io.h> #include <linux/usb/dwc3.h> +#include <linux/sizes.h> + +#include "xhci.h"
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) { @@ -97,3 +102,67 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | GFLADJ_30MHZ(val)); } + +struct dwc3_priv { + struct xhci_ctrl ctrl; /* should be the first member */ + void __iomem *regs; +}; + +static int dwc3_probe(struct udevice *dev) +{ + struct dwc3_priv *priv = dev_get_priv(dev); + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + fdt_addr_t base; + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_sysmem(base, SZ_32K); + if (!priv->regs) + return -ENOMEM; + + hccr = priv->regs; + + hcor = priv->regs + HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + + ret = dwc3_core_init(priv->regs + DWC3_REG_OFFSET); + if (ret) { + puts("XHCI: failed to initialize controller\n"); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(priv->regs + DWC3_REG_OFFSET, DWC3_GCTL_PRTCAP_HOST); + + return xhci_register(dev, hccr, hcor); +} + +static int dwc3_remove(struct udevice *dev) +{ + struct dwc3_priv *priv = dev_get_priv(dev); + + xhci_deregister(dev); + unmap_sysmem(priv->regs); + + return 0; +} + +static const struct udevice_id of_dwc3_match[] = { + { .compatible = "snps,dwc3" }, + { .compatible = "synopsys,dwc3" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3) = { + .name = "dwc3", + .id = UCLASS_USB, + .of_match = of_dwc3_match, + .probe = dwc3_probe, + .remove = dwc3_remove, + .ops = &xhci_usb_ops, + .priv_auto_alloc_size = sizeof(struct dwc3_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Synopsys DWC3 IP generally works with an SoC-specific glue layer. DT binding for that is like this:
usb3_glue { compatible = "foo,dwc3"; ...
usb3: usb3 { compatible = "snps,dwc3"; ... };};
The glue layer initializes some SoC-specific parts, then populates the child DWC3 core. To see how it works, refer to
drivers/usb/dwc3/dwc3-exynos.c drivers/usb/dwc3/dwc3-keystone.c drivers/usb/dwc3/dwc3-omap.c drivers/usb/dwc3/dwc3-st.c
of Linux Kernel.
This commit implements a driver for "snps,dwc3", which allows to use the same binding in U-Boot. The glue layer can be simply implemented based on Simple Bus Uclass.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Reviewed-by: Marek Vasut marex@denx.de
drivers/usb/host/xhci-dwc3.c | 71 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 33961cd..c7c8324 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -9,8 +9,13 @@ */
#include <common.h> -#include <asm/io.h> +#include <dm/device.h> +#include <mapmem.h> +#include <linux/io.h> #include <linux/usb/dwc3.h> +#include <linux/sizes.h>
+#include "xhci.h"
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) { @@ -97,3 +102,67 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | GFLADJ_30MHZ(val)); }
+struct dwc3_priv {
- struct xhci_ctrl ctrl; /* should be the first member */
- void __iomem *regs;
+};
+static int dwc3_probe(struct udevice *dev) +{
- struct dwc3_priv *priv = dev_get_priv(dev);
- struct xhci_hccr *hccr;
- struct xhci_hcor *hcor;
- fdt_addr_t base;
- int ret;
- base = dev_get_addr(dev);
- if (base == FDT_ADDR_T_NONE)
return -EINVAL;- priv->regs = map_sysmem(base, SZ_32K);
- if (!priv->regs)
return -ENOMEM;- hccr = priv->regs;
- hcor = priv->regs + HC_LENGTH(xhci_readl(&hccr->cr_capbase));
- ret = dwc3_core_init(priv->regs + DWC3_REG_OFFSET);
- if (ret) {
puts("XHCI: failed to initialize controller\n");return ret;- }
- /* We are hard-coding DWC3 core to Host Mode */
- dwc3_set_mode(priv->regs + DWC3_REG_OFFSET, DWC3_GCTL_PRTCAP_HOST);
- return xhci_register(dev, hccr, hcor);
+}
+static int dwc3_remove(struct udevice *dev) +{
- struct dwc3_priv *priv = dev_get_priv(dev);
- xhci_deregister(dev);
- unmap_sysmem(priv->regs);
- return 0;
+}
+static const struct udevice_id of_dwc3_match[] = {
- { .compatible = "snps,dwc3" },
- { .compatible = "synopsys,dwc3" },
- { /* sentinel */ }
+};
+U_BOOT_DRIVER(dwc3) = {
- .name = "dwc3",
- .id = UCLASS_USB,
- .of_match = of_dwc3_match,
- .probe = dwc3_probe,
- .remove = dwc3_remove,
- .ops = &xhci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct dwc3_priv),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
Add UniPhier platform specific glue layer to support USB3 Host mode on Synopsys DWC3 IP.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/usb/host/Kconfig | 7 +++ drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc3-uniphier.c | 110 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/usb/host/dwc3-uniphier.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d2363c8..b9eb5ed 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,13 @@ config USB_XHCI_UNIPHIER ---help--- Enables support for the on-chip xHCI controller on UniPhier SoCs.
+config USB_DWC3_UNIPHIER + bool "DesignWare USB3 Host Support on UniPhier Platforms" + depends on ARCH_UNIPHIER + help + Support of USB2/3 functionality in Socionext UniPhier platforms. + Say 'Y' here if you have one such device. + endif
config USB_OHCI_GENERIC diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 507519e..cc8b584 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o diff --git a/drivers/usb/host/dwc3-uniphier.c b/drivers/usb/host/dwc3-uniphier.c new file mode 100644 index 0000000..0571c6e --- /dev/null +++ b/drivers/usb/host/dwc3-uniphier.c @@ -0,0 +1,110 @@ +/* + * UniPhier Specific Glue Layer for DWC3 + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <dm/device.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define UNIPHIER_PRO4_DWC3_RESET 0x40 +#define UNIPHIER_PRO4_DWC3_RESET_XIOMMU BIT(5) +#define UNIPHIER_PRO4_DWC3_RESET_XLINK BIT(4) + +#define UNIPHIER_PRO5_DWC3_RESET 0x00 +#define UNIPHIER_PRO5_DWC3_RESET_XLINK BIT(15) +#define UNIPHIER_PRO5_DWC3_RESET_XIOMMU BIT(14) + +#define UNIPHIER_PXS2_DWC3_RESET 0x00 +#define UNIPHIER_PXS2_DWC3_RESET_XLINK BIT(15) + +static int uniphier_pro4_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET); + tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK; + writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET); + + return 0; +} + +static int uniphier_pro5_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET); + tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU; + writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET); + + return 0; +} + + +static int uniphier_pxs2_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET); + tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK | UNIPHIER_PXS2_DWC3_RESET_XIOMMU; + writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET); + + return 0; +} + +static int uniphier_dwc3_probe(struct udevice *dev) +{ + fdt_addr_t base; + void __iomem *regs; + int (*init)(void __iomem *regs); + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = map_sysmem(base, SZ_32K); + if (!regs) + return -ENOMEM; + + init = (int (*)(void __iomem *regs))dev_get_driver_data(dev); + ret = init(regs); + + unmap_sysmem(regs); + + return 0; +} + +static const struct udevice_id uniphier_dwc3_match[] = { + { + .compatible = "socionext,uniphier-pro4-dwc3", + .data = (ulong)uniphier_pro4_dwc3_init, + }, + { + .compatible = "socionext,uniphier-pro5-dwc3", + .data = (ulong)uniphier_pro5_dwc3_init, + }, + { + .compatible = "socionext,uniphier-pxs2-dwc3", + .data = (ulong)uniphier_pxs2_dwc3_init, + }, + { + .compatible = "socionext,uniphier-ld20-dwc3", + .data = (ulong)uniphier_pxs2_dwc3_init, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(usb_xhci) = { + .name = "uniphier-dwc3", + .id = UCLASS_SIMPLE_BUS, + .of_match = uniphier_dwc3_match, + .probe = uniphier_dwc3_probe, +};
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Add UniPhier platform specific glue layer to support USB3 Host mode on Synopsys DWC3 IP.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Reviewed-by: Marek Vasut marex@denx.de
drivers/usb/host/Kconfig | 7 +++ drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc3-uniphier.c | 110 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/usb/host/dwc3-uniphier.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d2363c8..b9eb5ed 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,13 @@ config USB_XHCI_UNIPHIER ---help--- Enables support for the on-chip xHCI controller on UniPhier SoCs.
+config USB_DWC3_UNIPHIER
- bool "DesignWare USB3 Host Support on UniPhier Platforms"
- depends on ARCH_UNIPHIER
- help
Support of USB2/3 functionality in Socionext UniPhier platforms.Say 'Y' here if you have one such device.endif
config USB_OHCI_GENERIC diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 507519e..cc8b584 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o diff --git a/drivers/usb/host/dwc3-uniphier.c b/drivers/usb/host/dwc3-uniphier.c new file mode 100644 index 0000000..0571c6e --- /dev/null +++ b/drivers/usb/host/dwc3-uniphier.c @@ -0,0 +1,110 @@ +/*
- UniPhier Specific Glue Layer for DWC3
- Copyright (C) 2016 Socionext Inc.
- Author: Masahiro Yamada yamada.masahiro@socionext.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <mapmem.h> +#include <dm/device.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/sizes.h>
+#define UNIPHIER_PRO4_DWC3_RESET 0x40 +#define UNIPHIER_PRO4_DWC3_RESET_XIOMMU BIT(5) +#define UNIPHIER_PRO4_DWC3_RESET_XLINK BIT(4)
+#define UNIPHIER_PRO5_DWC3_RESET 0x00 +#define UNIPHIER_PRO5_DWC3_RESET_XLINK BIT(15) +#define UNIPHIER_PRO5_DWC3_RESET_XIOMMU BIT(14)
+#define UNIPHIER_PXS2_DWC3_RESET 0x00 +#define UNIPHIER_PXS2_DWC3_RESET_XLINK BIT(15)
+static int uniphier_pro4_dwc3_init(void __iomem *regs) +{
- u32 tmp;
- tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET);
- tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK;
- writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET);
- return 0;
+}
+static int uniphier_pro5_dwc3_init(void __iomem *regs) +{
- u32 tmp;
- tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET);
- tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU;
- writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET);
I like how the bits doing exactly the same thing are always placed elsewhere :-)
- return 0;
+}
+static int uniphier_pxs2_dwc3_init(void __iomem *regs) +{
- u32 tmp;
- tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET);
- tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK | UNIPHIER_PXS2_DWC3_RESET_XIOMMU;
- writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET);
- return 0;
+}
+static int uniphier_dwc3_probe(struct udevice *dev) +{
- fdt_addr_t base;
- void __iomem *regs;
- int (*init)(void __iomem *regs);
- int ret;
- base = dev_get_addr(dev);
- if (base == FDT_ADDR_T_NONE)
return -EINVAL;- regs = map_sysmem(base, SZ_32K);
- if (!regs)
return -ENOMEM;- init = (int (*)(void __iomem *regs))dev_get_driver_data(dev);
- ret = init(regs);
- unmap_sysmem(regs);
- return 0;
+}
+static const struct udevice_id uniphier_dwc3_match[] = {
- {
.compatible = "socionext,uniphier-pro4-dwc3",.data = (ulong)uniphier_pro4_dwc3_init,- },
- {
.compatible = "socionext,uniphier-pro5-dwc3",.data = (ulong)uniphier_pro5_dwc3_init,- },
- {
.compatible = "socionext,uniphier-pxs2-dwc3",.data = (ulong)uniphier_pxs2_dwc3_init,- },
- {
.compatible = "socionext,uniphier-ld20-dwc3",.data = (ulong)uniphier_pxs2_dwc3_init,- },
- { /* sentinel */ }
+};
+U_BOOT_DRIVER(usb_xhci) = {
- .name = "uniphier-dwc3",
- .id = UCLASS_SIMPLE_BUS,
- .of_match = uniphier_dwc3_match,
- .probe = uniphier_dwc3_probe,
+};
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/Kconfig | 1 + include/configs/uniphier.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..59410cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -723,6 +723,7 @@ config ARCH_UNIPHIER select DM_SERIAL select DM_I2C select DM_MMC + select DM_USB help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 18cb963..868f001 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -136,6 +136,10 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION
+#ifdef CONFIG_USB_DWC3_UNIPHIER +#define CONFIG_USB_XHCI_DWC3 +#endif + /* SD/MMC */ #define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_GENERIC_MMC
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Please, do write commit messages.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
arch/arm/Kconfig | 1 + include/configs/uniphier.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..59410cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -723,6 +723,7 @@ config ARCH_UNIPHIER select DM_SERIAL select DM_I2C select DM_MMC
- select DM_USB help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 18cb963..868f001 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -136,6 +136,10 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION
+#ifdef CONFIG_USB_DWC3_UNIPHIER +#define CONFIG_USB_XHCI_DWC3
Could this be converted to Kconfig ?
+#endif
/* SD/MMC */ #define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_GENERIC_MMC
Hi Marek,
2016-05-11 20:26 GMT+09:00 Marek Vasut marex@denx.de:
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Please, do write commit messages.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
arch/arm/Kconfig | 1 + include/configs/uniphier.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..59410cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -723,6 +723,7 @@ config ARCH_UNIPHIER select DM_SERIAL select DM_I2C select DM_MMC
select DM_USB help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation)diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 18cb963..868f001 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -136,6 +136,10 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION
+#ifdef CONFIG_USB_DWC3_UNIPHIER +#define CONFIG_USB_XHCI_DWC3
Could this be converted to Kconfig ?
I noticed this task was not so easy as I had imagined first.
Before moving CONFIB_USB_XHCI_DWC3, I need to move CONFIG_USB_XHCI(_HCD) because USB_XHCI_DWC3 depends on USB_XHCI_HCD.
Before moving CONFIB_USB_XHCI(_HCD), I need to move CONFIG_USB because USB_XHCI(_HCD) depends on USB.
A problem here is that many boards define CONFIG_USB_XHCI without CONFIG_USB.
In spite of that fact, finally I managed to convert them and pass buildman test. So, v2 is out now.
On 05/16/2016 03:03 PM, Masahiro Yamada wrote:
Hi Marek,
2016-05-11 20:26 GMT+09:00 Marek Vasut marex@denx.de:
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Please, do write commit messages.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
arch/arm/Kconfig | 1 + include/configs/uniphier.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..59410cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -723,6 +723,7 @@ config ARCH_UNIPHIER select DM_SERIAL select DM_I2C select DM_MMC
select DM_USB help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation)diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 18cb963..868f001 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -136,6 +136,10 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION
+#ifdef CONFIG_USB_DWC3_UNIPHIER +#define CONFIG_USB_XHCI_DWC3
Could this be converted to Kconfig ?
I noticed this task was not so easy as I had imagined first.
Before moving CONFIB_USB_XHCI_DWC3, I need to move CONFIG_USB_XHCI(_HCD) because USB_XHCI_DWC3 depends on USB_XHCI_HCD.
Before moving CONFIB_USB_XHCI(_HCD), I need to move CONFIG_USB because USB_XHCI(_HCD) depends on USB.
A problem here is that many boards define CONFIG_USB_XHCI without CONFIG_USB.
In spite of that fact, finally I managed to convert them and pass buildman test. So, v2 is out now.
Thanks!
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
configs/uniphier_ld20_defconfig | 1 + configs/uniphier_pro4_defconfig | 1 + configs/uniphier_pxs2_ld6b_defconfig | 1 + 3 files changed, 3 insertions(+)
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig index cbc65dd..f340681 100644 --- a/configs/uniphier_ld20_defconfig +++ b/configs/uniphier_ld20_defconfig @@ -27,4 +27,5 @@ CONFIG_SPL_PINCTRL=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3_UNIPHIER=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 18f4caf..ab7b3f4 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -31,4 +31,5 @@ CONFIG_SPL_PINCTRL=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3_UNIPHIER=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index cf6d3e4..53cb5ce 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -32,4 +32,5 @@ CONFIG_SPL_PINCTRL=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3_UNIPHIER=y CONFIG_USB_STORAGE=y
UniPhier platform switched to DWC3 core with UniPhier specific glue layer to support USB3. This pre-DM driver is no longer needed.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/usb/host/Kconfig | 7 ---- drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-uniphier.c | 85 ---------------------------------------- include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 5 files changed, 95 deletions(-) delete mode 100644 drivers/usb/host/xhci-uniphier.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b9eb5ed..c0d85c8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -17,13 +17,6 @@ config USB_XHCI
if USB_XHCI_HCD
-config USB_XHCI_UNIPHIER - bool "Support for UniPhier on-chip xHCI USB controller" - depends on ARCH_UNIPHIER - default y - ---help--- - Enables support for the on-chip xHCI controller on UniPhier SoCs. - config USB_DWC3_UNIPHIER bool "DesignWare USB3 Host Support on UniPhier Platforms" depends on ARCH_UNIPHIER diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cc8b584..ff987f6 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -63,7 +63,6 @@ obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o -obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c deleted file mode 100644 index 1b3f3d2..0000000 --- a/drivers/usb/host/xhci-uniphier.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/err.h> -#include <linux/io.h> -#include <usb.h> -#include <fdtdec.h> -#include "xhci.h" - -static int get_uniphier_xhci_base(int index, struct xhci_hccr **base) -{ - DECLARE_GLOBAL_DATA_PTR; - int node_list[2]; - fdt_addr_t addr; - int count; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", - COMPAT_SOCIONEXT_XHCI, node_list, - ARRAY_SIZE(node_list)); - - if (index >= count) - return -ENODEV; - - addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg"); - if (addr == FDT_ADDR_T_NONE) - return -ENODEV; - - *base = (struct xhci_hccr *)addr; - - return 0; -} - -#define USB3_RST_CTRL 0x00100040 -#define IOMMU_RST_N (1 << 5) -#define LINK_RST_N (1 << 4) - -static void uniphier_xhci_reset(void __iomem *base, int on) -{ - u32 tmp; - - tmp = readl(base + USB3_RST_CTRL); - - if (on) - tmp &= ~(IOMMU_RST_N | LINK_RST_N); - else - tmp |= IOMMU_RST_N | LINK_RST_N; - - writel(tmp, base + USB3_RST_CTRL); -} - -int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) -{ - int ret; - struct xhci_hccr *cr; - struct xhci_hcor *or; - - ret = get_uniphier_xhci_base(index, &cr); - if (ret < 0) - return ret; - - uniphier_xhci_reset(cr, 0); - - or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase)); - - *hccr = cr; - *hcor = or; - - return 0; -} - -void xhci_hcd_stop(int index) -{ - int ret; - struct xhci_hccr *cr; - - ret = get_uniphier_xhci_base(index, &cr); - if (ret < 0) - return; - - uniphier_xhci_reset(cr, 1); -} diff --git a/include/fdtdec.h b/include/fdtdec.h index 37d482a..d1fddaa 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -158,7 +158,6 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ - COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 70acc29..e316cc8 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -63,7 +63,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(INTEL_ICH_SPI, "intel,ich-spi"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), - COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
UniPhier platform switched to DWC3 core with UniPhier specific glue layer to support USB3. This pre-DM driver is no longer needed.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Reviewed-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
Now UniPhier platform switched over to the DM-based xHCI driver. The pin-muxing for that is automatically cared by the pinctrl driver. These ad-hoc pin-muxing code is no longer needed.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12 ------------ arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 11 ----------- arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c | 7 ------- arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c | 7 ------- arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 11 ----------- 5 files changed, 48 deletions(-)
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c index 6066b16..0da280f 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c @@ -31,16 +31,4 @@ void uniphier_ld20_pin_init(void) sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ sg_set_iectrl_range(3, 17); #endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ - sg_set_iectrl_range(46, 53); -#endif } diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c index 913722b..f3b7115 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c @@ -32,15 +32,4 @@ void uniphier_ld6b_pin_init(void) sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */ sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */ #endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */ -#endif } diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c index 3796491..871d3ef 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c @@ -33,12 +33,5 @@ void uniphier_pro4_pin_init(void) /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ #endif
-#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c index 32ba923..58dff18 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c @@ -33,12 +33,5 @@ void uniphier_pro5_pin_init(void) sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */ #endif
-#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c index 2d62ab3..fc59205 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c @@ -32,15 +32,4 @@ void uniphier_pxs2_pin_init(void) sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */ sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */ #endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */ -#endif }
Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/clk/clk-pro4.c | 6 +++--- arch/arm/mach-uniphier/clk/clk-pro5.c | 6 +++--- arch/arm/mach-uniphier/clk/clk-pxs2.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 8746d7d..6a01543 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -15,7 +15,7 @@ void uniphier_pro4_clk_init(void)
/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | SC_RSTCTRL_NRST_GIO; #endif @@ -31,7 +31,7 @@ void uniphier_pro4_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */
-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; writel(tmp, SC_RSTCTRL2); @@ -40,7 +40,7 @@ void uniphier_pro4_clk_init(void)
/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c index 823bb06..dd86cad 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-pro5.c @@ -15,7 +15,7 @@ void uniphier_pro5_clk_init(void)
/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_NAND_DENALI @@ -24,7 +24,7 @@ void uniphier_pro5_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */
-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); @@ -33,7 +33,7 @@ void uniphier_pro5_clk_init(void)
/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 76bf856..3b50a20 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -15,7 +15,7 @@ void uniphier_pxs2_clk_init(void)
/* deassert reset */ tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; #endif #ifdef CONFIG_UNIPHIER_ETH @@ -27,7 +27,7 @@ void uniphier_pxs2_clk_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */
-#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); @@ -36,7 +36,7 @@ void uniphier_pxs2_clk_init(void)
/* provide clocks */ tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER +#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif
Adjust xHCI nodes to use the DWC3 core and the SoC-specific glue layer for former SoCs.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 +++++++++++++++++ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 4 ++++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 32 ++++++++++++++++++++++++-------- arch/arm/dts/uniphier-ph1-pro5.dtsi | 32 ++++++++++++++++++++++++-------- arch/arm/dts/uniphier-proxstream2.dtsi | 32 ++++++++++++++++++++++++-------- 5 files changed, 93 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi index f9cc3c4..5e2b595 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi @@ -256,6 +256,23 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + usb: usb@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3"; + reg = <0x65b00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, + <&pinctrl_usb2>, <&pinctrl_usb3>; + dwc3@65a00000 { + compatible = "snps,dwc3"; + reg = <0x65a00000 0x10000>; + interrupts = <0 134 4>; + tx-fifo-resize; + }; + }; }; };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 5be76e2..6cc5d1e 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -71,6 +71,10 @@ status = "okay"; };
+&usb1 { + status = "okay"; +}; + &usb2 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index d5767b6..7f42bc2 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -400,22 +400,38 @@ clocks = <&mio 4>, <&mio 6>; };
- usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb0: usb@65b00000 { + compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; + reg = <0x65b00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + dwc3@65a00000 { + compatible = "snps,dwc3"; + reg = <0x65a00000 0x10000>; + interrupts = <0 134 4>; + tx-fifo-resize; + }; };
- usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb1: usb@65d00000 { + compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; + reg = <0x65d00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + dwc3@65c00000 { + compatible = "snps,dwc3"; + reg = <0x65c00000 0x10000>; + interrupts = <0 137 4>; + tx-fifo-resize; + }; }; };
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index bd1b4b1..3036a76 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -379,22 +379,38 @@ bus-width = <4>; };
- usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb0: usb@65b00000 { + compatible = "socionext,uniphier-pro5-dwc3"; status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; + reg = <0x65b00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + dwc3@65a00000 { + compatible = "snps,dwc3"; + reg = <0x65a00000 0x10000>; + interrupts = <0 134 4>; + tx-fifo-resize; + }; };
- usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb1: usb@65d00000 { + compatible = "socionext,uniphier-pro5-dwc3"; status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; + reg = <0x65d00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + dwc3@65c00000 { + compatible = "snps,dwc3"; + reg = <0x65c00000 0x10000>; + interrupts = <0 137 4>; + tx-fifo-resize; + }; }; };
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 12968bd..8cff09c 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -383,22 +383,38 @@ bus-width = <4>; };
- usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb0: usb@65b00000 { + compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; + reg = <0x65b00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + dwc3@65a00000 { + compatible = "snps,dwc3"; + reg = <0x65a00000 0x10000>; + interrupts = <0 134 4>; + tx-fifo-resize; + }; };
- usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; + usb1: usb@65d00000 { + compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; + reg = <0x65d00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + dwc3@65c00000 { + compatible = "snps,dwc3"; + reg = <0x65c00000 0x10000>; + interrupts = <0 137 4>; + tx-fifo-resize; + }; }; };
On Driver Model USB, EHCI and xHCI can be enabled at the same time. PH1-Pro4 SoC has two EHCI cores and two xHCI cores, so enable the Generic EHCI driver.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
configs/uniphier_pro4_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index ab7b3f4..c50e403 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -32,4 +32,6 @@ CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3_UNIPHIER=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y
2016-05-11 19:28 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:
Masahiro Yamada (10): usb: xhci: add struct devrequest declaration to xhci.h usb: dwc3: make DWC3 core support code into a driver usb: dwc3: add UniPhier specific glue layer ARM: uniphier: switch over to USB DM ARM: uniphier: enable DWC3 xHCI driver usb: uniphier: remove UniPhier xHCI driver ARM: uniphier: delete unnecessary xHCI pin-mux settings ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG ARM: dts: uniphier: add/update xHCI nodes ARM: uniphier: enable Generic EHCI for PH1-Pro4
I included 01 because this is a prerequisite for 02.
I delegated 01-06 to Marek and 07-10 (follow-up cleanups) to me.
participants (2)
-
Marek Vasut -
Masahiro Yamada