[U-Boot] [PATCH 0/2] add support for LaCie CloudBox
These patches add support for the network storage LaCie CloudBox. The device shares one sata hardrive via a gigabit ethernet port. It is based on a Marvell Kirkwood 6702 soc.
From: Frédéric Leroy fredo@starox.org
The LaCie CloudBox device is a Kirkwood based nas :
- SoC: Marvell 88F6700 1000Mhz - SDRAM memory: 256MB DDR2 400Mhz - Gigabit ethernet: PHY Marvell 88E1318 - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - 1 push button - 1 reset switch - 1 SATA port - 1 LED (bi-color, blue and red)
Signed-off-by: Frédéric Leroy fredo@starox.org --- board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 104 ++++++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/lacie_kw.h | 8 +- 6 files changed, 361 insertions(+), 1 deletion(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
diff --git a/board/LaCie/cloudbox/Makefile b/board/LaCie/cloudbox/Makefile new file mode 100644 index 0000000..d656951 --- /dev/null +++ b/board/LaCie/cloudbox/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c new file mode 100644 index 0000000..6604a3c --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2013 Frederic Leroy fredo@starox.org + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "cloudbox.h" +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(CLOUDBOX_OE_VAL_LOW, CLOUDBOX_OE_VAL_HIGH, + CLOUDBOX_OE_LOW, CLOUDBOX_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_GPIO, /* hard disk power */ + MPP5_GPO, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP14_GPIO, /* LED red control */ + MPP15_SATA0_ACTn, /* LED blue control */ + MPP16_GPIO, /* power push buton */ + MPP17_GPIO, /* board power off */ + MPP20_GPIO, /* Ethernet PHY interrupt (WoL) */ + MPP28_GPIO, /* board revision (LSB) */ + MPP29_GPIO, /* board revision */ + MPP30_GPIO, /* board revision */ + MPP31_GPIO, /* board revision */ + MPP32_GPIO, /* board revision (MSB) */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Nothing to do with fdt */ + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1318_init("egiga0", 0); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return kw_gpio_get_value(CLOUDBOX_GPIO_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_button, + "Return GPIO button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/cloudbox/cloudbox.h b/board/LaCie/cloudbox/cloudbox.h new file mode 100644 index 0000000..fb8af83 --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 Frederic Leroy fredo@starox.org + * + * Based on LaCie u-boot sources + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CLOUDBOX_H +#define CLOUDBOX_H + +/* GPIO configuration */ +#define CLOUDBOX_OE_LOW 0xF0310000 +#define CLOUDBOX_OE_HIGH 0x00000001 +#define CLOUDBOX_OE_VAL_LOW 0x00000010 +#define CLOUDBOX_OE_VAL_HIGH 0x00000000 + +#define CLOUDBOX_GPIO_BUTTON 16 + +#endif /* CLOUDBOX_H */ diff --git a/board/LaCie/cloudbox/kwbimage.cfg b/board/LaCie/cloudbox/kwbimage.cfg new file mode 100644 index 0000000..a6a8ff9 --- /dev/null +++ b/board/LaCie/cloudbox/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Dram configuration based on Lacie u-boot sources +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +#Dram initalization for DDR2 256MB, 400MHz, 1CS +DATA 0xFFD01400 0x43010C30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38743000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 7= 5.5 cycles: Recommended for CL 6. + +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22135551 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000032 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000C # DDR Address Control +# This value is from Lacie U-Boot source. +# It defines 4 1Gb bank, but there is only 2 on the device ! +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width +# bit7-6: 00, Cs1size +# bit9-8: 00, Cs2width +# bit11-10: 00, Cs2size +# bit13-12: 00, Cs3width +# bit15-14: 00, Cs3size +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 00, ODT1 controlled by ODT Control register above +# bit31-4: zero, required + +DATA 0xFFD0141C 0x00000662 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 6, CL=6 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, This device does not support auto-precharge write recovery. Must be 0x3. +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2,6 10, DDR ODT control enabled, 150 ohm termination +# bit5-3: 000, required +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F177 # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 0 , MBUS Burst Chop enabled +# bit6-4: 111, required +# bit7 : 0 , Reserved Must be 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD0149C 0x0000E811 # CPU ODT Control +# bit3-0: 0001, internal ODT is asserted during read from DRAM bank 0 +# bit7-4: 0001, internal ODT is asserted during write from DRAM bank 0 +# bit9-8: 00, Internal ODT assertion/de-assertion is controlled by ODTRd/ODTWr fields +# bit11-10: 10, DQ_ODTSel. ODT select turned on ( 75 ohm ) +# bit13-12: 10, 75 ohm DDR Controller M_STARTBURST_IN I/O buffer ODT Select +# bit14: 1, DDR Controller M_STARTBURST_IN ODT Enable +# bit15: 1, DDR IO ODT Unit : Use ODT Block + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: 1's, required +# bit31-24: 0x0f, CPU CS Window0 Size + +DATA 0xFFD0150C 0x00000000 # bit 0: 0, Window1 disabled +DATA 0xFFD01514 0x00000000 # bit 0: 0, Window2 disabled +DATA 0xFFD0151C 0x00000000 # bit 0: 0, Window3 disabled + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 1e598cb..057d98a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -170,6 +170,7 @@ kmsuv31 arm arm926ejs km_arm keymile mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 +cloudbox arm arm926ejs cloudbox LaCie kirkwood lacie_kw:CLOUDBOX d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index e2b3b21..dc101d6 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -44,6 +44,8 @@ #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 #define CONFIG_IDENT_STRING " 2Big v2" +#elif defined(CONFIG_CLOUDBOX) +#define CONFIG_IDENT_STRING " CloudBox" #else #error "Unknown board" #endif @@ -70,9 +72,11 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_SF +#if !defined(CONFIG_CLOUDBOX) /* No I2C eeprom */ #define CONFIG_CMD_I2C +#endif #define CONFIG_CMD_IDE -#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */ +#if !defined(CONFIG_NETSPACE_MINI_V2) && !defined(CONFIG_CLOUDBOX) /* No USB ports on these devices */ #define CONFIG_CMD_USB #endif
@@ -115,6 +119,8 @@ #define CONFIG_SYS_PROMPT "d2v2> " #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_PROMPT "2big2> " +#elif defined(CONFIG_CLOUDBOX) +#define CONFIG_SYS_PROMPT "cb> " #else #define CONFIG_SYS_PROMPT "ns2> " #endif
Dear Frederic Leroy,
In message 1372178945-11528-2-git-send-email-fredo@starox.org you wrote:
From: Frédéric Leroy fredo@starox.org
The LaCie CloudBox device is a Kirkwood based nas :
- SoC: Marvell 88F6700 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- 1 push button
- 1 reset switch
- 1 SATA port
- 1 LED (bi-color, blue and red)
Signed-off-by: Frédéric Leroy fredo@starox.org
board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 104 ++++++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/lacie_kw.h | 8 +- 6 files changed, 361 insertions(+), 1 deletion(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
The (mandatory) entry to MAINTAINERS is missing.
Checkpatch says:
WARNING: please, no spaces at the start of a line #253: FILE: board/LaCie/cloudbox/cloudbox.c:82: + return 0;$
WARNING: line over 80 characters #525: FILE: include/configs/lacie_kw.h:79: +#if !defined(CONFIG_NETSPACE_MINI_V2) && !defined(CONFIG_CLOUDBOX) /* No USB ports on these devices */
Please clean these up.
index e2b3b21..dc101d6 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -44,6 +44,8 @@ #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 #define CONFIG_IDENT_STRING " 2Big v2" +#elif defined(CONFIG_CLOUDBOX) +#define CONFIG_IDENT_STRING " CloudBox"
Please keep such lists alphabetically sorted.
@@ -115,6 +119,8 @@ #define CONFIG_SYS_PROMPT "d2v2> " #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_PROMPT "2big2> " +#elif defined(CONFIG_CLOUDBOX) +#define CONFIG_SYS_PROMPT "cb> "
Same here again.
On the other hand, this is actually crap. We should use a common prompt for all these boards, eventually the standard "=> ".
Best regards,
Wolfgang Denk
This series adds support for the LaCie Cloudbox v2 device.
Changes in v2:
- sort unsorted #ifdef list in lacie_kw.h - add entry to MAINTAINERS - remove unused GPIO definitions - remove empty misc_init_r() - add Machine ID - Use #define values for ethernet phy init - checkpatch compliant
Frédéric Leroy (4): lacie_kw: sort #ifdef lists by CONFIG_ identifiers arm: add support for LaCie CloudBox LaCie/common: Fix cloudbox ethernet leds arm: add machine ID for CloudBox
MAINTAINERS | 4 + arch/arm/include/asm/mach-types.h | 14 ++++ board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 94 +++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ board/LaCie/common/common.c | 13 ++- boards.cfg | 1 + include/configs/lacie_kw.h | 44 ++++++---- 9 files changed, 401 insertions(+), 18 deletions(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
Signed-off-by: Frédéric Leroy fredo@starox.org --- include/configs/lacie_kw.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index e2b3b21..cac616a 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -21,29 +21,29 @@ /* * Machine number definition */ -#if defined(CONFIG_INETSPACE_V2) +#if defined(CONFIG_D2NET_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 +#define CONFIG_IDENT_STRING " D2 v2" +#elif defined(CONFIG_INETSPACE_V2) #define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 #define CONFIG_IDENT_STRING " IS v2" -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#define CONFIG_IDENT_STRING " NS v2" +#elif defined(CONFIG_NET2BIG_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 +#define CONFIG_IDENT_STRING " 2Big v2" #elif defined(CONFIG_NETSPACE_LITE_V2) #define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 #define CONFIG_IDENT_STRING " NS v2 Lite" +#elif defined(CONFIG_NETSPACE_MAX_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +#define CONFIG_IDENT_STRING " NS Max v2" #elif defined(CONFIG_NETSPACE_MINI_V2) #define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 #define CONFIG_IDENT_STRING " NS v2 Mini" -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#define CONFIG_IDENT_STRING " NS Max v2" -#elif defined(CONFIG_D2NET_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 -#define CONFIG_IDENT_STRING " D2 v2" -#elif defined(CONFIG_NET2BIG_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 -#define CONFIG_IDENT_STRING " 2Big v2" +#elif defined(CONFIG_NETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +#define CONFIG_IDENT_STRING " NS v2" #else #error "Unknown board" #endif
On Sun, Jun 30, 2013 at 12:12:26PM +0200, Frédéric Leroy wrote:
Signed-off-by: Frédéric Leroy fredo@starox.org
include/configs/lacie_kw.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)
Acked-by: Simon Guinot simon.guinot@sequanux.org
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index e2b3b21..cac616a 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -21,29 +21,29 @@ /*
- Machine number definition
*/ -#if defined(CONFIG_INETSPACE_V2) +#if defined(CONFIG_D2NET_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 +#define CONFIG_IDENT_STRING " D2 v2" +#elif defined(CONFIG_INETSPACE_V2) #define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 #define CONFIG_IDENT_STRING " IS v2" -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#define CONFIG_IDENT_STRING " NS v2" +#elif defined(CONFIG_NET2BIG_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 +#define CONFIG_IDENT_STRING " 2Big v2" #elif defined(CONFIG_NETSPACE_LITE_V2) #define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 #define CONFIG_IDENT_STRING " NS v2 Lite" +#elif defined(CONFIG_NETSPACE_MAX_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +#define CONFIG_IDENT_STRING " NS Max v2" #elif defined(CONFIG_NETSPACE_MINI_V2) #define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 #define CONFIG_IDENT_STRING " NS v2 Mini" -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#define CONFIG_IDENT_STRING " NS Max v2" -#elif defined(CONFIG_D2NET_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 -#define CONFIG_IDENT_STRING " D2 v2" -#elif defined(CONFIG_NET2BIG_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 -#define CONFIG_IDENT_STRING " 2Big v2" +#elif defined(CONFIG_NETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +#define CONFIG_IDENT_STRING " NS v2" #else #error "Unknown board"
#endif
1.8.1.2
The LaCie CloudBox device is a Kirkwood based nas :
- SoC: Marvell 88F6702 1000Mhz - SDRAM memory: 256MB DDR2 400Mhz - Gigabit ethernet: PHY Marvell 88E1318 - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - 1 push button - 1 reset switch - 1 SATA port - 1 LED (bi-color, blue and red)
Signed-off-by: Frédéric Leroy fredo@starox.org ---
Changes in v2:
- sort unsorted #ifdef list in lacie_kw.h - add entry to MAINTAINERS - remove unused GPIO definitions - remove empty misc_init_r() - add Machine ID - Use #define values for ethernet phy init - checkpatch compliant
MAINTAINERS | 4 + board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 89 ++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/lacie_kw.h | 14 +++- 7 files changed, 354 insertions(+), 3 deletions(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 3e70b03..9bf561d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -770,6 +770,10 @@ Sergey Lapin slapin@ossfans.org
afeb9260 ARM926EJS (AT91SAM9260 SoC)
+Frederic Leroy fredo@starox.org + + cloudbox ARM926EJS (Kirkwood SoC) + Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC) diff --git a/board/LaCie/cloudbox/Makefile b/board/LaCie/cloudbox/Makefile new file mode 100644 index 0000000..d656951 --- /dev/null +++ b/board/LaCie/cloudbox/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c new file mode 100644 index 0000000..e5ee5a3 --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2013 Frederic Leroy fredo@starox.org + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "cloudbox.h" +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(CLOUDBOX_OE_VAL_LOW, CLOUDBOX_OE_VAL_HIGH, + CLOUDBOX_OE_LOW, CLOUDBOX_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_GPIO, /* hard disk power */ + MPP6_SYSRST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP14_GPIO, /* LED red control */ + MPP15_SATA0_ACTn, /* LED blue control */ + MPP16_GPIO, /* power push buton */ + MPP17_GPIO, /* board power off */ + MPP20_GPIO, /* Ethernet PHY interrupt (WoL) */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Nothing to do with fdt */ + return 0; +} + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1318_init("egiga0", 0); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO button status */ +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return kw_gpio_get_value(CLOUDBOX_GPIO_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_button, + "Return GPIO button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/cloudbox/cloudbox.h b/board/LaCie/cloudbox/cloudbox.h new file mode 100644 index 0000000..fb8af83 --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 Frederic Leroy fredo@starox.org + * + * Based on LaCie u-boot sources + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CLOUDBOX_H +#define CLOUDBOX_H + +/* GPIO configuration */ +#define CLOUDBOX_OE_LOW 0xF0310000 +#define CLOUDBOX_OE_HIGH 0x00000001 +#define CLOUDBOX_OE_VAL_LOW 0x00000010 +#define CLOUDBOX_OE_VAL_HIGH 0x00000000 + +#define CLOUDBOX_GPIO_BUTTON 16 + +#endif /* CLOUDBOX_H */ diff --git a/board/LaCie/cloudbox/kwbimage.cfg b/board/LaCie/cloudbox/kwbimage.cfg new file mode 100644 index 0000000..a6a8ff9 --- /dev/null +++ b/board/LaCie/cloudbox/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Dram configuration based on Lacie u-boot sources +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +#Dram initalization for DDR2 256MB, 400MHz, 1CS +DATA 0xFFD01400 0x43010C30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38743000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 7= 5.5 cycles: Recommended for CL 6. + +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22135551 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000032 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000C # DDR Address Control +# This value is from Lacie U-Boot source. +# It defines 4 1Gb bank, but there is only 2 on the device ! +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width +# bit7-6: 00, Cs1size +# bit9-8: 00, Cs2width +# bit11-10: 00, Cs2size +# bit13-12: 00, Cs3width +# bit15-14: 00, Cs3size +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 00, ODT1 controlled by ODT Control register above +# bit31-4: zero, required + +DATA 0xFFD0141C 0x00000662 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 6, CL=6 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, This device does not support auto-precharge write recovery. Must be 0x3. +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2,6 10, DDR ODT control enabled, 150 ohm termination +# bit5-3: 000, required +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F177 # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 0 , MBUS Burst Chop enabled +# bit6-4: 111, required +# bit7 : 0 , Reserved Must be 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD0149C 0x0000E811 # CPU ODT Control +# bit3-0: 0001, internal ODT is asserted during read from DRAM bank 0 +# bit7-4: 0001, internal ODT is asserted during write from DRAM bank 0 +# bit9-8: 00, Internal ODT assertion/de-assertion is controlled by ODTRd/ODTWr fields +# bit11-10: 10, DQ_ODTSel. ODT select turned on ( 75 ohm ) +# bit13-12: 10, 75 ohm DDR Controller M_STARTBURST_IN I/O buffer ODT Select +# bit14: 1, DDR Controller M_STARTBURST_IN ODT Enable +# bit15: 1, DDR IO ODT Unit : Use ODT Block + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: 1's, required +# bit31-24: 0x0f, CPU CS Window0 Size + +DATA 0xFFD0150C 0x00000000 # bit 0: 0, Window1 disabled +DATA 0xFFD01514 0x00000000 # bit 0: 0, Window2 disabled +DATA 0xFFD0151C 0x00000000 # bit 0: 0, Window3 disabled + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 1458289..11d7718 100644 --- a/boards.cfg +++ b/boards.cfg @@ -170,6 +170,7 @@ kmsuv31 arm arm926ejs km_arm keymile mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 +cloudbox arm arm926ejs cloudbox LaCie kirkwood lacie_kw:CLOUDBOX d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index cac616a..fe27bbe 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -21,7 +21,9 @@ /* * Machine number definition */ -#if defined(CONFIG_D2NET_V2) +#if defined(CONFIG_CLOUDBOX) +#define CONFIG_IDENT_STRING " CloudBox" +#elif defined(CONFIG_D2NET_V2) #define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 #define CONFIG_IDENT_STRING " D2 v2" #elif defined(CONFIG_INETSPACE_V2) @@ -70,9 +72,11 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_SF +#if !defined(CONFIG_CLOUDBOX) #define CONFIG_CMD_I2C +#endif #define CONFIG_CMD_IDE -#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */ +#if !defined(CONFIG_NETSPACE_MINI_V2) && !defined(CONFIG_CLOUDBOX) #define CONFIG_CMD_USB #endif
@@ -111,7 +115,9 @@ #define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_IDE_MAXDEVICE 1 -#if defined(CONFIG_D2NET_V2) +#if defined(CONFIG_CLOUDBOX) +#define CONFIG_SYS_PROMPT "cb> " +#elif defined(CONFIG_D2NET_V2) #define CONFIG_SYS_PROMPT "d2v2> " #elif defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_PROMPT "2big2> " @@ -122,7 +128,9 @@ /* * Enable platform initialisation via misc_init_r() function */ +#if !defined(CONFIG_CLOUDBOX) #define CONFIG_MISC_INIT_R +#endif
/* * Ethernet Driver configuration
The cloudbox device have a different ethernet phy setup than other ns2 devices. We get initialization value from the GPL LaCie source
Signed-off-by: Frédéric Leroy fredo@starox.org --- board/LaCie/common/common.c | 13 ++++++++++--- include/configs/lacie_kw.h | 5 +++++ 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index a62bf9f..85480e7 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -21,6 +21,12 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+#if !defined(MII_MARVELL_LED_REG) +# define MII_MARVELL_LED_REG 16 +# define MII_MARVELL_LED_MASK 0xf0 +# define MII_MARVELL_LED_VALUE 0x0f +#endif + void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; @@ -53,9 +59,10 @@ void mv_phy_88e1318_init(const char *name, u16 phyaddr) * Set control mode 4 for LED[0]. */ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); - miiphy_read(name, phyaddr, 16, ®); - reg |= 0xf; - miiphy_write(name, phyaddr, 16, reg); + miiphy_read(name, phyaddr, MII_MARVELL_LED_REG, ®); + reg &= MII_MARVELL_LED_MASK; + reg |= MII_MARVELL_LED_VALUE; + miiphy_write(name, phyaddr, MII_MARVELL_LED_REG, reg);
/* * Enable RGMII delay on Tx and Rx for CPU port diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index fe27bbe..02e0882 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -138,6 +138,11 @@ #ifdef CONFIG_CMD_NET #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_NETCONSOLE +#if defined(CONFIG_CLOUDBOX) +# define MII_MARVELL_LED_REG 17 +# define MII_MARVELL_LED_MASK 0xffc0 +# define MII_MARVELL_LED_VALUE 0x15 +#endif #endif
/*
On Sun, Jun 30, 2013 at 12:12:28PM +0200, Frédéric Leroy wrote:
The cloudbox device have a different ethernet phy setup than other ns2 devices. We get initialization value from the GPL LaCie source
Signed-off-by: Frédéric Leroy fredo@starox.org
board/LaCie/common/common.c | 13 ++++++++++--- include/configs/lacie_kw.h | 5 +++++ 2 files changed, 15 insertions(+), 3 deletions(-)
Acked-by: Simon Guinot simon.guinot@sequanux.org
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index a62bf9f..85480e7 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -21,6 +21,12 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+#if !defined(MII_MARVELL_LED_REG) +# define MII_MARVELL_LED_REG 16 +# define MII_MARVELL_LED_MASK 0xf0 +# define MII_MARVELL_LED_VALUE 0x0f +#endif
void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; @@ -53,9 +59,10 @@ void mv_phy_88e1318_init(const char *name, u16 phyaddr) * Set control mode 4 for LED[0]. */ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
- miiphy_read(name, phyaddr, 16, ®);
- reg |= 0xf;
- miiphy_write(name, phyaddr, 16, reg);
miiphy_read(name, phyaddr, MII_MARVELL_LED_REG, ®);
reg &= MII_MARVELL_LED_MASK;
reg |= MII_MARVELL_LED_VALUE;
miiphy_write(name, phyaddr, MII_MARVELL_LED_REG, reg);
/*
- Enable RGMII delay on Tx and Rx for CPU port
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index fe27bbe..02e0882 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -138,6 +138,11 @@ #ifdef CONFIG_CMD_NET #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_NETCONSOLE +#if defined(CONFIG_CLOUDBOX) +# define MII_MARVELL_LED_REG 17 +# define MII_MARVELL_LED_MASK 0xffc0 +# define MII_MARVELL_LED_VALUE 0x15 +#endif #endif
/*
1.8.1.2
Hi, experts: I tried to turn off gcc optimazition by changing config.mk file: OPTFLAGS= -O0 #-fomit-frame-pointer
But failed to compile u-boot, it tipped: ...... /home/lion/Origen0921/arm-2010.09/bin/arm-none-eabi-ld: arch/arm/cpu/armv7/libarmv7.o: relocation R_ARM_MOVW_ABS_NC against `a local symbol' can not be used when making a shared object; recompile with -fPIC arch/arm/cpu/armv7/libarmv7.o: could not read symbols: Bad value make[1]: *** [u-boot] Error 1 make[1]: Leaving directory `/home/lion/DebugLinux/uboot-0627/u-boot' make: *** [smdkc100] Error 2
Best wishes,
Dear TigerLiu@viatech.com.cn,
In message FE7ADED5C2218B4786C09CD97DC4C49F9403F2@exchbj02.viatech.com.bj you wrote:
I tried to turn off gcc optimazition by changing config.mk file: OPTFLAGS= -O0 #-fomit-frame-pointer
But failed to compile u-boot, it tipped:
Don't do it, then.
Q: why would you want to switch off optimization? That's almost always a bad idea...
Best regards,
Wolfgang Denk
Hi, Denk: During debug u-boot with JTAG tools, maybe turning off optimizations was recommended.
Best wishes, -----邮件原件----- 发件人: Wolfgang Denk [mailto:wd@denx.de] 发送时间: 2013年7月1日 18:03 收件人: Tiger Liu 抄送: u-boot@lists.denx.de 主题: Re: [U-Boot] compiled failed when turned off gcc optimazition
Dear TigerLiu@viatech.com.cn,
In message FE7ADED5C2218B4786C09CD97DC4C49F9403F2@exchbj02.viatech.com.bj you wrote:
I tried to turn off gcc optimazition by changing config.mk file: OPTFLAGS= -O0 #-fomit-frame-pointer
But failed to compile u-boot, it tipped:
Don't do it, then.
Q: why would you want to switch off optimization? That's almost always a bad idea...
Best regards,
Wolfgang Denk
Dear TigerLiu@viatech.com.cn,
please do not top post / full quote.
In message FE7ADED5C2218B4786C09CD97DC4C49F9403F9@exchbj02.viatech.com.bj you wrote:
During debug u-boot with JTAG tools, maybe turning off optimizations was recommended.
Many people recommend many things. Even strange or non-working or incorrect or dangerous ones.
Best regards,
Wolfgang Denk
On 07/01/2013 04:37 AM, Wolfgang Denk wrote:
Dear TigerLiu@viatech.com.cn,
please do not top post / full quote.
In message FE7ADED5C2218B4786C09CD97DC4C49F9403F9@exchbj02.viatech.com.bj you wrote:
During debug u-boot with JTAG tools, maybe turning off optimizations was recommended.
Many people recommend many things. Even strange or non-working or incorrect or dangerous ones.
A while back I tried this for the Linux kernel, with similiar results. I just let it go without investigating further, guessing that maybe some tricks with compiler directives were incompatible with turning off optimization.
But there's a good motivation for wanting to turn off optimization. Single-stepping with a debugger at the C source level is almost useless. I've since gotten better at single-stepping at the assembly level while using the mixed c and assembly view of gdb.
Mike
Dear Mike Dunn,
In message 51D1C455.9010801@newsguy.com you wrote:
But there's a good motivation for wanting to turn off optimization.
I disagree here. If you are hunting down a problem, you want to be as close at the original code as possible. Disabling optimization is such a dramatic change to the generated code that you actually debug a different program.
Single-stepping with a debugger at the C source level is almost useless. I've since gotten better at single-stepping at the assembly level while using the mixed c and assembly view of gdb.
Hm... Did you read up the documentation, say [1], and try out these recommendations?
[1] http://www.denx.de/wiki/view/DULG/DebuggingTricks
Best regards,
Wolfgang Denk
On 07/01/2013 12:51 PM, Wolfgang Denk wrote:
Dear Mike Dunn,
In message 51D1C455.9010801@newsguy.com you wrote:
But there's a good motivation for wanting to turn off optimization.
I disagree here. If you are hunting down a problem, you want to be as close at the original code as possible. Disabling optimization is such a dramatic change to the generated code that you actually debug a different program.
I guess it depends on what problem being debugged... I think your point is valid for things like tracking down race conditions or misbehaving hardware. But for more mundane problems like logical errors in the code, optimizations get in the way. It would be nice to be able to experiment with optimizations off. Just knowing that a particular problem still exists when unoptimized code is run will provide some clues.
Single-stepping with a debugger at the C source level is almost useless. I've since gotten better at single-stepping at the assembly level while using the mixed c and assembly view of gdb.
Hm... Did you read up the documentation, say [1], and try out these recommendations?
No, but I will. Many thanks! Mike
Hi Mike,
On Wed, Jul 3, 2013 at 5:40 AM, Mike Dunn mikedunn@newsguy.com wrote:
On 07/01/2013 12:51 PM, Wolfgang Denk wrote:
Dear Mike Dunn,
In message 51D1C455.9010801@newsguy.com you wrote:
But there's a good motivation for wanting to turn off optimization.
I disagree here. If you are hunting down a problem, you want to be as close at the original code as possible. Disabling optimization is such a dramatic change to the generated code that you actually debug a different program.
I guess it depends on what problem being debugged... I think your point is valid for things like tracking down race conditions or misbehaving hardware. But for more mundane problems like logical errors in the code, optimizations get in the way. It would be nice to be able to experiment with optimizations off. Just knowing that a particular problem still exists when unoptimized code is run will provide some clues.
Do be honest, I have never used an online debugger
I have always found that a combination of hardware LEDs and printf's has been more than sufficient, particularly for mundane issues.
I'll freely admit that an online debugger might been faster for me, but I just wanted to point out that there is more than one way to skin a cat.
I also believe that the more onerous the debugging tool is (and it doesn't get more so than using the hardware LEDs) the more attention you pay to the code rather than the output ;)
Regards,
Graeme
Hi, experts:
Would any expert fix this question?
It seems related MOVW instruction's usuage when turning off gcc optimazition.
If i just turned on "-O1" or "-O2", still failed to compile uboot code.
Best wishes,
Hi TigerLiu@viatech.com.cn,
On Fri, 5 Jul 2013 18:31:50 +0800, TigerLiu@viatech.com.cn wrote:
Hi, experts:
Would any expert fix this question?
It seems related MOVW instruction's usuage when turning off gcc optimazition.
If i just turned on "-O1" or "-O2", still failed to compile uboot code.
I have seen the issue arise, and looked it up with the help of Jeroen Hofstee (Cc:). It is somehow related to the fact that on ARM, U-Boot (especially the DM) relies on ARM ELF relocation records all being of the R_ARM_RELATIVE type, while for -O{0,1,2} the compiler generates (some) MOVW-related relocation record types.
I have local branches related to this. I need to go through them and will post them but not for 2013.07 as these are not fixes, and there is no bug per se since U-Boot is supposed to build with -Os, not -O{0,1,2}.
Best wishes,
Amicalement,
CloudBox device is device tree compliant, but older LaCie kernel uses machine ID method to boot.
Signed-off-by: Frédéric Leroy fredo@starox.org --- arch/arm/include/asm/mach-types.h | 14 ++++++++++++++ board/LaCie/cloudbox/cloudbox.c | 7 ++++++- include/configs/lacie_kw.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..071bd11 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_CLOUDBOX 4170
#ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14235,6 +14236,19 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif
+#ifdef CONFIG_MACH_CLOUDBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLOUDBOX +# endif +# define machine_cloudbox() (machine_arch_type == MACH_TYPE_CLOUDBOX) +#else +# define machine_cloudbox() (0) +#endif + + /* * These have not yet been registered */ diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c index e5ee5a3..51b1f96 100644 --- a/board/LaCie/cloudbox/cloudbox.c +++ b/board/LaCie/cloudbox/cloudbox.c @@ -64,7 +64,12 @@ int board_early_init_f(void)
int board_init(void) { - /* Nothing to do with fdt */ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + return 0; }
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 02e0882..b305bf6 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -22,6 +22,7 @@ * Machine number definition */ #if defined(CONFIG_CLOUDBOX) +#define CONFIG_MACH_TYPE MACH_TYPE_CLOUDBOX #define CONFIG_IDENT_STRING " CloudBox" #elif defined(CONFIG_D2NET_V2) #define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
On Sun, Jun 30, 2013 at 12:12:29PM +0200, Frédéric Leroy wrote:
CloudBox device is device tree compliant, but older LaCie kernel uses machine ID method to boot.
Signed-off-by: Frédéric Leroy fredo@starox.org
arch/arm/include/asm/mach-types.h | 14 ++++++++++++++ board/LaCie/cloudbox/cloudbox.c | 7 ++++++- include/configs/lacie_kw.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..071bd11 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_CLOUDBOX 4170
#ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14235,6 +14236,19 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif
+#ifdef CONFIG_MACH_CLOUDBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLOUDBOX +# endif +# define machine_cloudbox() (machine_arch_type == MACH_TYPE_CLOUDBOX) +#else +# define machine_cloudbox() (0) +#endif
Hi Fred,
I think you can't update this file directly. Pulling the Linux mach-types file is the ARM maintainer job.
Note that for the CloudBox board, the mach-types entry has been removed because not needed by Linux. The Linux mainline support is only based on DT. I had the same issue with the ns2 lite and mini. At the time, I have been told to include the machine ID in the board header: http://marc.info/?l=u-boot&m=134694402011372&w=2
Looks in configs/lacie_kw.h and grep for "missing in mach-types.h".
Besides, I don't understand why do you need a separate patch to add the legacy boot support.
Simon
/*
- These have not yet been registered
*/ diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c index e5ee5a3..51b1f96 100644 --- a/board/LaCie/cloudbox/cloudbox.c +++ b/board/LaCie/cloudbox/cloudbox.c @@ -64,7 +64,12 @@ int board_early_init_f(void)
int board_init(void) {
- /* Nothing to do with fdt */
- /* Machine number */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- /* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
- return 0;
}
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 02e0882..b305bf6 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -22,6 +22,7 @@
- Machine number definition
*/ #if defined(CONFIG_CLOUDBOX) +#define CONFIG_MACH_TYPE MACH_TYPE_CLOUDBOX #define CONFIG_IDENT_STRING " CloudBox" #elif defined(CONFIG_D2NET_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
1.8.1.2
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
Le 01/07/2013 00:53, Simon Guinot a écrit :
On Sun, Jun 30, 2013 at 12:12:29PM +0200, Frédéric Leroy wrote:
CloudBox device is device tree compliant, but older LaCie kernel uses machine ID method to boot.
Signed-off-by: Frédéric Leroy fredo@starox.org [...] +# define machine_cloudbox() (0) +#endif
Hi Fred,
I think you can't update this file directly. Pulling the Linux mach-types file is the ARM maintainer job.
Note that for the CloudBox board, the mach-types entry has been removed because not needed by Linux. The Linux mainline support is only based on DT. I had the same issue with the ns2 lite and mini. At the time, I have been told to include the machine ID in the board header: http://marc.info/?l=u-boot&m=134694402011372&w=2
Looks in configs/lacie_kw.h and grep for "missing in mach-types.h".
There is a doublon for netspace_lite_v2 : $ git grep MACH_TYPE_NETSPACE_ arch/arm/include/asm/mach-types.h:#define MACH_TYPE_NETSPACE_LITE_V2 2983 [...] include/configs/lacie_kw.h:#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
Besides, I don't understand why do you need a separate patch to add the legacy boot support.
Partly because I added CloudBox without it and it seems logical to add it after, partly because I was not sure of the change of mach_types.h :)
I am not at ease with sending patch to the ML and with patchwork. How should I send the fix ? A new v3 patch including all but " lacie_kw: sort #ifdef lists by CONFIG_ identifiers" and "LaCie/common: Fix cloudbox ethernet leds", or just a v3 of "arm: add machine ID for CloudBox" ?
- -- Frédéric
On Mon, Jul 01, 2013 at 11:30:01AM +0200, Frédéric Leroy wrote:
Le 01/07/2013 00:53, Simon Guinot a écrit :
On Sun, Jun 30, 2013 at 12:12:29PM +0200, Frédéric Leroy wrote:
CloudBox device is device tree compliant, but older LaCie kernel uses machine ID method to boot.
Signed-off-by: Frédéric Leroy fredo@starox.org [...] +# define machine_cloudbox() (0) +#endif
Hi Fred,
I think you can't update this file directly. Pulling the Linux mach-types file is the ARM maintainer job.
Note that for the CloudBox board, the mach-types entry has been removed because not needed by Linux. The Linux mainline support is only based on DT. I had the same issue with the ns2 lite and mini. At the time, I have been told to include the machine ID in the board header: http://marc.info/?l=u-boot&m=134694402011372&w=2
Looks in configs/lacie_kw.h and grep for "missing in mach-types.h".
There is a doublon for netspace_lite_v2 : $ git grep MACH_TYPE_NETSPACE_ arch/arm/include/asm/mach-types.h:#define MACH_TYPE_NETSPACE_LITE_V2 2983
This one will probably disappear soon because the Linux support for this board is only based on DT...
[...] include/configs/lacie_kw.h:#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
Besides, I don't understand why do you need a separate patch to add the legacy boot support.
Partly because I added CloudBox without it and it seems logical to add it after, partly because I was not sure of the change of mach_types.h :)
I am not at ease with sending patch to the ML and with patchwork. How should I send the fix ? A new v3 patch including all but " lacie_kw: sort #ifdef lists by CONFIG_ identifiers" and "LaCie/common: Fix cloudbox ethernet leds", or just a v3 of "arm: add machine ID for CloudBox" ?
I think that you must resend the whole patch series even if you keep some patches unchanged.
Regards,
Simon
On Tue, Jun 25, 2013 at 06:49:04PM +0200, Frederic Leroy wrote:
From: Frédéric Leroy fredo@starox.org
Hi Frédéric,
The LaCie CloudBox device is a Kirkwood based nas :
- SoC: Marvell 88F6700 1000Mhz
88F6702
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- 1 push button
- 1 reset switch
- 1 SATA port
- 1 LED (bi-color, blue and red)
Signed-off-by: Frédéric Leroy fredo@starox.org
board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 104 ++++++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/lacie_kw.h | 8 +- 6 files changed, 361 insertions(+), 1 deletion(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
diff --git a/board/LaCie/cloudbox/Makefile b/board/LaCie/cloudbox/Makefile new file mode 100644 index 0000000..d656951 --- /dev/null +++ b/board/LaCie/cloudbox/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#
+include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o ../common/common.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+######################################################################### diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c new file mode 100644 index 0000000..6604a3c --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.c @@ -0,0 +1,104 @@ +/*
- Copyright (C) 2013 Frederic Leroy fredo@starox.org
- Based on Kirkwood support:
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- */
+#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h>
+#include "cloudbox.h" +#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- /* Gpio configuration */
- kw_config_gpio(CLOUDBOX_OE_VAL_LOW, CLOUDBOX_OE_VAL_HIGH,
CLOUDBOX_OE_LOW, CLOUDBOX_OE_HIGH);- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,MPP1_SPI_MOSI,MPP2_SPI_SCK,MPP3_SPI_MISO,MPP4_GPIO, /* hard disk power */MPP5_GPO,MPP6_SYSRST_OUTn,MPP7_GPO,MPP8_TW_SDA,MPP9_TW_SCK,MPP10_UART0_TXD,MPP11_UART0_RXD,MPP12_GPO,MPP14_GPIO, /* LED red control */MPP15_SATA0_ACTn, /* LED blue control */MPP16_GPIO, /* power push buton */MPP17_GPIO, /* board power off */MPP20_GPIO, /* Ethernet PHY interrupt (WoL) */MPP28_GPIO, /* board revision (LSB) */MPP29_GPIO, /* board revision */MPP30_GPIO, /* board revision */MPP31_GPIO, /* board revision */MPP32_GPIO, /* board revision (MSB) */0
The MPPs 5, 7 and 12 are not used. Please drop their configuration.
Moreover, AFAIK, the board revision GPIOs are not used. I am not even sure they hold a coherent value.
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
+}
+int board_init(void) +{
- /* Nothing to do with fdt */
- return 0;
In addition, can we also set the machine ID ? Without breaking the DT boot ? It would be nice to support the two Linux booting methods: DT and legacy (machine ID, ATAGs). Note that the Linux kernel provided by the LaCie stock firmware is not DT compliant.
+}
+#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{
return 0;+} +#endif /* CONFIG_MISC_INIT_R */
Maybe you could simply undef CONFIG_MISC_INIT_R ?
Except the points above, the whole patch looks good to me.
Thanks,
Simon
On Tue, Jun 25, 2013 at 10:50:56PM +0200, Simon Guinot wrote:
On Tue, Jun 25, 2013 at 06:49:04PM +0200, Frederic Leroy wrote:
From: Frédéric Leroy fredo@starox.org
Hi Frédéric,
The LaCie CloudBox device is a Kirkwood based nas :
- SoC: Marvell 88F6700 1000Mhz
88F6702
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- 1 push button
- 1 reset switch
- 1 SATA port
- 1 LED (bi-color, blue and red)
Signed-off-by: Frédéric Leroy fredo@starox.org
board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 104 ++++++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/lacie_kw.h | 8 +- 6 files changed, 361 insertions(+), 1 deletion(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg
diff --git a/board/LaCie/cloudbox/Makefile b/board/LaCie/cloudbox/Makefile new file mode 100644 index 0000000..d656951 --- /dev/null +++ b/board/LaCie/cloudbox/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2013 Frederic Leroy fredo@starox.org +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#
+include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o ../common/common.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+######################################################################### diff --git a/board/LaCie/cloudbox/cloudbox.c b/board/LaCie/cloudbox/cloudbox.c new file mode 100644 index 0000000..6604a3c --- /dev/null +++ b/board/LaCie/cloudbox/cloudbox.c @@ -0,0 +1,104 @@ +/*
- Copyright (C) 2013 Frederic Leroy fredo@starox.org
- Based on Kirkwood support:
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- */
+#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h>
+#include "cloudbox.h" +#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- /* Gpio configuration */
- kw_config_gpio(CLOUDBOX_OE_VAL_LOW, CLOUDBOX_OE_VAL_HIGH,
CLOUDBOX_OE_LOW, CLOUDBOX_OE_HIGH);- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,MPP1_SPI_MOSI,MPP2_SPI_SCK,MPP3_SPI_MISO,MPP4_GPIO, /* hard disk power */MPP5_GPO,MPP6_SYSRST_OUTn,MPP7_GPO,MPP8_TW_SDA,MPP9_TW_SCK,MPP10_UART0_TXD,MPP11_UART0_RXD,MPP12_GPO,MPP14_GPIO, /* LED red control */MPP15_SATA0_ACTn, /* LED blue control */MPP16_GPIO, /* power push buton */MPP17_GPIO, /* board power off */MPP20_GPIO, /* Ethernet PHY interrupt (WoL) */MPP28_GPIO, /* board revision (LSB) */MPP29_GPIO, /* board revision */MPP30_GPIO, /* board revision */MPP31_GPIO, /* board revision */MPP32_GPIO, /* board revision (MSB) */0The MPPs 5, 7 and 12 are not used. Please drop their configuration.
Moreover, AFAIK, the board revision GPIOs are not used. I am not even sure they hold a coherent value.
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
+}
+int board_init(void) +{
- /* Nothing to do with fdt */
- return 0;
In addition, can we also set the machine ID ? Without breaking the DT boot ? It would be nice to support the two Linux booting methods: DT and legacy (machine ID, ATAGs). Note that the Linux kernel provided by the LaCie stock firmware is not DT compliant.
+}
+#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{
return 0;+} +#endif /* CONFIG_MISC_INIT_R */
Maybe you could simply undef CONFIG_MISC_INIT_R ?
Except the points above, the whole patch looks good to me.
In addition, you should also fix the checkpatch warnings.
Simon
From: Frédéric Leroy fredo@starox.org
The cloudbox device have a different ethernet phy setup than other ns2 devices. We get initialization value from the GPL LaCie source
Signed-off-by: Frédéric Leroy fredo@starox.org --- board/LaCie/common/common.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index a62bf9f..d828685 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -52,10 +52,18 @@ void mv_phy_88e1318_init(const char *name, u16 phyaddr) /* * Set control mode 4 for LED[0]. */ + #ifndef CONFIG_CLOUDBOX miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); miiphy_read(name, phyaddr, 16, ®); reg |= 0xf; miiphy_write(name, phyaddr, 16, reg); + #else + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); + miiphy_read(name, phyaddr, 17, ®); + reg &= ~0x3f; + reg |= 0x15; + miiphy_write(name, phyaddr, 17, reg); + #endif
/* * Enable RGMII delay on Tx and Rx for CPU port
Dear Frederic Leroy,
In message 1372178945-11528-3-git-send-email-fredo@starox.org you wrote:
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index a62bf9f..d828685 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c
...
- #ifndef CONFIG_CLOUDBOX
...
- #else
...
- #endif
Preprocessor statements must start in column 1; please fix.
Also, can we not avoid the #ifdef alltogether by providing a #define for the register number to read? This could then be done in the board config file.
Best regards,
Wolfgang Denk
On Tue, Jun 25, 2013 at 06:49:05PM +0200, Frederic Leroy wrote:
From: Frédéric Leroy fredo@starox.org
The cloudbox device have a different ethernet phy setup than other ns2 devices. We get initialization value from the GPL LaCie source
Signed-off-by: Frédéric Leroy fredo@starox.org
board/LaCie/common/common.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index a62bf9f..d828685 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -52,10 +52,18 @@ void mv_phy_88e1318_init(const char *name, u16 phyaddr) /* * Set control mode 4 for LED[0]. */
- #ifndef CONFIG_CLOUDBOX miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); miiphy_read(name, phyaddr, 16, ®); reg |= 0xf; miiphy_write(name, phyaddr, 16, reg);
- #else
- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
- miiphy_read(name, phyaddr, 17, ®);
- reg &= ~0x3f;
- reg |= 0x15;
- miiphy_write(name, phyaddr, 17, reg);
- #endif
This doesn't look very common but I can't figure out a more elegant way.
Acked-by: Simon Guinot simon.guinot@sequanux.org
participants (8)
-
Albert ARIBAUD -
Frederic Leroy -
Frédéric Leroy
-
Graeme Russ -
Mike Dunn -
Simon Guinot -
TigerLiu＠viatech.com.cn -
Wolfgang Denk