
Hi Sean,
+ u-boot ML
Sean Nyekjaer sean@geanix.com wrote on Wed, 14 Apr 2021 15:13:39 +0200:
Hi,
I have two boards with a iMX6ULL SoC one attached to a Micron NAND flash (MT29F4G08ABAFAWP) and one a Toshiba (TC58BVG2S0HTAI0).
After updating the boards from u-boot 2018.07 -> 2020.01, the Micron fitted boards is having ECC problems(in u-boot). U-boot 2018.07 selects ecc_strength to 18. U-boot 2020.01 selects ecc_strength to 8, but if I hardcode u-boot to run the mxs_nand_legacy_calc_ecc_layout() it selects 18 bits.
The Toshiba boards always selects 8 bit ecc_strength so they have no issues.
The kernel driver (gpmi-nand.c) seems to also use the legacy method (Resulting 18 bits in ecc strength for the Micron NAND). In common_nfc_set_geometry(): Both chip->ecc.strength and chip->ecc.size are 0.
I would expect ecc.strength to be set to 8, earlier but cannot find the spot where it should be set. Is the gpmi-nand driver missing a call to nand_ecc_choose_conf()? Maybe we need a legacy option for the kernel like u-boot.
We have +10K boards deployed so it's not so easy to switch from 18 -> 8 bits. I can explicit fix this in U-boot by forcing the legacy mode via a dt flag, but the gut feeling says this will come back to haunt us :)
/Sean
I honestly don't know about such issue on U-Boot side, maybe you can try to be more specific on what commit broke the logic for you as there are not so many of them between the two versions:
$ git l v2018.07..v2020.01 -- drivers/mtd/nand/raw/mxs_nand.c 1eb69ae4985 common: Move ARM cache operations out of common.h 9ab5f221a5e nand: mxs_nand: add API for switching different BCH layouts 1d43e24b946 i.MX6: nand: add nandbcb command for imx 1001502545f CONFIG_SPL_SYS_[DI]CACHE_OFF: add 04568bd0b6d MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL 5645df9e00a MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static 5ae585ba3a8 MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC a430fa06a4a mtd: move NAND files into a raw/ subdirectory
Good luck with your debugging, Miquèl

On 19/04/2021 09.32, Miquel Raynal wrote:
Hi Sean,
- u-boot ML
Sean Nyekjaer sean@geanix.com wrote on Wed, 14 Apr 2021 15:13:39 +0200:
Hi,
I have two boards with a iMX6ULL SoC one attached to a Micron NAND flash (MT29F4G08ABAFAWP) and one a Toshiba (TC58BVG2S0HTAI0).
After updating the boards from u-boot 2018.07 -> 2020.01, the Micron fitted boards is having ECC problems(in u-boot). U-boot 2018.07 selects ecc_strength to 18. U-boot 2020.01 selects ecc_strength to 8, but if I hardcode u-boot to run the mxs_nand_legacy_calc_ecc_layout() it selects 18 bits.
The Toshiba boards always selects 8 bit ecc_strength so they have no issues.
The kernel driver (gpmi-nand.c) seems to also use the legacy method (Resulting 18 bits in ecc strength for the Micron NAND). In common_nfc_set_geometry(): Both chip->ecc.strength and chip->ecc.size are 0.
I would expect ecc.strength to be set to 8, earlier but cannot find the spot where it should be set. Is the gpmi-nand driver missing a call to nand_ecc_choose_conf()? Maybe we need a legacy option for the kernel like u-boot.
We have +10K boards deployed so it's not so easy to switch from 18 -> 8 bits. I can explicit fix this in U-boot by forcing the legacy mode via a dt flag, but the gut feeling says this will come back to haunt us :)
/Sean
I honestly don't know about such issue on U-Boot side, maybe you can try to be more specific on what commit broke the logic for you as there are not so many of them between the two versions:
$ git l v2018.07..v2020.01 -- drivers/mtd/nand/raw/mxs_nand.c 1eb69ae4985 common: Move ARM cache operations out of common.h 9ab5f221a5e nand: mxs_nand: add API for switching different BCH layouts 1d43e24b946 i.MX6: nand: add nandbcb command for imx 1001502545f CONFIG_SPL_SYS_[DI]CACHE_OFF: add 04568bd0b6d MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL 5645df9e00a MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static 5ae585ba3a8 MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC a430fa06a4a mtd: move NAND files into a raw/ subdirectory
Hi Miquel,
Thanks for CC'ing the u-boot list :)
commit 616f03dabacb6c500e8a7ceb920cd08554c9fcae Author: Ye Li ye.li@nxp.com Date: Mon May 4 22:08:50 2020 +0800
mtd: gpmi: change the BCH layout setting for large oob NAND
This commit ^^ introduced the legacy function that was the "primary" before.
Guess we can say, that u-boot broke compatibility with the kernel. I have fixed my setup by enabling the legacy option via dt, in u-boot.
/Sean

Adding Ye Li as the author of such commit.
On Mon, Apr 19, 2021 at 6:34 AM Sean Nyekjaer sean@geanix.com wrote:
On 19/04/2021 09.32, Miquel Raynal wrote:
Hi Sean,
- u-boot ML
Sean Nyekjaer sean@geanix.com wrote on Wed, 14 Apr 2021 15:13:39 +0200:
Hi,
I have two boards with a iMX6ULL SoC one attached to a Micron NAND flash (MT29F4G08ABAFAWP) and one a Toshiba (TC58BVG2S0HTAI0).
After updating the boards from u-boot 2018.07 -> 2020.01, the Micron fitted boards is having ECC problems(in u-boot). U-boot 2018.07 selects ecc_strength to 18. U-boot 2020.01 selects ecc_strength to 8, but if I hardcode u-boot to run the mxs_nand_legacy_calc_ecc_layout() it selects 18 bits.
The Toshiba boards always selects 8 bit ecc_strength so they have no issues.
The kernel driver (gpmi-nand.c) seems to also use the legacy method (Resulting 18 bits in ecc strength for the Micron NAND). In common_nfc_set_geometry(): Both chip->ecc.strength and chip->ecc.size are 0.
I would expect ecc.strength to be set to 8, earlier but cannot find the spot where it should be set. Is the gpmi-nand driver missing a call to nand_ecc_choose_conf()? Maybe we need a legacy option for the kernel like u-boot.
We have +10K boards deployed so it's not so easy to switch from 18 -> 8 bits. I can explicit fix this in U-boot by forcing the legacy mode via a dt flag, but the gut feeling says this will come back to haunt us :)
/Sean
I honestly don't know about such issue on U-Boot side, maybe you can try to be more specific on what commit broke the logic for you as there are not so many of them between the two versions:
$ git l v2018.07..v2020.01 -- drivers/mtd/nand/raw/mxs_nand.c 1eb69ae4985 common: Move ARM cache operations out of common.h 9ab5f221a5e nand: mxs_nand: add API for switching different BCH layouts 1d43e24b946 i.MX6: nand: add nandbcb command for imx 1001502545f CONFIG_SPL_SYS_[DI]CACHE_OFF: add 04568bd0b6d MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL 5645df9e00a MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static 5ae585ba3a8 MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC a430fa06a4a mtd: move NAND files into a raw/ subdirectory
Hi Miquel,
Thanks for CC'ing the u-boot list :)
commit 616f03dabacb6c500e8a7ceb920cd08554c9fcae Author: Ye Li ye.li@nxp.com Date: Mon May 4 22:08:50 2020 +0800
mtd: gpmi: change the BCH layout setting for large oob NAND
This commit ^^ introduced the legacy function that was the "primary" before.
Guess we can say, that u-boot broke compatibility with the kernel. I have fixed my setup by enabling the legacy option via dt, in u-boot.
/Sean
participants (3)
-
Fabio Estevam
-
Miquel Raynal
-
Sean Nyekjaer