[PATCH v2 0/5] arm: mach-snapdragon: Qualcomm pinctrl driver cleanup

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Caleb Connolly

6 Nov 2023 6 Nov '23

4:28 p.m.

This series moves the Qualcomm pinctrl drivers from mach-snapdragon and mach-ipq40xx to drivers/pinctrl/qcom. It then makes the necessary changes to enable compatibility with Linux DTs.

The pinctrl hardware on most Qualcomm platforms is made up of "tiles", these are just banks of pins at different register addresses. The mapping between pin number and tile is totally arbitrary, this unfortunately means that it is necessary to have a map of pin to tile in order to support all pins. Up until now this driver has ignored tiles, meaning that the pin numbers and DT nodes are entirely different to the Linux DT and only a subset of pins are addressable.

Patch 2 solves this by introducing the pin_offset map, initially supporting SDM845. This map is used for all pin register lookups for both the pinctrl and GPIO drivers. Similarly to the clock/reset drivers these are both associated with a single DT node, where the pinctrl driver is responsible for binding the GPIO drivers.

Patch 3 introduces support for gpio-reserved-ranges, this property is used on some boards to mark pin ranges that shouldn't be touched (else firmware will trigger a fault and reset the board).

This series loosely depends on the associated clock driver cleanup which can be found here (Makefile and perhaps DTS conflicts):

https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ece84@linaro...

--- Changes in v2: * Drop msm -> qcom rename (will be handled in a future patch) * Drop "handle reserved ranges" patch to be introduced alongside a user * Re-order APQ4019 move to be the second patch * Change driver name to pinctrl_qcom instead of qcom_pinctrl * Add MAINTAINERS entry * Move shared GPIO header to mach-snapdragon * Link to v1: https://lore.kernel.org/r/20231025-b4-qcom-pinctrl-v1-0-9123d6a217eb@linaro....

--- Caleb Connolly (5): pinctrl: qcom: move out of mach-snapdragon pinctrl: qcom: move ipq4019 driver from mach-ipq40xx pinctrl: qcom: make compatible with linux DTs msm_gpio: use unsigned int fixup! pinctrl: qcom: make compatible with linux DTs

MAINTAINERS | 1 + arch/arm/Kconfig | 1 + arch/arm/dts/dragonboard845c-uboot.dtsi | 2 +- arch/arm/dts/sdm845.dtsi | 16 +- arch/arm/dts/starqltechn-uboot.dtsi | 5 +- arch/arm/dts/starqltechn.dts | 16 +- arch/arm/mach-ipq40xx/Makefile | 8 - arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 --------------------- arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 5 - arch/arm/mach-snapdragon/include/mach/gpio.h | 28 +++- arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 ------ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 33 ---- drivers/gpio/msm_gpio.c | 42 +++--- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/qcom/Kconfig | 46 ++++++ drivers/pinctrl/qcom/Makefile | 10 ++ .../pinctrl/qcom}/pinctrl-apq8016.c | 21 ++- .../pinctrl/qcom}/pinctrl-apq8096.c | 21 ++- .../pinctrl/qcom}/pinctrl-ipq4019.c | 25 +++- .../pinctrl/qcom/pinctrl-qcom.c | 70 +++++---- .../pinctrl/qcom/pinctrl-qcom.h | 15 +- .../pinctrl/qcom}/pinctrl-qcs404.c | 21 ++- drivers/pinctrl/qcom/pinctrl-sdm845.c | 100 +++++++++++++ 25 files changed, 350 insertions(+), 352 deletions(-) --- base-commit: 8c5e4ddf52ea3c1e85c44cdd5d5b2e2f6c892b4f

// Caleb (they/them)

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Caleb Connolly

6 Nov 6 Nov

4:29 p.m.

New subject: [PATCH v2 1/5] pinctrl: qcom: move out of mach-snapdragon

Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the rest of the pinctrl drivers, adjust the drivers so that support for each platform can be enabled/disabled individually and introduce platform specific configuration options.

Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- MAINTAINERS | 1 + arch/arm/mach-snapdragon/Kconfig | 4 +++ arch/arm/mach-snapdragon/Makefile | 5 --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/qcom/Kconfig | 39 ++++++++++++++++++++++ drivers/pinctrl/qcom/Makefile | 9 +++++ .../pinctrl/qcom}/pinctrl-apq8016.c | 19 +++++++++-- .../pinctrl/qcom}/pinctrl-apq8096.c | 19 +++++++++-- .../pinctrl/qcom/pinctrl-qcom.c | 39 ++++++++++++---------- .../pinctrl/qcom/pinctrl-qcom.h | 11 +++--- .../pinctrl/qcom}/pinctrl-qcs404.c | 19 +++++++++-- .../pinctrl/qcom}/pinctrl-sdm845.c | 19 +++++++++-- 13 files changed, 149 insertions(+), 37 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS index b483fa2ea95a..f6d63c8ab563 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -576,6 +576,7 @@ F: drivers/clk/qcom/ F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c +F: drivers/pinctrl/qcom/ F: drivers/serial/serial_msm.c F: drivers/serial/serial_msm_geni.c F: drivers/smem/msm_smem.c diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index dde37eccc55e..3c9f3bee3f18 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -16,6 +16,7 @@ config SDM845 bool "Qualcomm Snapdragon 845 SoC" select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_SDM845 + imply PINCTRL_QCOM_SDM845

config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -28,6 +29,7 @@ config TARGET_DRAGONBOARD410C select BOARD_LATE_INIT select ENABLE_ARM_SOC_BOOT0_HOOK imply CLK_QCOM_APQ8016 + imply PINCTRL_QCOM_APQ8016 help Support for 96Boards Dragonboard 410C. This board complies with 96Board Open Platform Specifications. Features: @@ -42,6 +44,7 @@ config TARGET_DRAGONBOARD410C config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" imply CLK_QCOM_APQ8096 + imply PINCTRL_QCOM_APQ8096 help Support for 96Boards Dragonboard 820C. This board complies with 96Board Open Platform Specifications. Features: @@ -76,6 +79,7 @@ config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_QCS404 + imply PINCTRL_QCOM_QCS404 help Support for Qualcomm Technologies, Inc. QCS404 evaluation board. Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 497ee35cf7d3..3a3a297c1768 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -8,9 +8,4 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o obj-y += misc.o obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 75b3ff47a2e8..53f32ea1612e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,6 +355,7 @@ source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" +source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fc1f01a02cbd..603c2e0a2da2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_PINCTRL_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index 000000000000..412925c48788 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,39 @@ +if ARCH_SNAPDRAGON + +config PINCTRL_QCOM + depends on PINCTRL_GENERIC + def_bool n + +menu "Qualcomm pinctrl drivers" + +config PINCTRL_QCOM_APQ8016 + bool "Qualcomm APQ8016 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the MSM8916 / APQ8016 + Snapdragon 410 SoC, as well as the associated GPIO driver. + +config PINCTRL_QCOM_APQ8096 + bool "Qualcomm APQ8096 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the MSM8996 / APQ8096 + Snapdragon 820 SoC, as well as the associated GPIO driver. + +config PINCTRL_QCOM_QCS404 + bool "Qualcomm QCS404 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC, + as well as the associated GPIO driver. + +config PINCTRL_QCOM_SDM845 + bool "Qualcomm SDM845 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, + as well as the associated GPIO driver. + +endmenu + +endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile new file mode 100644 index 000000000000..86f507427301 --- /dev/null +++ b/drivers/pinctrl/qcom/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Linaro Ltd. + +obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o +obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o +obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o +obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c similarity index 75% rename from arch/arm/mach-snapdragon/pinctrl-apq8016.c rename to drivers/pinctrl/qcom/pinctrl-apq8016.c index 70c0be0bca90..bcbc0df50715 100644 --- a/arch/arm/mach-snapdragon/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -6,8 +6,10 @@ * */

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -52,10 +54,23 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data apq8016_data = { +static const struct msm_pinctrl_data apq8016_data = { .pin_count = 133, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8016_get_function_name, .get_function_mux = apq8016_get_function_mux, .get_pin_name = apq8016_get_pin_name, }; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_apq8016) = { + .name = "pinctrl_apq8016", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c similarity index 74% rename from arch/arm/mach-snapdragon/pinctrl-apq8096.c rename to drivers/pinctrl/qcom/pinctrl-apq8096.c index 45462f01c2c7..525085617680 100644 --- a/arch/arm/mach-snapdragon/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -6,8 +6,10 @@ * */

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -47,10 +49,23 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data apq8096_data = { +static const struct msm_pinctrl_data apq8096_data = { .pin_count = 157, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8096_get_function_name, .get_function_mux = apq8096_get_function_mux, .get_pin_name = apq8096_get_pin_name, }; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_apq8096) = { + .name = "pinctrl_apq8096", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/drivers/pinctrl/qcom/pinctrl-qcom.c similarity index 85% rename from arch/arm/mach-snapdragon/pinctrl-snapdragon.c rename to drivers/pinctrl/qcom/pinctrl-qcom.c index 826dc5148661..1cface7f610b 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -11,10 +11,11 @@ #include <errno.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> -#include "pinctrl-snapdragon.h" +#include "pinctrl-qcom.h"

struct msm_pinctrl_priv { phys_addr_t base; @@ -109,7 +110,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; }

-static struct pinctrl_ops msm_pinctrl_ops = { +struct pinctrl_ops msm_pinctrl_ops = { .get_pins_count = msm_get_pins_count, .get_pin_name = msm_get_pin_name, .set_state = pinctrl_generic_set_state, @@ -121,12 +122,24 @@ static struct pinctrl_ops msm_pinctrl_ops = { .get_function_name = msm_get_function_name, };

-static int msm_pinctrl_bind(struct udevice *dev) +int msm_pinctrl_bind(struct udevice *dev) { ofnode node = dev_ofnode(dev); + struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev); + struct driver *drv; + struct udevice *pinctrl_dev; const char *name; int ret;

+ drv = lists_driver_lookup_name("pinctrl_qcom"); + if (!drv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data, + dev_ofnode(dev), &pinctrl_dev); + if (ret) + return ret; + ofnode_get_property(node, "gpio-controller", &ret); if (ret < 0) return 0; @@ -139,28 +152,18 @@ static int msm_pinctrl_bind(struct udevice *dev) /* Bind gpio node */ ret = device_bind_driver_to_node(dev, "gpio_msm", name, node, NULL); - if (ret) + if (ret) { + device_unbind(pinctrl_dev); return ret; - - dev_dbg(dev, "bind %s\n", name); + }

return 0; }

-static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data }, - { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data }, - { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, - { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, - { } -}; - -U_BOOT_DRIVER(pinctrl_snapdraon) = { - .name = "pinctrl_msm", +U_BOOT_DRIVER(pinctrl_qcom) = { + .name = "pinctrl_qcom", .id = UCLASS_PINCTRL, - .of_match = msm_pinctrl_ids, .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, - .bind = msm_pinctrl_bind, }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/drivers/pinctrl/qcom/pinctrl-qcom.h similarity index 68% rename from arch/arm/mach-snapdragon/pinctrl-snapdragon.h rename to drivers/pinctrl/qcom/pinctrl-qcom.h index 178ee01a41f4..1edd9a43ffda 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -5,8 +5,8 @@ * (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com * */ -#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H +#ifndef _PINCTRL_QCOM_H +#define _PINCTRL_QCOM_H

struct udevice;

@@ -25,9 +25,8 @@ struct pinctrl_function { int val; };

-extern struct msm_pinctrl_data apq8016_data; -extern struct msm_pinctrl_data apq8096_data; -extern struct msm_pinctrl_data sdm845_data; -extern struct msm_pinctrl_data qcs404_data; +extern struct pinctrl_ops msm_pinctrl_ops; + +int msm_pinctrl_bind(struct udevice *dev);

#endif diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c similarity index 78% rename from arch/arm/mach-snapdragon/pinctrl-qcs404.c rename to drivers/pinctrl/qcom/pinctrl-qcs404.c index a6e53c4412ec..272331c90b5c 100644 --- a/arch/arm/mach-snapdragon/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -5,8 +5,10 @@ * (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org */

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -59,10 +61,23 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data qcs404_data = { +static struct msm_pinctrl_data qcs404_data = { .pin_count = 126, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = qcs404_get_function_name, .get_function_mux = qcs404_get_function_mux, .get_pin_name = qcs404_get_pin_name, }; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_qcs404) = { + .name = "pinctrl_qcs404", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c similarity index 70% rename from arch/arm/mach-snapdragon/pinctrl-sdm845.c rename to drivers/pinctrl/qcom/pinctrl-sdm845.c index 40f2f012fa0d..1a09c5c81dc6 100644 --- a/arch/arm/mach-snapdragon/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -6,8 +6,10 @@ * */

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -35,10 +37,23 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data sdm845_data = { +static struct msm_pinctrl_data sdm845_data = { .pin_count = 150, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = sdm845_get_function_name, .get_function_mux = sdm845_get_function_mux, .get_pin_name = sdm845_get_pin_name, }; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_sdm845) = { + .name = "pinctrl_sdm845", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};

-- 2.42.0

Caleb Connolly

4:29 p.m.

New subject: [PATCH v2 2/5] pinctrl: qcom: move ipq4019 driver from mach-ipq40xx

Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom.

Acked-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 8 - arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 --------------------- arch/arm/mach-ipq40xx/pinctrl-snapdragon.h | 30 ---- drivers/pinctrl/qcom/Kconfig | 7 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom}/pinctrl-ipq4019.c | 23 ++- 7 files changed, 27 insertions(+), 209 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 69144ff9cdab..bd48131292e3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -767,6 +767,7 @@ config ARCH_IPQ40XX select SMEM select OF_CONTROL select CLK_QCOM_IPQ4019 + select PINCTRL_QCOM_IPQ4019 imply CMD_DM

config ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile deleted file mode 100644 index b36a935c6f9f..000000000000 --- a/arch/arm/mach-ipq40xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2019 Sartura Ltd. -# -# Author: Robert Marko robert.marko@sartura.hr - -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c deleted file mode 100644 index 036fec93d727..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TLMM driver for Qualcomm IPQ40xx - * - * (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com - * - * Copyright (c) 2020 Sartura Ltd. - * - * Author: Robert Marko robert.marko@sartura.hr - * - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <asm/io.h> -#include <dm/device_compat.h> -#include <dm/lists.h> -#include <dm/pinctrl.h> -#include <linux/bitops.h> -#include "pinctrl-snapdragon.h" - -struct msm_pinctrl_priv { - phys_addr_t base; - struct msm_pinctrl_data *data; -}; - -#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) - -static const struct pinconf_param msm_conf_params[] = { - { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, - { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, - { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 }, -}; - -static int msm_get_functions_count(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->functions_count; -} - -static int msm_get_pins_count(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->pin_count; -} - -static const char *msm_get_function_name(struct udevice *dev, - unsigned int selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->get_function_name(dev, selector); -} - -static int msm_pinctrl_probe(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - priv->base = devfdt_get_addr(dev); - priv->data = (struct msm_pinctrl_data *)dev->driver_data; - - return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; -} - -static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->get_pin_name(dev, selector); -} - -static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, - unsigned int func_selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, - priv->data->get_function_mux(func_selector) << 2); - return 0; -} - -static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, - unsigned int param, unsigned int argument) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - switch (param) { - case PIN_CONFIG_DRIVE_STRENGTH: - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_DRV_STRENGTH_MASK, argument << 6); - break; - case PIN_CONFIG_BIAS_DISABLE: - clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_GPIO_PULL_MASK); - break; - case PIN_CONFIG_BIAS_PULL_UP: - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_GPIO_PULL_MASK, argument); - break; - default: - return 0; - } - - return 0; -} - -static int msm_pinctrl_bind(struct udevice *dev) -{ - ofnode node = dev_ofnode(dev); - const char *name; - int ret; - - ofnode_get_property(node, "gpio-controller", &ret); - if (ret < 0) - return 0; - - /* Get the name of gpio node */ - name = ofnode_get_name(node); - if (!name) - return -EINVAL; - - /* Bind gpio node */ - ret = device_bind_driver_to_node(dev, "gpio_msm", - name, node, NULL); - if (ret) - return ret; - - dev_dbg(dev, "bind %s\n", name); - - return 0; -} - -static struct pinctrl_ops msm_pinctrl_ops = { - .get_pins_count = msm_get_pins_count, - .get_pin_name = msm_get_pin_name, - .set_state = pinctrl_generic_set_state, - .pinmux_set = msm_pinmux_set, - .pinconf_num_params = ARRAY_SIZE(msm_conf_params), - .pinconf_params = msm_conf_params, - .pinconf_set = msm_pinconf_set, - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, -}; - -static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, - { } -}; - -U_BOOT_DRIVER(pinctrl_snapdraon) = { - .name = "pinctrl_msm", - .id = UCLASS_PINCTRL, - .of_match = msm_pinctrl_ids, - .priv_auto = sizeof(struct msm_pinctrl_priv), - .ops = &msm_pinctrl_ops, - .probe = msm_pinctrl_probe, - .bind = msm_pinctrl_bind, -}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h deleted file mode 100644 index 2341a713495d..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm Pin control - * - * (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com - * - */ -#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H - -#include <common.h> - -struct msm_pinctrl_data { - int pin_count; - int functions_count; - const char *(*get_function_name)(struct udevice *dev, - unsigned int selector); - unsigned int (*get_function_mux)(unsigned int selector); - const char *(*get_pin_name)(struct udevice *dev, - unsigned int selector); -}; - -struct pinctrl_function { - const char *name; - int val; -}; - -extern struct msm_pinctrl_data ipq4019_data; - -#endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 412925c48788..2fe639814785 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -20,6 +20,13 @@ config PINCTRL_QCOM_APQ8096 Say Y here to enable support for pinctrl on the MSM8996 / APQ8096 Snapdragon 820 SoC, as well as the associated GPIO driver.

+config PINCTRL_QCOM_IPQ4019 + bool "Qualcomm IPQ4019 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the IPQ4019 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 86f507427301..6d9aca6d7b7e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -4,6 +4,7 @@

obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c similarity index 73% rename from arch/arm/mach-ipq40xx/pinctrl-ipq4019.c rename to drivers/pinctrl/qcom/pinctrl-ipq4019.c index 3e365f8cc86a..87058e21ce80 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -7,12 +7,13 @@ * Author: Robert Marko robert.marko@sartura.hr */

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 -static char pin_name[MAX_PIN_NAME_LEN]; - +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ @@ -26,7 +27,6 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"mdc_0", 1}, /* Only for GPIO7 */ {"mdc_1", 2}, /* Only for GPIO52 */ }; - static const char *ipq4019_get_function_name(struct udevice *dev, unsigned int selector) { @@ -45,10 +45,23 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data ipq4019_data = { +static const struct msm_pinctrl_data ipq4019_data = { .pin_count = 100, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = ipq4019_get_function_name, .get_function_mux = ipq4019_get_function_mux, .get_pin_name = ipq4019_get_pin_name, }; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_ipq4019) = { + .name = "pinctrl_ipq4019", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +};

-- 2.42.0

Caleb Connolly

4:29 p.m.

New subject: [PATCH v2 3/5] pinctrl: qcom: make compatible with linux DTs

The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver.

Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/dragonboard845c-uboot.dtsi | 2 +- arch/arm/dts/sdm845.dtsi | 16 ++-------- arch/arm/dts/starqltechn-uboot.dtsi | 5 +--- arch/arm/dts/starqltechn.dts | 16 +++++----- arch/arm/mach-snapdragon/include/mach/gpio.h | 28 ++++++++++++++--- drivers/gpio/msm_gpio.c | 36 ++++++++++++---------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 2 +- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +- drivers/pinctrl/qcom/pinctrl-qcom.c | 31 ++++++++++++------- drivers/pinctrl/qcom/pinctrl-qcom.h | 5 +++- drivers/pinctrl/qcom/pinctrl-qcs404.c | 2 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 45 ++++++++++++++++++++++++++-- 13 files changed, 130 insertions(+), 62 deletions(-)

diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi index 7106db8a7348..7728f4f4a3e5 100644 --- a/arch/arm/dts/dragonboard845c-uboot.dtsi +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi @@ -19,7 +19,7 @@ bootph-all; };

- pinctrl_north@3900000 { + pinctrl@3400000 { bootph-all; }; }; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 3b86b9328fc6..4798ace0ff8b 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -26,23 +26,13 @@ #power-domain-cells = <1>; };

- gpio_north: gpio_north@3900000 { - #gpio-cells = <2>; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; - reg = <0x3900000 0x400000>; - gpio-count = <150>; - gpio-controller; - gpio-ranges = <&gpio_north 0 0 150>; - gpio-bank-name = "soc_north."; - }; - - tlmm_north: pinctrl_north@3900000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0x3900000 0x400000>; + reg = <0x3400000 0xc00000>; gpio-count = <150>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm_north 0 0 150>; + gpio-ranges = <&tlmm 0 0 150>;

/* DEBUG UART */ qup_uart9: qup-uart9-default { diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi index d81a22ffe492..034d5c1c07ed 100644 --- a/arch/arm/dts/starqltechn-uboot.dtsi +++ b/arch/arm/dts/starqltechn-uboot.dtsi @@ -19,10 +19,7 @@ clock-controller@100000 { bootph-all; }; - gpio_north@3900000 { - bootph-all; - }; - pinctrl_north@3900000 { + pinctrl@3400000 { bootph-all; }; }; diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index eec51d165f98..5b6372bee79a 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -65,15 +65,15 @@ serial@a84000 { status = "okay"; }; + }; +};

- pinctrl_north@3900000 { - muic_i2c: muic_i2c { - pins = "GPIO_33", "GPIO_34"; - drive-strength = <0x2>; - function = "gpio"; - bias-disable; - }; - }; +&tlmm { + muic_i2c: muic-i2c-n { + pins = "GPIO_33", "GPIO_34"; + drive-strength = <0x2>; + function = "gpio"; + bias-disable; }; };

diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index bbc2bc16175d..8dac62f870b9 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -1,8 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Empty gpio.h + * Qualcomm common pin control data. * - * This file must stay as arch/arm/include/asm/gpio.h requires it. - * - * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * Copyright (C) 2023 Linaro Ltd. */ +#ifndef _QCOM_GPIO_H_ +#define _QCOM_GPIO_H_ + +#include <asm/types.h> +#include <stdbool.h> + +struct msm_pin_data { + int pin_count; + const unsigned int *pin_offsets; +}; + +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) +{ + u32 out = (selector * 0x1000); + + if (offs) + return out + offs[selector]; + + return out; +} + +#endif /* _QCOM_GPIO_H_ */ diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 51670f263716..7d77776a25fd 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -11,13 +11,10 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> +#include <qcom-gpio.h>

DECLARE_GLOBAL_DATA_PTR;

-/* Register offsets */ -#define GPIO_CONFIG_OFF(no) ((no) * 0x1000) -#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4) - /* OE */ #define GPIO_OE_DISABLE (0x0 << 9) #define GPIO_OE_ENABLE (0x1 << 9) @@ -29,15 +26,22 @@ DECLARE_GLOBAL_DATA_PTR;

struct msm_gpio_bank { phys_addr_t base; + const struct msm_pin_data *pin_data; };

+#define GPIO_CONFIG_REG(dev, x) \ + (qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x)) + +#define GPIO_IN_OUT_REG(dev, x) \ + (GPIO_CONFIG_REG(dev, x) + 0x4) + static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); - phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);

/* Disable OE bit */ - clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE); + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), + GPIO_OE_MASK, GPIO_OE_DISABLE);

return 0; } @@ -48,7 +52,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)

value = !!value; /* set value */ - writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));

return 0; } @@ -57,13 +61,13 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); - phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);

value = !!value; /* set value */ - writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); /* switch direction */ - clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE); + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), + GPIO_OE_MASK, GPIO_OE_ENABLE);

return 0; } @@ -72,14 +76,14 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

- return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN); + return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); }

-static int msm_gpio_get_function(struct udevice *dev, unsigned offset) +static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

- if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE) + if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) return GPIOF_OUTPUT;

return GPIOF_INPUT; @@ -98,6 +102,7 @@ static int msm_gpio_probe(struct udevice *dev) struct msm_gpio_bank *priv = dev_get_priv(dev);

priv->base = dev_read_addr(dev); + priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);

return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; } @@ -105,9 +110,10 @@ static int msm_gpio_probe(struct udevice *dev) static int msm_gpio_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);

- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "gpio-count", 0); + /* Get the pin count from the pinctrl driver */ + uc_priv->gpio_count = pin_data->pin_count; uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "gpio-bank-name", NULL); if (uc_priv->bank_name == NULL) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index bcbc0df50715..8149ffd83cc4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -55,7 +55,7 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8016_data = { - .pin_count = 133, + .pin_data = { .pin_count = 133, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8016_get_function_name, .get_function_mux = apq8016_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 525085617680..d64ab1ff7bee 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -50,7 +50,7 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8096_data = { - .pin_count = 157, + .pin_data = { .pin_count = 157, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8096_get_function_name, .get_function_mux = apq8096_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 87058e21ce80..2d99f99e1e45 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -46,7 +46,7 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data ipq4019_data = { - .pin_count = 100, + .pin_data = { .pin_count = 100, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = ipq4019_get_function_name, .get_function_mux = ipq4019_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 1cface7f610b..dc3d8c4d9034 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -13,8 +13,11 @@ #include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> +#include <mach/gpio.h> + #include "pinctrl-qcom.h"

struct msm_pinctrl_priv { @@ -22,7 +25,9 @@ struct msm_pinctrl_priv { struct msm_pinctrl_data *data; };

-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define GPIO_CONFIG_REG(priv, x) \ + (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x)) + #define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) @@ -45,7 +50,7 @@ static int msm_get_pins_count(struct udevice *dev) { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

- return priv->data->pin_count; + return priv->data->pin_data.pin_count; }

static const char *msm_get_function_name(struct udevice *dev, @@ -61,7 +66,7 @@ static int msm_pinctrl_probe(struct udevice *dev) struct msm_pinctrl_priv *priv = dev_get_priv(dev);

priv->base = dev_read_addr(dev); - priv->data = (struct msm_pinctrl_data *)dev->driver_data; + priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);

return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; } @@ -78,7 +83,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, priv->data->get_function_mux(func_selector) << 2); return 0; @@ -92,15 +97,15 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: argument = (argument / 2) - 1; - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_DRV_STRENGTH_MASK, argument << 6); break; case PIN_CONFIG_BIAS_DISABLE: - clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK); break; case PIN_CONFIG_BIAS_PULL_UP: - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; default: @@ -149,9 +154,15 @@ int msm_pinctrl_bind(struct udevice *dev) if (!name) return -EINVAL;

- /* Bind gpio node */ - ret = device_bind_driver_to_node(dev, "gpio_msm", - name, node, NULL); + drv = lists_driver_lookup_name("gpio_msm"); + if (!drv) { + printf("Can't find gpio_msm driver\n"); + return -ENODEV; + } + + /* Bind gpio device as a child of the pinctrl device */ + ret = device_bind_with_driver_data(pinctrl_dev, drv, + name, (ulong)&data->pin_data, node, NULL); if (ret) { device_unbind(pinctrl_dev); return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 1edd9a43ffda..07f2eae9baea 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -8,10 +8,13 @@ #ifndef _PINCTRL_QCOM_H #define _PINCTRL_QCOM_H

+#include <asm/types.h> +#include <mach/gpio.h> + struct udevice;

struct msm_pinctrl_data { - int pin_count; + struct msm_pin_data pin_data; int functions_count; const char *(*get_function_name)(struct udevice *dev, unsigned int selector); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 272331c90b5c..ac00afa2a1f4 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -62,7 +62,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data qcs404_data = { - .pin_count = 126, + .pin_data = { .pin_count = 126, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = qcs404_get_function_name, .get_function_mux = qcs404_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 1a09c5c81dc6..9f0f4085ce2d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -3,6 +3,7 @@ * Qualcomm SDM845 pinctrl * * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + * (C) Copyright 2023 Linaro Ltd. * */

@@ -11,6 +12,10 @@

#include "pinctrl-qcom.h"

+#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define EAST 0x00100000 + #define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");

@@ -19,6 +24,39 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, };

+static const unsigned int sdm845_pin_offsets[] = { + [0] = EAST, [1] = EAST, [2] = EAST, [3] = EAST, [4] = NORTH, + [5] = NORTH, [6] = NORTH, [7] = NORTH, [8] = EAST, [9] = EAST, + [10] = EAST, [11] = EAST, [12] = SOUTH, [13] = SOUTH, [14] = SOUTH, + [15] = SOUTH, [16] = SOUTH, [17] = SOUTH, [18] = SOUTH, [19] = SOUTH, + [20] = SOUTH, [21] = SOUTH, [22] = SOUTH, [23] = SOUTH, [24] = SOUTH, + [25] = SOUTH, [26] = SOUTH, [27] = EAST, [28] = EAST, [29] = EAST, + [30] = EAST, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] = NORTH, + [35] = SOUTH, [36] = SOUTH, [37] = SOUTH, [38] = NORTH, [39] = EAST, + [40] = SOUTH, [41] = EAST, [42] = EAST, [43] = EAST, [44] = EAST, + [45] = EAST, [46] = EAST, [47] = EAST, [48] = EAST, [49] = NORTH, + [50] = NORTH, [51] = NORTH, [52] = NORTH, [53] = NORTH, [54] = NORTH, + [55] = NORTH, [56] = NORTH, [57] = NORTH, [58] = NORTH, [59] = NORTH, + [60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH, [64] = NORTH, + [65] = NORTH, [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = EAST, + [70] = EAST, [71] = EAST, [72] = EAST, [73] = EAST, [74] = EAST, + [75] = EAST, [76] = EAST, [77] = EAST, [78] = EAST, [79] = NORTH, + [80] = NORTH, [81] = NORTH, [82] = NORTH, [83] = NORTH, [84] = NORTH, + [85] = EAST, [86] = EAST, [87] = EAST, [88] = EAST, [89] = SOUTH, + [90] = SOUTH, [91] = SOUTH, [92] = SOUTH, [93] = SOUTH, [94] = SOUTH, + [95] = SOUTH, [96] = SOUTH, [97] = NORTH, [98] = NORTH, [99] = NORTH, + [100] = NORTH, [101] = NORTH, [102] = NORTH, [103] = NORTH, [104] = NORTH, + [105] = NORTH, [106] = NORTH, [107] = NORTH, [108] = NORTH, [109] = NORTH, + [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, [114] = NORTH, + [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH, + [120] = NORTH, [121] = NORTH, [122] = EAST, [123] = EAST, [124] = EAST, + [125] = EAST, [126] = EAST, [127] = NORTH, [128] = NORTH, [129] = NORTH, + [130] = NORTH, [131] = NORTH, [132] = NORTH, [133] = NORTH, [134] = NORTH, + [135] = NORTH, [136] = NORTH, [137] = NORTH, [138] = NORTH, [139] = NORTH, + [140] = NORTH, [141] = NORTH, [142] = NORTH, [143] = NORTH, [144] = NORTH, + [145] = NORTH, [146] = NORTH, [147] = NORTH, [148] = NORTH, [149] = NORTH, +}; + static const char *sdm845_get_function_name(struct udevice *dev, unsigned int selector) { @@ -28,7 +66,7 @@ static const char *sdm845_get_function_name(struct udevice *dev, static const char *sdm845_get_pin_name(struct udevice *dev, unsigned int selector) { - snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); return pin_name; }

@@ -38,7 +76,10 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data sdm845_data = { - .pin_count = 150, + .pin_data = { + .pin_offsets = sdm845_pin_offsets, + .pin_count = ARRAY_SIZE(sdm845_pin_offsets), + }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = sdm845_get_function_name, .get_function_mux = sdm845_get_function_mux,

-- 2.42.0

Sumit Garg

7 Nov 7 Nov

6:28 a.m.

New subject: [PATCH v2 3/5] pinctrl: qcom: make compatible with linux DTs

On Mon, 6 Nov 2023 at 20:59, Caleb Connolly caleb.connolly@linaro.org wrote:

...

The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver.

Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/dts/dragonboard845c-uboot.dtsi | 2 +- arch/arm/dts/sdm845.dtsi | 16 ++-------- arch/arm/dts/starqltechn-uboot.dtsi | 5 +--- arch/arm/dts/starqltechn.dts | 16 +++++----- arch/arm/mach-snapdragon/include/mach/gpio.h | 28 ++++++++++++++--- drivers/gpio/msm_gpio.c | 36 ++++++++++++---------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 2 +- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +- drivers/pinctrl/qcom/pinctrl-qcom.c | 31 ++++++++++++------- drivers/pinctrl/qcom/pinctrl-qcom.h | 5 +++- drivers/pinctrl/qcom/pinctrl-qcs404.c | 2 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 45 ++++++++++++++++++++++++++-- 13 files changed, 130 insertions(+), 62 deletions(-)

diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi index 7106db8a7348..7728f4f4a3e5 100644 --- a/arch/arm/dts/dragonboard845c-uboot.dtsi +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi @@ -19,7 +19,7 @@ bootph-all; };
          pinctrl_north@3900000 {
          pinctrl@3400000 {
                  bootph-all;
          };
  };
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 3b86b9328fc6..4798ace0ff8b 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -26,23 +26,13 @@ #power-domain-cells = <1>; };
          gpio_north: gpio_north@3900000 {
                  #gpio-cells = <2>;
          tlmm: pinctrl@3400000 {
                  compatible = "qcom,sdm845-pinctrl";
                  reg = <0x3900000 0x400000>;
                  gpio-count = <150>;
                  gpio-controller;
                  gpio-ranges = <&gpio_north 0 0 150>;
                  gpio-bank-name = "soc_north.";
          };
          tlmm_north: pinctrl_north@3900000 {
                  compatible = "qcom,sdm845-pinctrl";
                  reg = <0x3900000 0x400000>;
                  reg = <0x3400000 0xc00000>;
                  gpio-count = <150>;
                  gpio-controller;
                  #gpio-cells = <2>;
                  gpio-ranges = <&tlmm_north 0 0 150>;
                  gpio-ranges = <&tlmm 0 0 150>;

                  /* DEBUG UART */
                  qup_uart9: qup-uart9-default {
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi index d81a22ffe492..034d5c1c07ed 100644 --- a/arch/arm/dts/starqltechn-uboot.dtsi +++ b/arch/arm/dts/starqltechn-uboot.dtsi @@ -19,10 +19,7 @@ clock-controller@100000 { bootph-all; };
          gpio_north@3900000 {
                  bootph-all;
          };
          pinctrl_north@3900000 {
          pinctrl@3400000 {
                  bootph-all;
          };
  };
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index eec51d165f98..5b6372bee79a 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -65,15 +65,15 @@ serial@a84000 { status = "okay"; };
  };
+};
          pinctrl_north@3900000 {
                  muic_i2c: muic_i2c {
                          pins = "GPIO_33", "GPIO_34";
                          drive-strength = <0x2>;
                          function = "gpio";
                          bias-disable;
                  };
          };
+&tlmm {
  muic_i2c: muic-i2c-n {
          pins = "GPIO_33", "GPIO_34";
          drive-strength = <0x2>;
          function = "gpio";
          bias-disable;
  };
};

diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index bbc2bc16175d..8dac62f870b9 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -1,8 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /*

Empty gpio.h

Qualcomm common pin control data.

This file must stay as arch/arm/include/asm/gpio.h requires it.

(C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com

Copyright (C) 2023 Linaro Ltd.

*/

+#ifndef _QCOM_GPIO_H_ +#define _QCOM_GPIO_H_

+#include <asm/types.h> +#include <stdbool.h>

+struct msm_pin_data {
  int pin_count;
  const unsigned int *pin_offsets;
+};

+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) +{
  u32 out = (selector * 0x1000);
  if (offs)
          return out + offs[selector];
  return out;
+}

+#endif /* _QCOM_GPIO_H_ */ diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 51670f263716..7d77776a25fd 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -11,13 +11,10 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> +#include <qcom-gpio.h>

It looks like you forgot to merge fix patch #5 here. Once you do that feel free to add:

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

...

DECLARE_GLOBAL_DATA_PTR;

-/* Register offsets */ -#define GPIO_CONFIG_OFF(no) ((no) * 0x1000) -#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)

/* OE */ #define GPIO_OE_DISABLE (0x0 << 9) #define GPIO_OE_ENABLE (0x1 << 9) @@ -29,15 +26,22 @@ DECLARE_GLOBAL_DATA_PTR;

struct msm_gpio_bank { phys_addr_t base;
  const struct msm_pin_data *pin_data;
};

+#define GPIO_CONFIG_REG(dev, x) \
  (qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x))
+#define GPIO_IN_OUT_REG(dev, x) \
  (GPIO_CONFIG_REG(dev, x) + 0x4)
static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);
  phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);

  /* Disable OE bit */
  clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
  clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
                  GPIO_OE_MASK, GPIO_OE_DISABLE);

  return 0;
} @@ -48,7 +52,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
    value = !!value;
    /* set value */
  writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
  writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));

  return 0;
} @@ -57,13 +61,13 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);
  phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);

  value = !!value;
  /* set value */
  writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
  writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
  /* switch direction */
  clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
  clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
                  GPIO_OE_MASK, GPIO_OE_ENABLE);

  return 0;
} @@ -72,14 +76,14 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);
  return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
  return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}

-static int msm_gpio_get_function(struct udevice *dev, unsigned offset) +static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);
  if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
  if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
          return GPIOF_OUTPUT;

  return GPIOF_INPUT;
@@ -98,6 +102,7 @@ static int msm_gpio_probe(struct udevice *dev) struct msm_gpio_bank *priv = dev_get_priv(dev);
    priv->base = dev_read_addr(dev);
  priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);

  return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
} @@ -105,9 +110,10 @@ static int msm_gpio_probe(struct udevice *dev) static int msm_gpio_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
  uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
                                       "gpio-count", 0);
  /* Get the pin count from the pinctrl driver */
  uc_priv->gpio_count = pin_data->pin_count;
  uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
                                   "gpio-bank-name", NULL);
  if (uc_priv->bank_name == NULL)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index bcbc0df50715..8149ffd83cc4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -55,7 +55,7 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8016_data = {
  .pin_count = 133,
  .pin_data = { .pin_count = 133, },
  .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  .get_function_name = apq8016_get_function_name,
  .get_function_mux = apq8016_get_function_mux,
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 525085617680..d64ab1ff7bee 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -50,7 +50,7 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8096_data = {
  .pin_count = 157,
  .pin_data = { .pin_count = 157, },
  .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  .get_function_name = apq8096_get_function_name,
  .get_function_mux = apq8096_get_function_mux,
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 87058e21ce80..2d99f99e1e45 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -46,7 +46,7 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data ipq4019_data = {
  .pin_count = 100,
  .pin_data = { .pin_count = 100, },
  .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  .get_function_name = ipq4019_get_function_name,
  .get_function_mux = ipq4019_get_function_mux,
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 1cface7f610b..dc3d8c4d9034 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -13,8 +13,11 @@ #include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> +#include <mach/gpio.h>

#include "pinctrl-qcom.h"

struct msm_pinctrl_priv { @@ -22,7 +25,9 @@ struct msm_pinctrl_priv { struct msm_pinctrl_data *data; };

-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define GPIO_CONFIG_REG(priv, x) \
  (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) @@ -45,7 +50,7 @@ static int msm_get_pins_count(struct udevice *dev) { struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  return priv->data->pin_count;
  return priv->data->pin_data.pin_count;
}

static const char *msm_get_function_name(struct udevice *dev, @@ -61,7 +66,7 @@ static int msm_pinctrl_probe(struct udevice *dev) struct msm_pinctrl_priv *priv = dev_get_priv(dev);
    priv->base = dev_read_addr(dev);
  priv->data = (struct msm_pinctrl_data *)dev->driver_data;
  priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);

  return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
} @@ -78,7 +83,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                  TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
                  priv->data->get_function_mux(func_selector) << 2);
  return 0;
@@ -92,15 +97,15 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: argument = (argument / 2) - 1;
          clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
          clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                          TLMM_DRV_STRENGTH_MASK, argument << 6);
          break;
  case PIN_CONFIG_BIAS_DISABLE:
          clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
          clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                       TLMM_GPIO_PULL_MASK);
          break;
  case PIN_CONFIG_BIAS_PULL_UP:
          clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
          clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                          TLMM_GPIO_PULL_MASK, argument);
          break;
  default:
@@ -149,9 +154,15 @@ int msm_pinctrl_bind(struct udevice *dev) if (!name) return -EINVAL;
  /* Bind gpio node */
  ret = device_bind_driver_to_node(dev, "gpio_msm",
                                   name, node, NULL);
  drv = lists_driver_lookup_name("gpio_msm");
  if (!drv) {
          printf("Can't find gpio_msm driver\n");
          return -ENODEV;
  }
  /* Bind gpio device as a child of the pinctrl device */
  ret = device_bind_with_driver_data(pinctrl_dev, drv,
                                     name, (ulong)&data->pin_data, node, NULL);
  if (ret) {
          device_unbind(pinctrl_dev);
          return ret;
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 1edd9a43ffda..07f2eae9baea 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -8,10 +8,13 @@ #ifndef _PINCTRL_QCOM_H #define _PINCTRL_QCOM_H

+#include <asm/types.h> +#include <mach/gpio.h>

struct udevice;

struct msm_pinctrl_data {
  int pin_count;
  struct msm_pin_data pin_data;
  int functions_count;
  const char *(*get_function_name)(struct udevice *dev,
                                   unsigned int selector);
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 272331c90b5c..ac00afa2a1f4 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -62,7 +62,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data qcs404_data = {
  .pin_count = 126,
  .pin_data = { .pin_count = 126, },
  .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  .get_function_name = qcs404_get_function_name,
  .get_function_mux = qcs404_get_function_mux,
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 1a09c5c81dc6..9f0f4085ce2d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -3,6 +3,7 @@

Qualcomm SDM845 pinctrl

(C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com

(C) Copyright 2023 Linaro Ltd.

*/

@@ -11,6 +12,10 @@

#include "pinctrl-qcom.h"

+#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define EAST 0x00100000

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");

@@ -19,6 +24,39 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, };

+static const unsigned int sdm845_pin_offsets[] = {
  [0] = EAST,    [1] = EAST,    [2] = EAST,    [3] = EAST,    [4] = NORTH,
  [5] = NORTH,   [6] = NORTH,   [7] = NORTH,   [8] = EAST,    [9] = EAST,
  [10] = EAST,   [11] = EAST,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
  [15] = SOUTH,  [16] = SOUTH,  [17] = SOUTH,  [18] = SOUTH,  [19] = SOUTH,
  [20] = SOUTH,  [21] = SOUTH,  [22] = SOUTH,  [23] = SOUTH,  [24] = SOUTH,
  [25] = SOUTH,  [26] = SOUTH,  [27] = EAST,   [28] = EAST,   [29] = EAST,
  [30] = EAST,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = NORTH,
  [35] = SOUTH,  [36] = SOUTH,  [37] = SOUTH,  [38] = NORTH,  [39] = EAST,
  [40] = SOUTH,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
  [45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = NORTH,
  [50] = NORTH,  [51] = NORTH,  [52] = NORTH,  [53] = NORTH,  [54] = NORTH,
  [55] = NORTH,  [56] = NORTH,  [57] = NORTH,  [58] = NORTH,  [59] = NORTH,
  [60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
  [65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = EAST,
  [70] = EAST,   [71] = EAST,   [72] = EAST,   [73] = EAST,   [74] = EAST,
  [75] = EAST,   [76] = EAST,   [77] = EAST,   [78] = EAST,   [79] = NORTH,
  [80] = NORTH,  [81] = NORTH,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
  [85] = EAST,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = SOUTH,
  [90] = SOUTH,  [91] = SOUTH,  [92] = SOUTH,  [93] = SOUTH,  [94] = SOUTH,
  [95] = SOUTH,  [96] = SOUTH,  [97] = NORTH,  [98] = NORTH,  [99] = NORTH,
  [100] = NORTH, [101] = NORTH, [102] = NORTH, [103] = NORTH, [104] = NORTH,
  [105] = NORTH, [106] = NORTH, [107] = NORTH, [108] = NORTH, [109] = NORTH,
  [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, [114] = NORTH,
  [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH,
  [120] = NORTH, [121] = NORTH, [122] = EAST,  [123] = EAST,  [124] = EAST,
  [125] = EAST,  [126] = EAST,  [127] = NORTH, [128] = NORTH, [129] = NORTH,
  [130] = NORTH, [131] = NORTH, [132] = NORTH, [133] = NORTH, [134] = NORTH,
  [135] = NORTH, [136] = NORTH, [137] = NORTH, [138] = NORTH, [139] = NORTH,
  [140] = NORTH, [141] = NORTH, [142] = NORTH, [143] = NORTH, [144] = NORTH,
  [145] = NORTH, [146] = NORTH, [147] = NORTH, [148] = NORTH, [149] = NORTH,
+};

static const char *sdm845_get_function_name(struct udevice *dev, unsigned int selector) { @@ -28,7 +66,7 @@ static const char *sdm845_get_function_name(struct udevice *dev, static const char *sdm845_get_pin_name(struct udevice *dev, unsigned int selector) {
  snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
  snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
  return pin_name;
}

@@ -38,7 +76,10 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data sdm845_data = {
  .pin_count = 150,
  .pin_data = {
          .pin_offsets = sdm845_pin_offsets,
          .pin_count = ARRAY_SIZE(sdm845_pin_offsets),
  },
  .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  .get_function_name = sdm845_get_function_name,
  .get_function_mux = sdm845_get_function_mux,
-- 2.42.0

Caleb Connolly

6 Nov 6 Nov

4:29 p.m.

New subject: [PATCH v2 4/5] msm_gpio: use unsigned int

Replaces the uses of "unsigned" with "unsigned int".

Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/gpio/msm_gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 7d77776a25fd..3e4a0194b10a 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -46,7 +46,7 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) return 0; }

-static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);

@@ -57,7 +57,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) return 0; }

-static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, +static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -72,14 +72,14 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, return 0; }

-static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) +static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); }

-static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) +static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

-- 2.42.0

Caleb Connolly

4:29 p.m.

New subject: [PATCH v2 5/5] fixup! pinctrl: qcom: make compatible with linux DTs

--- drivers/gpio/msm_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 3e4a0194b10a..80cd28bb231f 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -11,7 +11,7 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> -#include <qcom-gpio.h> +#include <mach/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

-- 2.42.0

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