[U-Boot] [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well.
Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com --- board/freescale/ls1043ardb/cpld.c | 26 ++++++++++++++++++++++++-- board/freescale/ls1043ardb/cpld.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c2824..c645283 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) { + u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7); @@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) { - CPLD_WRITE(global_rst, 1); + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); }
void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif
Qianyu,
The reset command is used to boot from the location set in the hardware switch.
Regards, Mingkai
-----Original Message----- From: Gong Qianyu [mailto:Qianyu.Gong@nxp.com] Sent: Monday, April 25, 2016 4:39 PM To: u-boot@lists.denx.de; york sun; Mingkai Hu Cc: Shaohui Xie; Zhiqiang Hou; Wenbin Song; Qianyu Gong Subject: [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well.
Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com
board/freescale/ls1043ardb/cpld.c | 26 ++++++++++++++++++++++++-- board/freescale/ls1043ardb/cpld.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c2824..c645283 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) {
- u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
cpld_rev_bit(®5);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
CPLD_WRITE(cfg_rcw_src1, reg5);
CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) {
- CPLD_WRITE(global_rst, 1);
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
- cpld_rev_bit(®5);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
- CPLD_WRITE(vbank, 0);
- CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040
#endif
2.1.0.27.g96db324
Hi Mingkai,
-----Original Message----- From: Mingkai Hu Sent: Saturday, April 30, 2016 8:26 PM To: Qianyu Gong qianyu.gong@nxp.com; u-boot@lists.denx.de; york sun york.sun@nxp.com Cc: Shaohui Xie shaohui.xie@nxp.com; Zhiqiang Hou zhiqiang.hou@nxp.com; Wenbin Song wenbin.song@nxp.com; Qianyu Gong qianyu.gong@nxp.com Subject: RE: [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
Qianyu,
The reset command is used to boot from the location set in the hardware switch.
Regards, Mingkai
Using 'reset' could be enough for that purpose, I think. 'cpld reset' and 'cpld reset altbank' are used to reset to boot from NOR(default or alternate bank).
Regards, Qianyu
-----Original Message----- From: Gong Qianyu [mailto:Qianyu.Gong@nxp.com] Sent: Monday, April 25, 2016 4:39 PM To: u-boot@lists.denx.de; york sun; Mingkai Hu Cc: Shaohui Xie; Zhiqiang Hou; Wenbin Song; Qianyu Gong Subject: [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well.
Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com
board/freescale/ls1043ardb/cpld.c | 26 ++++++++++++++++++++++++-- board/freescale/ls1043ardb/cpld.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c2824..c645283 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) {
- u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
cpld_rev_bit(®5);
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
CPLD_WRITE(cfg_rcw_src1, reg5);
CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) {
- CPLD_WRITE(global_rst, 1);
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
- cpld_rev_bit(®5);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
- CPLD_WRITE(vbank, 0);
- CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040
#endif
2.1.0.27.g96db324
On 04/25/2016 01:48 AM, Gong Qianyu wrote:
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well.
Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com
board/freescale/ls1043ardb/cpld.c | 26 ++++++++++++++++++++++++-- board/freescale/ls1043ardb/cpld.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-)
Applied to u-boot-fsl-qoriq master, awaiting upstream.
Thanks.
York
participants (4)
-
Gong Qianyu -
Mingkai Hu -
Qianyu Gong
-
York Sun