[U-Boot] PPC405EX CHIP_21 erratum
We've been bitten by the PPC405EX CHIP_21 erratum. I've looked through the U-Boot code, but it doesn't appear that there is a work-around for this one.
The following patch is my adaptation of AMCC's suggestion as to the fix. But I have to say that I don't care for it, if for no other reason that it will break if a rev E comes out.
Also, I made it #ifdef'd on CONFIG_405EX, but it will not work on a 405EXr. And I have seen a 405EX report its PVR as if it were a 405EXr. It's not looking good for the suggested work-around.
AMCC claims this can be fixed in hardware, by always doing a double reset. Naturally, that is hard to implement and would mean massive rework of existing boards.
So I am contemplating a different work-around, whereby software always resets the board on a cold boot (if such a thing can be reliably detected). That would hopefully be the equivalent of the hardware double reset, and would not be dependent on specific PVR values, making it more "future proof".
Has anyone else run across this? Do you have similar concerns about the patch?
Patch below is for discussion only. Do not apply.
Signed-off-by: Steve Falco sfalco@harris.com
---
--- /home/sfalco/start.S.orig 2011-04-29 12:38:20.000000000 -0400 +++ arch/powerpc/cpu/ppc4xx/start.S 2011-04-29 12:38:49.000000000 -0400 @@ -1184,6 +1184,31 @@ #else GET_GOT /* initialize GOT access */
+#ifdef CONFIG_405EX +/* Errata CHIP_21 */ + mfspr r3, PVR + lis r0,0x1291 + ori r0,r0,0x1475 + cmpw r0,r3,r0 + beq r0,..GoodPVR /*Is it a 405EX REV D with security? */ + lis r0,0x1291 + ori r0,r0,0x1473 + cmpw r0,r3,r0 + beq r0,..GoodPVR /*Is it a 405EX REV D with without security? */ + lis r0,0x1291 + ori r0,r0,0x147F + cmpw r0,r3,r0 + beq r0,..GoodPVR /*Is it a 405EX REV C with security? */ + lis r0,0x1291 + ori r0,r0,0x147D + cmpw r0,r3,r0 + beq r0,..GoodPVR /*Is it a 405EX REV C with without security? */ + lis r3,0x3000 /*DBCR0[RST]=0b11 */ + ori r3,r3,0x0000 + mtspr SPRN_DBCR0,r3 +..GoodPVR: +#endif + bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f /* run first part of init code (from Flash) */
Hi Steve,
On Friday 29 April 2011 18:54:02 Steven A. Falco wrote:
We've been bitten by the PPC405EX CHIP_21 erratum.
How did it affect you exactly? Was an incorrect PVR detected? Did this result in some problems (Linux etc)?
I've looked through the U-Boot code, but it doesn't appear that there is a work-around for this one.
Correct, there currently is no workaround.
The following patch is my adaptation of AMCC's suggestion as to the fix. But I have to say that I don't care for it, if for no other reason that it will break if a rev E comes out.
Also, I made it #ifdef'd on CONFIG_405EX, but it will not work on a 405EXr. And I have seen a 405EX report its PVR as if it were a 405EXr. It's not looking good for the suggested work-around.
AMCC claims this can be fixed in hardware, by always doing a double reset. Naturally, that is hard to implement and would mean massive rework of existing boards.
Yes, there are many 405EX(r) boards in the field already. Such an hardware workaround should really be avoided if possible.
So I am contemplating a different work-around, whereby software always resets the board on a cold boot (if such a thing can be reliably detected). That would hopefully be the equivalent of the hardware double reset, and would not be dependent on specific PVR values, making it more "future proof".
Has anyone else run across this? Do you have similar concerns about the patch?
No, I have not seen this problem before. And yes, I would also prefer your "alternative suggestion", with the always reboot after powerup optionally built into the U-Boot image. But as you already mentioned, we would have to find a way to reliably detect the powerup reset, so that we don't end in an reset-loop.
Cheers, Stefan
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participants (2)
-
Stefan Roese -
Steven A. Falco