Signed-off-by: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com --- drivers/serial/serial_sh.c | 3 ++- include/asm-sh/cpu_sh2.h | 4 ++++ include/asm-sh/cpu_sh7203.h | 41 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletions(-) create mode 100644 include/asm-sh/cpu_sh7203.h

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 0801ac4..4ea117c 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -72,7 +72,8 @@ # endif #elif defined(CONFIG_CPU_SH7750) || \ defined(CONFIG_CPU_SH7751) || \ - defined(CONFIG_CPU_SH7722) + defined(CONFIG_CPU_SH7722) || \ + defined(CONFIG_CPU_SH7203) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) # define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 diff --git a/include/asm-sh/cpu_sh2.h b/include/asm-sh/cpu_sh2.h index d776cb9..7d8f92a 100644 --- a/include/asm-sh/cpu_sh2.h +++ b/include/asm-sh/cpu_sh2.h @@ -31,6 +31,10 @@ #define CACHE_OC_NUM_ENTRIES 256 #define CACHE_OC_ENTRY_SHIFT 4

+#if defined(CONFIG_CPU_SH7203) +# include <asm/cpu_sh7203.h> +#else # error "Unknown SH2 variant" +#endif

#endif /* _ASM_CPU_SH2_H_ */ diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h new file mode 100644 index 0000000..77dcac4 --- /dev/null +++ b/include/asm-sh/cpu_sh7203.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CPU_SH7203_H_ +#define _ASM_CPU_SH7203_H_ + +/* Cache */ +#define CCR1 0xFFFC1000 +#define CCR CCR1 + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ + +/* SDRAM controller */ + +/* SCIF */ +#define SCSMR_0 0xFFFE8000 +#define SCIF0_BASE SCSMR_0 + +/* Timer(CMT) */ +#define CMSTR 0xFFFEC000 +#define CMCSR_0 0xFFFEC002 +#define CMCNT_0 0xFFFEC004 +#define CMCOR_0 0xFFFEC006 +#define CMCSR_1 0xFFFEC008 +#define CMCNT_1 0xFFFEC00A +#define CMCOR_1 0xFFFEC00C + +/* On chip oscillator circuits */ +#define FRQCR 0xA415FF80 +#define WTCNT 0xA415FF84 +#define WTCSR 0xA415FF86 + +#endif /* _ASM_CPU_SH7203_H_ */