[U-Boot-Users] Missing 440GX SDRAM Controller reset?
I have this same problem described a few months ago and corrected by adding the SDRAM controller reset present in the PIBS code but missing in rev 1.1.1 of u-boot e.g:
mtsdr(sdr_srst, 0x00200000); mtsdr(sdr_srst, 0x00000000);
Was this left out on purpose? It seems like if the BDI configuration can cause a hang then a warm-reboot is going to be problematic too??
Re: problems with BDI2000 / u-boot / Linux on IBM 440GX Ocotea
reference board
The first problem is if I try to run u-boot from flash with a
BDI2000
connected (i.e. do "reset" and "go" commands), then u-boot starts running but hangs in the SDRAM init. Specifically, it hangs waiting for the MRS Command Complete status bit to be set.
IIRC I ran into the same thing, all I needed to do was remove the
sdram
configuration from the config for the BDI.
On Tue, 2004-10-26 at 16:29, David Adair wrote:
I have this same problem described a few months ago and corrected by adding the SDRAM controller reset present in the PIBS code but missing in rev 1.1.1 of u-boot e.g:
mtsdr(sdr_srst, 0x00200000); mtsdr(sdr_srst, 0x00000000);Was this left out on purpose? It seems like if the BDI configuration can cause a hang then a warm-reboot is going to be problematic too??
Hmmm... Must've been an oversight on my part. I'm running 3 different 440GX boards (Ocotea included) w/o problem.
However, for completeness sake, please submit a patch.
Thanx
Travis Sawyer
This patch allows the SDRAM initialization to succeed even with the default out of box BDI2000 settings. I suspect but have not proven that it will also make warm-reboot operation more reliable.
diff -ru u-boot-1.1.1/cpu/ppc4xx/spd_sdram.c u-boot-1.1.1-mod2/cpu/ppc4xx/spd_sdram.c --- u-boot-1.1.1/cpu/ppc4xx/spd_sdram.c 2003-12-09 06:56:24.000000000 -0800 +++ u-boot-1.1.1-mod2/cpu/ppc4xx/spd_sdram.c 2004-10-27 10:04:02.000000000 -0700 @@ -772,6 +772,14 @@ */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+#if defined(CONFIG_440_GX) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(sdr_srst, SDR0_SRST_DMC); + mtsdr(sdr_srst, 0x00000000); +#endif + /* * program 440GP SDRAM controller options (SDRAM0_CFG0) */ diff -ru u-boot-1.1.1/include/ppc440.h u-boot-1.1.1-mod2/include/ppc440.h --- u-boot-1.1.1/include/ppc440.h 2004-03-13 16:07:34.000000000 -0800 +++ u-boot-1.1.1-mod2/include/ppc440.h 2004-10-27 10:02:36.000000000 -0700 @@ -893,6 +893,38 @@ #define SDR0_MFR_ECS_MASK 0x10000000 #define SDR0_MFR_ECS_INTERNAL 0x10000000
+#define SDR0_SRST_BGO 0x80000000 +#define SDR0_SRST_PLB 0x40000000 +#define SDR0_SRST_EBC 0x20000000 +#define SDR0_SRST_OPB 0x10000000 +#define SDR0_SRST_UART0 0x08000000 +#define SDR0_SRST_UART1 0x04000000 +#define SDR0_SRST_IIC0 0x02000000 +#define SDR0_SRST_IIC1 0x01000000 +#define SDR0_SRST_GPIO 0x00800000 +#define SDR0_SRST_GPT 0x00400000 +#define SDR0_SRST_DMC 0x00200000 +#define SDR0_SRST_PCI 0x00100000 +#define SDR0_SRST_EMAC0 0x00080000 +#define SDR0_SRST_EMAC1 0x00040000 +#define SDR0_SRST_CPM 0x00020000 +#define SDR0_SRST_IMU 0x00010000 +#define SDR0_SRST_UIC01 0x00008000 +#define SDR0_SRST_UICB2 0x00004000 +#define SDR0_SRST_SRAM 0x00002000 +#define SDR0_SRST_EBM 0x00001000 +#define SDR0_SRST_BGI 0x00000800 +#define SDR0_SRST_DMA 0x00000400 +#define SDR0_SRST_DMAC 0x00000200 +#define SDR0_SRST_MAL 0x00000100 +#define SDR0_SRST_ZMII 0x00000080 +#define SDR0_SRST_GPTR 0x00000040 +#define SDR0_SRST_PPM 0x00000020 +#define SDR0_SRST_EMAC2 0x00000010 +#define SDR0_SRST_EMAC3 0x00000008 +#define SDR0_SRST_RGMII 0x00000001 + +
/*-------------------------------------------------------------------------- ---+ | Clocking
+--------------------------------------------------------------------------- --*/
Disclaimer: I have problems running MAKEALL for a few platforms that I believe to be unrelated to my change (e.g. they also happen without the patch)
Configuring for AR405 board... ppc_4xx-ld: u-boot: Not enough room for program headers (allocated 2, need 3) ppc_4xx-ld: final link failed: Bad value make: *** [u-boot] Error 1 ppc_4xx-size: u-boot: No such file or directory
On Tue, 2004-10-26 at 16:29, David Adair wrote:
I have this same problem described a few months ago and
corrected by
adding the SDRAM controller reset present in the PIBS code
but missing
in rev 1.1.1 of u-boot e.g:
mtsdr(sdr_srst, 0x00200000); mtsdr(sdr_srst, 0x00000000);Was this left out on purpose? It seems like if the BDI
configuration
can cause a hang then a warm-reboot is going to be problematic too??
Hmmm... Must've been an oversight on my part. I'm running 3 different 440GX boards (Ocotea included) w/o problem.
However, for completeness sake, please submit a patch.
Thanx
Travis Sawyer
In message ORIONnRMWuLn5U9T3TG0000008e@orion.ariodata.com you wrote:
This patch allows the SDRAM initialization to succeed even with the default out of box BDI2000 settings. I suspect but have not proven that it will also make warm-reboot operation more reliable.
Added, thanks.
Best regards,
Wolfgang Denk
participants (3)
-
David Adair -
Travis Sawyer -
Wolfgang Denk