Attached is a patch to update the support for the AMCC Yosemite board. It does the following.

1. Enable the PCI interrupt. I submitted a patch previously that did this same thing. 2. Disable the FLASH write protect in the board control and status registers. 3. Added a function to dynamically figure a value for the SDRAM0_TR1[RDCT]. This value needs to be adjusted on each boot and any 440 designs with DDR should do this.