[U-Boot] [PATCH v2] rtl8169: fix cache misalignment message on transmit.

The call to flush cache on the transmit buffer was misplaced (for very short packets) and asked to flush less than a cacheline.
Move the flush cache call to after a short packet has been padded to minimum length (so the padding is flushed too), and round the size up to a cacheline.
Signed-off-by: Peter Chubb peter.chubb@data61.csiro.au Acked-by: Joe Hershberger joe.hershberger@ni.com --- drivers/net/rtl8169.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40..a3f4423 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -629,11 +629,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - rtl_flush_buffer(ptxb, length);
while (len < ETH_ZLEN) ptxb[len++] = '\0';
+ rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); + tpc->TxDescArray[entry].buf_Haddr = 0; #ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32(

2016-09-14 3:29 GMT+02:00 Peter.Chubb@data61.csiro.au:
The call to flush cache on the transmit buffer was misplaced (for very short packets) and asked to flush less than a cacheline.
Move the flush cache call to after a short packet has been padded to minimum length (so the padding is flushed too), and round the size up to a cacheline.
Signed-off-by: Peter Chubb peter.chubb@data61.csiro.au Acked-by: Joe Hershberger joe.hershberger@ni.com
drivers/net/rtl8169.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Tested-by Nicolas Chauvet kwizart@gmail.com
This fix the following message on trimslice with 2016.09: --- BOOTP broadcast 1 CACHE: Misaligned operation at range [3ffba600, 3ffba756] ---
Thx

participants (3)
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Joe Hershberger
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Nicolas Chauvet
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Peter.Chubb@data61.csiro.au