Hi,

On 04/07/2024 08:50, Minda Chen wrote:

...

USB PHY maybe need to set PHY mode in different USB dr mode. So translate to generic PHY mode and call generic_phy_set_mode().

Signed-off-by: Minda Chen minda.chen@starfivetech.com

drivers/usb/cdns3/core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)

diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 12a741c6ea..1e863bed89 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -107,6 +107,7 @@ static int cdns3_core_init_role(struct cdns3 *cdns) { struct udevice *dev = cdns->dev; enum usb_dr_mode best_dr_mode;

• int mode = PHY_MODE_INVALID; enum usb_dr_mode dr_mode; int ret = 0;

@@ -173,6 +174,30 @@ static int cdns3_core_init_role(struct cdns3 *cdns)

cdns->dr_mode = dr_mode;

• if (cdns->dr_mode == USB_DR_MODE_HOST) {

• mode = PHY_MODE_USB_HOST;
  

• } else if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) {

• mode = PHY_MODE_USB_DEVICE;
  

• } else if (cdns->dr_mode == USB_DR_MODE_OTG) {

• mode = PHY_MODE_USB_OTG;
  

• } else {

• dev_err(dev, "Unknown dr mode %d\n", cdns->dr_mode);
  

• ret = -EINVAL;
  

• goto err;
  

• }
• ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
• if (ret) {

• dev_err(dev, "Set usb 2.0 PHY mode failed %d\n", ret);
  

• goto err;
  

• }
• ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
• if (ret) {

• dev_err(dev, "Set usb 3.0 PHY mode failed %d\n", ret);
  

• goto err;
  

• }

Should we be doing the above inside cdns3_drd_update_mode() so that the PHY can be put in the correct state even during role switches?

OK， Thanks.

...

ret = cdns3_drd_update_mode(cdns); if (ret) goto err;

-- cheers, -roger

On 04/07/2024 08:50, Minda Chen wrote:

Add Starfive JH7110 USB 2.0 PHY driver, which is generic PHY driver.

Signed-off-by: Minda Chen minda.chen@starfivetech.com

drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 14 +++ drivers/phy/starfive/Makefile | 6 ++ drivers/phy/starfive/phy-jh7110-usb2.c | 135 +++++++++++++++++++++++++ 5 files changed, 157 insertions(+) create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8f767877e7..0c4d63a01f 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -307,5 +307,6 @@ source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" source "drivers/phy/qcom/Kconfig" source "drivers/phy/renesas/Kconfig" +source "drivers/phy/starfive/Kconfig"

endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 7a2b764492..6ac867350c 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -44,3 +44,4 @@ obj-y += cadence/ obj-y += ti/ obj-y += qcom/ obj-y += renesas/ +obj-y += starfive/ diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig new file mode 100644 index 0000000000..11a819f8b2 --- /dev/null +++ b/drivers/phy/starfive/Kconfig @@ -0,0 +1,14 @@ +# +# Phy drivers for Starfive platforms

PHY?

+#

+menu "Starfive PHY driver"

+config PHY_STARFIVE_JH7110_USB2

• bool "Starfive JH7110 USB 2.0 PHY driver"
• select PHY
• help

•  Enable this to support the Starfive JH7110 USB 2.0 PHY.
  

•  Generic PHY driver JH7110 USB 2.0.
  

+endmenu diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile new file mode 100644 index 0000000000..a405a75e34 --- /dev/null +++ b/drivers/phy/starfive/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Starfive +#

+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c new file mode 100644 index 0000000000..d48c9f8a74 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-usb2.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • StarFive JH7110 USB 2.0 PHY driver
• • Copyright (C) 2024 StarFive Technology Co., Ltd.
• • Author: Minda Chen minda.chen@starfivetech.com
• */

+#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <soc.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h>

+#define USB_LS_KEEPALIVE_OFF 0x4 +#define USB_LS_KEEPALIVE_ENABLE BIT(4) +#define USB_PHY_CLK_RATE 125000000

+struct jh7110_usb2_phy {

• struct phy *phy;
• void __iomem *regs;
• struct clk *usb_125m_clk;
• struct clk *app_125m;
• enum phy_mode mode;

+};

+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) +{

• /* Host mode enable the LS speed keep-alive signal */
• if (set)

• clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
  

• 		USB_LS_KEEPALIVE_ENABLE,
  

• 		USB_LS_KEEPALIVE_ENABLE);
  

• else

• clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
  

• 		USB_LS_KEEPALIVE_ENABLE, 0);
  

+}

+static int usb2_phy_set_mode(struct phy *_phy,

• 	     enum phy_mode mode, int submode)
  

+{

• struct udevice *dev = _phy->dev;
• struct jh7110_usb2_phy *phy = dev_get_priv(dev);
• if (mode == phy->mode)

• return 0;
  

• switch (mode) {
• case PHY_MODE_USB_HOST:
• case PHY_MODE_USB_DEVICE:
• case PHY_MODE_USB_OTG:

• dev_dbg(dev, "Changing phy to %d\n", mode);
  

• phy->mode = mode;
  

• usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
  

• break;
  

• default:

• return -EINVAL;
  

• }
• return 0;

+}

+static int jh7110_usb2_phy_init(struct phy *_phy) +{

• struct udevice *dev = _phy->dev;
• struct jh7110_usb2_phy *phy = dev_get_priv(dev);
• int ret;
• ret = clk_set_rate(phy->usb_125m_clk, USB_PHY_CLK_RATE);
• if (ret < 0) {

• dev_err(dev, "Failed to set 125m clock\n");
  

• return ret;
  

• }
• return clk_prepare_enable(phy->app_125m);

+}

+static int jh7110_usb2_phy_exit(struct phy *_phy) +{

• struct udevice *dev = _phy->dev;
• struct jh7110_usb2_phy *phy = dev_get_priv(dev);
• clk_disable_unprepare(phy->app_125m);
• return 0;

+}

+struct phy_ops jh7110_usb2_phy_ops = {

• .init = jh7110_usb2_phy_init,
• .exit = jh7110_usb2_phy_exit,
• .set_mode = usb2_phy_set_mode,

+};

+int jh7110_usb2_phy_probe(struct udevice *dev) +{

• struct jh7110_usb2_phy *phy = dev_get_priv(dev);
• phy->regs = dev_read_addr_ptr(dev);
• if (!phy->regs)

• return -EINVAL;
  

• phy->usb_125m_clk = devm_clk_get(dev, "125m");
• if (IS_ERR(phy->usb_125m_clk)) {

• dev_err(dev, "Failed to get 125m clock\n");
  

• return PTR_ERR(phy->usb_125m_clk);
  

• }
• phy->app_125m = devm_clk_get(dev, "app_125m");
• if (IS_ERR(phy->app_125m)) {

• dev_err(dev, "Failed to get app 125m clock\n");
  

• return PTR_ERR(phy->app_125m);
  

• }
• return 0;

+}

+static const struct udevice_id jh7110_usb2_phy[] = {

• { .compatible = "starfive,jh7110-usb-phy"},
• {},

+};

+U_BOOT_DRIVER(jh7110_usb2_phy) = {

• .name = "jh7110_usb2_phy",
• .id = UCLASS_PHY,
• .of_match = jh7110_usb2_phy,
• .probe = jh7110_usb2_phy_probe,
• .ops = &jh7110_usb2_phy_ops,
• .priv_auto = sizeof(struct jh7110_usb2_phy),

how about space instead of tab?

+};

Reviewed-by: Roger Quadros rogerq@kernel.org

On 04/07/2024 08:50, Minda Chen wrote:

Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic PHY driver and can be used as USB 3.0 driver.

Signed-off-by: Minda Chen minda.chen@starfivetech.com

drivers/phy/starfive/Kconfig | 7 + drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-pcie.c | 202 +++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c

diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index 11a819f8b2..5d49684bc7 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -4,6 +4,13 @@

menu "Starfive PHY driver"

+config PHY_STARFIVE_JH7110_PCIE

•    bool "Starfive JH7110 PCIe 2.0 PHY driver"
  

•    select PHY
  

•    help
  

•      Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
  

•  Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
  

Should be aligned to previous line.

config PHY_STARFIVE_JH7110_USB2 bool "Starfive JH7110 USB 2.0 PHY driver" select PHY diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index a405a75e34..82f25aa21b 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2023 Starfive #

+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c new file mode 100644 index 0000000000..57d5d8bf53 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-pcie.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • StarFive JH7110 PCIe 2.0 PHY driver
• • Copyright (C) 2024 StarFive Technology Co., Ltd.
• • Author: Minda Chen minda.chen@starfivetech.com
• */

+#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <soc.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h>

+#define PCIE_KVCO_LEVEL_OFF 0x28 +#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c +#define PCIE_USB3_PHY_SS_MODE BIT(4)

extra tab?

+#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 +#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc

+#define USB_PDRSTN_SPLIT BIT(17)

+#define PCIE_USB3_PHY_MODE BIT(20) +#define PCIE_PHY_MODE_MASK GENMASK(21, 20) +#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) +#define PCIE_BUS_WIDTH BIT(3) +#define PCIE_USB3_RATE_MASK GENMASK(6, 5) +#define PCIE_USB3_RX_STANDBY_MASK BIT(7) +#define PCIE_USB3_PHY_ENABLE BIT(4)

Why not use define and use regmap_fields? You are already using regmap.

+struct jh7110_pcie_phy {

• struct phy *phy;
• struct regmap *stg_syscon;
• struct regmap *sys_syscon;
• void __iomem *regs;
• u32 sys_phy_connect;
• u32 stg_pcie_mode;
• u32 stg_pcie_usb;
• enum phy_mode mode;

+};

+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode) +{

• unsigned int phy_mode, width, usb3_phy, ss_mode;
• /* default is PCIe mode */
• if (!data->stg_syscon || !data->sys_syscon) {

• if (usb_mode) {
  

• 	dev_err(data->phy->dev, "doesn't support usb3 mode\n");
  

• 	return -EINVAL;
  

• }
  

• return 0;
  

• }
• if (usb_mode) {

• phy_mode = PCIE_USB3_PHY_MODE;
  

• width = 0;
  

• usb3_phy = PCIE_USB3_PHY_ENABLE;
  

• ss_mode = PCIE_USB3_PHY_SS_MODE;
  

• } else {

• phy_mode = 0;
  

• width = PCIE_BUS_WIDTH;
  

• usb3_phy = 0;
  

• ss_mode = 0;
  

• }
• regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,

• 	   PCIE_PHY_MODE_MASK, phy_mode);
  

• regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,

• 	   PCIE_USB3_BUS_WIDTH_MASK, width);
  

• regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,

• 	   PCIE_USB3_PHY_ENABLE, usb3_phy);
  

• clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,

• 	PCIE_USB3_PHY_SS_MODE, ss_mode);
  

• regmap_update_bits(data->sys_syscon, data->sys_phy_connect,

• 	   USB_PDRSTN_SPLIT, 0);
  

• return 0;

+}

+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) +{

• /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
• writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
• writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);

+}

+static int jh7110_pcie_phy_set_mode(struct phy *_phy,

• 		    enum phy_mode mode, int submode)
  

+{

• struct udevice *dev = _phy->dev;
• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• int ret;
• if (mode == phy->mode)

• return 0;
  

• switch (mode) {
• case PHY_MODE_USB_HOST:
• case PHY_MODE_USB_DEVICE:
• case PHY_MODE_USB_OTG:

• ret = phy_pcie_mode_set(phy, 1);
  

• if (ret)
  

• 	return ret;
  

• break;
  

• case PHY_MODE_PCIE:

• phy_pcie_mode_set(phy, 0);
  

• break;
  

• default:

• return -EINVAL;
  

• }
• dev_dbg(_phy->dev, "Changing phy mode to %d\n", mode);
• phy->mode = mode;
• return 0;

+}

+static const struct phy_ops jh7110_pcie_phy_ops = {

• .set_mode = jh7110_pcie_phy_set_mode,

+};

+static int starfive_pcie_phy_get_syscon(struct udevice *dev) +{

• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• struct ofnode_phandle_args sys_phandle, stg_phandle;
• int ret;
• /* get corresponding syscon phandle */
• ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,

• 			 &sys_phandle);
  

• if (ret < 0) {

• dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
  

• return ret;
  

• }
• ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,

• 			 &stg_phandle);
  

• if (ret < 0) {

• dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
  

• return ret;
  

• }
• phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
• if (!IS_ERR_OR_NULL(phy->sys_syscon)) {

• /* get syscon register offset */
  

• phy->sys_phy_connect = sys_phandle.args[0];
  

• } else {

• phy->sys_syscon = NULL;
  

Why not error out if you could not get the sys_syscon regmap?

• }
• phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
• if (!IS_ERR_OR_NULL(phy->stg_syscon)) {

• phy->stg_pcie_mode = stg_phandle.args[0];
  

• phy->stg_pcie_usb = stg_phandle.args[1];
  

• } else {

• phy->stg_syscon = NULL;
  

same here?

• }
• return 0;

+}

+int jh7110_pcie_phy_probe(struct udevice *dev) +{

• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• int rc;
• phy->regs = dev_read_addr_ptr(dev);
• if (!phy->regs)

• return -EINVAL;
  

• rc = starfive_pcie_phy_get_syscon(dev);
• if (rc)

• return rc;
  

• phy_kvco_gain_set(phy);
• return 0;

+}

+static const struct udevice_id jh7110_pcie_phy[] = {

• { .compatible = "starfive,jh7110-pcie-phy"},
• {},

+};

+U_BOOT_DRIVER(jh7110_pcie_phy) = {

• .name = "jh7110_pcie_phy",
• .id = UCLASS_PHY,
• .of_match = jh7110_pcie_phy,
• .probe = jh7110_pcie_phy_probe,
• .ops = &jh7110_pcie_phy_ops,
• .priv_auto = sizeof(struct jh7110_pcie_phy),

need space instead of tab?

+};

On 04/07/2024 08:50, Minda Chen wrote:

Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic PHY driver and can be used as USB 3.0 driver.

Signed-off-by: Minda Chen minda.chen@starfivetech.com

drivers/phy/starfive/Kconfig | 7 + drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-pcie.c | 202 +++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c

diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index 11a819f8b2..5d49684bc7 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -4,6 +4,13 @@

menu "Starfive PHY driver"

+config PHY_STARFIVE_JH7110_PCIE

•    bool "Starfive JH7110 PCIe 2.0 PHY driver"
  

•    select PHY
  

•    help
  

•      Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
  

•  Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
  

config PHY_STARFIVE_JH7110_USB2 bool "Starfive JH7110 USB 2.0 PHY driver" select PHY diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index a405a75e34..82f25aa21b 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2023 Starfive #

+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c new file mode 100644 index 0000000000..57d5d8bf53 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-pcie.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • StarFive JH7110 PCIe 2.0 PHY driver
• • Copyright (C) 2024 StarFive Technology Co., Ltd.
• • Author: Minda Chen minda.chen@starfivetech.com
• */

+#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <soc.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h>

+#define PCIE_KVCO_LEVEL_OFF 0x28 +#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c +#define PCIE_USB3_PHY_SS_MODE BIT(4) +#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 +#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc

+#define USB_PDRSTN_SPLIT BIT(17)

+#define PCIE_USB3_PHY_MODE BIT(20) +#define PCIE_PHY_MODE_MASK GENMASK(21, 20) +#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) +#define PCIE_BUS_WIDTH BIT(3) +#define PCIE_USB3_RATE_MASK GENMASK(6, 5) +#define PCIE_USB3_RX_STANDBY_MASK BIT(7) +#define PCIE_USB3_PHY_ENABLE BIT(4)

+struct jh7110_pcie_phy {

• struct phy *phy;
• struct regmap *stg_syscon;
• struct regmap *sys_syscon;
• void __iomem *regs;
• u32 sys_phy_connect;
• u32 stg_pcie_mode;
• u32 stg_pcie_usb;
• enum phy_mode mode;

+};

+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode) +{

• unsigned int phy_mode, width, usb3_phy, ss_mode;
• /* default is PCIe mode */
• if (!data->stg_syscon || !data->sys_syscon) {

• if (usb_mode) {
  

• 	dev_err(data->phy->dev, "doesn't support usb3 mode\n");
  

• 	return -EINVAL;
  

• }
  

• return 0;
  

• }
• if (usb_mode) {

• phy_mode = PCIE_USB3_PHY_MODE;
  

• width = 0;
  

• usb3_phy = PCIE_USB3_PHY_ENABLE;
  

• ss_mode = PCIE_USB3_PHY_SS_MODE;
  

• } else {

• phy_mode = 0;
  

• width = PCIE_BUS_WIDTH;
  

• usb3_phy = 0;
  

• ss_mode = 0;
  

• }
• regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,

• 	   PCIE_PHY_MODE_MASK, phy_mode);
  

• regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,

• 	   PCIE_USB3_BUS_WIDTH_MASK, width);
  

• regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,

• 	   PCIE_USB3_PHY_ENABLE, usb3_phy);
  

• clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,

• 	PCIE_USB3_PHY_SS_MODE, ss_mode);
  

• regmap_update_bits(data->sys_syscon, data->sys_phy_connect,

• 	   USB_PDRSTN_SPLIT, 0);
  

• return 0;

+}

+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) +{

• /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
• writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
• writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);

+}

+static int jh7110_pcie_phy_set_mode(struct phy *_phy,

• 		    enum phy_mode mode, int submode)
  

+{

• struct udevice *dev = _phy->dev;
• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• int ret;
• if (mode == phy->mode)

• return 0;
  

• switch (mode) {
• case PHY_MODE_USB_HOST:
• case PHY_MODE_USB_DEVICE:
• case PHY_MODE_USB_OTG:

• ret = phy_pcie_mode_set(phy, 1);
  

• if (ret)
  

• 	return ret;
  

• break;
  

• case PHY_MODE_PCIE:

• phy_pcie_mode_set(phy, 0);
  

• break;
  

• default:

• return -EINVAL;
  

• }
• dev_dbg(_phy->dev, "Changing phy mode to %d\n", mode);
• phy->mode = mode;
• return 0;

+}

+static const struct phy_ops jh7110_pcie_phy_ops = {

• .set_mode = jh7110_pcie_phy_set_mode,

+};

+static int starfive_pcie_phy_get_syscon(struct udevice *dev) +{

• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• struct ofnode_phandle_args sys_phandle, stg_phandle;
• int ret;
• /* get corresponding syscon phandle */
• ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,

• 			 &sys_phandle);
  

• if (ret < 0) {

• dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
  

• return ret;
  

• }
• ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,

• 			 &stg_phandle);
  

• if (ret < 0) {

• dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
  

• return ret;
  

• }
• phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
• if (!IS_ERR_OR_NULL(phy->sys_syscon)) {

• /* get syscon register offset */
  

• phy->sys_phy_connect = sys_phandle.args[0];
  

• } else {

• phy->sys_syscon = NULL;
  

• }
• phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
• if (!IS_ERR_OR_NULL(phy->stg_syscon)) {

• phy->stg_pcie_mode = stg_phandle.args[0];
  

• phy->stg_pcie_usb = stg_phandle.args[1];
  

• } else {

• phy->stg_syscon = NULL;
  

• }
• return 0;

+}

+int jh7110_pcie_phy_probe(struct udevice *dev) +{

• struct jh7110_pcie_phy *phy = dev_get_priv(dev);
• int rc;
• phy->regs = dev_read_addr_ptr(dev);
• if (!phy->regs)

• return -EINVAL;
  

• rc = starfive_pcie_phy_get_syscon(dev);
• if (rc)

• return rc;
  

• phy_kvco_gain_set(phy);
• return 0;

+}

+static const struct udevice_id jh7110_pcie_phy[] = {

• { .compatible = "starfive,jh7110-pcie-phy"},
• {},

+};

+U_BOOT_DRIVER(jh7110_pcie_phy) = {

• .name = "jh7110_pcie_phy",
• .id = UCLASS_PHY,
• .of_match = jh7110_pcie_phy,
• .probe = jh7110_pcie_phy_probe,
• .ops = &jh7110_pcie_phy_ops,
• .priv_auto = sizeof(struct jh7110_pcie_phy),

+};

Please drop the new blank line at the end.

On 04/07/2024 08:50, Minda Chen wrote:

Add cdns USB3 wrapper driver.

Signed-off-by: Minda Chen minda.chen@starfivetech.com

drivers/usb/cdns3/Kconfig | 7 ++ drivers/usb/cdns3/Makefile | 2 + drivers/usb/cdns3/cdns3-starfive.c | 183 +++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 drivers/usb/cdns3/cdns3-starfive.c

diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 35b61497d9..f8f363982b 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -55,4 +55,11 @@ config USB_CDNS3_TI help Say 'Y' here if you are building for Texas Instruments platforms that contain Cadence USB3 controller core. E.g.: J721e.

+config USB_CDNS3_STARFIVE

• tristate "Cadence USB3 support on Starfive platforms"
• default USB_CDNS3
• help

•  Say 'Y' here if you are building for Starfive platforms
  

•  that contain Cadence USB3 controller core. E.g.: JH7110.
  

endif diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 18d7190755..03d1eadb2f 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -9,3 +9,5 @@ cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o

obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o

+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c new file mode 100644 index 0000000000..660833fb5b --- /dev/null +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
• • Copyright (C) 2024 StarFive Technology Co., Ltd.
• • Author: Minda Chen minda.chen@starfivetech.com
• */

+#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/usb/otg.h> +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <malloc.h>

+#include "core.h"

+#define USB_STRAP_HOST BIT(17) +#define USB_STRAP_DEVICE BIT(18) +#define USB_STRAP_MASK GENMASK(18, 16)

+#define USB_SUSPENDM_HOST BIT(19) +#define USB_SUSPENDM_MASK BIT(19)

+#define USB_MISC_CFG_MASK GENMASK(23, 20) +#define USB_SUSPENDM_BYPS BIT(20) +#define USB_PLL_EN BIT(22) +#define USB_REFCLK_MODE BIT(23)

+struct cdns_starfive {

• struct udevice *dev;
• struct regmap *stg_syscon;
• struct reset_ctl_bulk resets;
• struct clk_bulk clks;
• u32 stg_usb_mode;
• enum usb_dr_mode mode;

+};

+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode) +{

• unsigned int strap, suspendm;
• regmap_update_bits(data->stg_syscon, data->stg_usb_mode,

• 	   USB_MISC_CFG_MASK,
  

• 	   USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
  

• switch (mode) {
• case USB_DR_MODE_HOST:

• strap = USB_STRAP_HOST;
  

• suspendm = USB_SUSPENDM_HOST;
  

• break;
  

• case USB_DR_MODE_PERIPHERAL:

• strap = USB_STRAP_DEVICE;
  

• suspendm = 0;
  

• break;
  

• default:

• return;
  

• }
• regmap_update_bits(data->stg_syscon, data->stg_usb_mode,

• 	   USB_STRAP_MASK, strap);
  

• regmap_update_bits(data->stg_syscon, data->stg_usb_mode,

• 	   USB_SUSPENDM_MASK, suspendm);
  

+}

+static void cdns_clk_rst_deinit(struct cdns_starfive *data) +{

• reset_assert_bulk(&data->resets);
• clk_disable_bulk(&data->clks);

+}

+static int cdns_clk_rst_init(struct cdns_starfive *data) +{

• int ret;
• ret = clk_get_bulk(data->dev, &data->clks);
• if (ret)

• return ret;
  

• ret = reset_get_bulk(data->dev, &data->resets);
• if (ret)

• goto err_clk;
  

• ret = clk_enable_bulk(&data->clks);
• if (ret)

• goto err_en_clk;
  

• ret = reset_deassert_bulk(&data->resets);
• if (ret)

• goto err_reset;
  

• return 0;

+err_reset:

• clk_disable_bulk(&data->clks);

+err_en_clk:

• reset_release_bulk(&data->resets);

+err_clk:

• clk_release_bulk(&data->clks);
• return ret;

+}

+static int cdns_starfive_get_syscon(struct cdns_starfive *data) +{

• struct ofnode_phandle_args phandle;
• int ret;
• ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0,

• 			 &phandle);
  

unnecessary blank line

• if (ret < 0) {

• dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
  

• return ret;
  

• }
• data->stg_syscon = syscon_node_to_regmap(phandle.node);
• if (IS_ERR(data->stg_syscon)) {

• dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon));
  

• return PTR_ERR(data->stg_syscon);
  

• }

Need a new blank line?

• data->stg_usb_mode = phandle.args[0];
• return 0;

+}

+static int cdns_starfive_probe(struct udevice *dev) +{

• struct cdns_starfive *data = dev_get_plat(dev);
• enum usb_dr_mode dr_mode;
• ofnode node;
• int ret;
• data->dev = dev;
• ret = cdns_starfive_get_syscon(data);

unnecessary blank new lines.

• if (ret)

• return ret;
  

• node = ofnode_by_compatible(dev_ofnode(dev), "cdns,usb3");
• if (!ofnode_valid(node)) {

• dev_err(dev, "failed to get usb node\n");
  

• return -ENODEV;
  

• }
• dr_mode = usb_get_dr_mode(node);
• data->mode = dr_mode;
• cdns_mode_init(data, dr_mode);

Don't you need to release reset and enable clock before doing cdns_mode_init()?

• return cdns_clk_rst_init(data);

+}

+static int cdns_starfive_remove(struct udevice *dev) +{

• struct cdns_starfive *data = dev_get_plat(dev);
• cdns_clk_rst_deinit(data);
• return 0;

+}

+static const struct udevice_id cdns_starfive_of_match[] = {

• { .compatible = "starfive,jh7110-usb", },
• {},

+};

+U_BOOT_DRIVER(cdns_starfive) = {

• .name = "cdns-starfive",
• .id = UCLASS_NOP,
• .of_match = cdns_starfive_of_match,
• .bind = cdns3_bind,
• .probe = cdns_starfive_probe,
• .remove = cdns_starfive_remove,
• .plat_auto = sizeof(struct cdns_starfive),
• .flags = DM_FLAG_OS_PREPARE,

+};