[U-Boot] [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support
LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a GPU and LCD controller, as well as TSN-enabled Ethernet ports and a TSN-enabled switch with four external ports. The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a number of industrial and embedded applications. The device provides excellent integration with the new Time-Sensitive Networking standards and enables a number of TSN applications
Features Summary * Two 32/64-bit Arm v8 Cortex-A72 CPUs * Cache coherent interconnect fabric (CCI-400) * 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support * LCD controller and DisplayPort/eDP interface * Graphics processing unit * TSN-capable Ethernet Switch with four external ports * Ethernet Controller (ENETC) with TSN functionality * Four SerDes lanes with two PLLs for high-speed peripheral interfaces * Additional peripheral interfaces * Two high-speed USB 3.0 controllers * Two eSDHC controllers * Two controller area network (FlexCAN) modules * supporting flexible datarate (FD) * Three serial peripheral interface (SPI) controllers * Flexible SPI interface (FlexSPI) controller * Eight I2C controllers * Six LPUARTs * 16550-compliant DUART * General Purpose IO (GPIO) * Eight FlexTimers/PWM controllers * Six asynchronous audio interface (SAI) * Support for hardware virtualization and partitioning enforcement * QorIQ platform's trust architecture 3.0 * Queue direct memory access controller (qDMA) * Enhanced direct memory access controller (eDMA) * Global programmable interrupt controller (GIC) * Arm generic timer * Thermal Monitor Unit (TMU)
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang Yuantian andy.tang@nxp.com --- v2: - fix many issues arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++ arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++++++ arch/arm/dts/fsl-ls1028a.dtsi | 280 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- 11 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..8ecd095 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -20,6 +20,40 @@ config ARCH_LS1012A select SYS_I2C_MXC_I2C2 imply PANIC_HANG
+config ARCH_LS1028A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_FSL_HAS_CCI400 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select FSL_TZASC_1 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A008514 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + imply PANIC_HANG + config ARCH_LS1043A bool select ARMV8_SET_SMPEN @@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1028a-pcie" if ARCH_LS1028A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" + default 2 if ARCH_LS1028A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A @@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 - default 0x3090000 if ARCH_LS1088A + default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A default 0x180000 if FSL_LSCH2 help Offset for CCI400 base @@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ
config SYS_FSL_PCLK_DIV int "Platform clock divider" + default 1 if ARCH_LS1028A default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A default 1 if ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e9bc987..a8d3cf9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -48,3 +48,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif + +ifneq ($(CONFIG_ARCH_LS1028A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b..657d13c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), @@ -246,11 +247,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifndef CONFIG_ARCH_LS1028A { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#endif #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a0e2621..ad55573 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -8,6 +8,7 @@ SoC overview 6. LS2088A 7. LS2081A 8. LX2160A + 9. LS1028A
LS1043A --------- @@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities
2)LX2080A, few difference w.r.t. LX2160A: a) Eight 64-bit ARM v8 Cortex-A72 CPUs + + +LS1028A +-------- +The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with +a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and +a TSNenabled 4-port switch. + +The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, +combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and +Octal/Quad SPI interfaces provide capabilities for a number of industrial and +embedded applications. The device provides excellent integration with the +new Time-Sensitive Networking standard, and enables a number of +TSN applications. + +The LS1028A SoC includes the following function and features: + - Two 64-bit ARM v8 A72 CPUs + - Cache Coherent interconnect (CCI-400) + - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC + - eDP/Displayport interface + - Graphics processing unit + - One Configurable x4 SerDes + - Ethernet interfaces + - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one + ethernet MAC supporting 1G, 100M, 10M. + - Switched: TSN IP to support four 2.5/1G interfaces. + - None of the MACs support MACSEC + - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII + - Support for 10G-SXGMII and 10G-QXGMII. + - Energy efficient Ethernet support (802.3az) + - IEEE 1588 support + - High-speed peripheral interfaces + - Two PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controller + - Additional peripheral interfaces + - Two high-speed USB 2.0/3.0 controllers with integrated PHY each + supporting host or device modes + - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) + - Two Serial peripheral interface (SPI) controllers + - Eight I2C controllers + - Two UART controllers + - Additional six Industrual UARTs (LPUART). + - One FlexSPI controller + - General Purpose IO (GPIO) + - Two CAN-FD interfaces + - Eight Flextimers with PWM I/O + - Support for hardware virtualization and partitioning enforcement + - Layerscape Trust Architecture + - Service Processor (SP) provides pre-boot initialization and secure-boot + capabilities diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c new file mode 100644 index 0000000..f5f264c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; + u8 rcw_lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, + {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, + {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, + {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, + {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, + {0xCC51, {SXGMII1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC3B, {PCIE1, QXGMII2, PCIE2, PCIE2} }, + {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} }, + {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, + {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} }, + {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, + {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} }, + {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} }, + {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} }, + {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} }, + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, + {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, + {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, + {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, + {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, + {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi new file mode 100644 index 0000000..a38c8ce --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028a SOC common device tree source + * + * Copyright 2019 NXP + * + */ + +/ { + compatible = "fsl,ls1028a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + memory@01080000 { + device_type = "memory"; + reg = <0x00000000 0x01080000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + fspi: flexspi@20C0000 { + compatible = "nxp,dn-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20C0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ + reg-names = "FSPI", "FSPI-memory"; + num-cs = <1>; + status = "disabled"; + }; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <0 32 0x1>; /* edge triggered */ + status = "disabled"; + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <0 32 0x1>; /* edge triggered */ + status = "disabled"; + }; + + pcie@3400000 { /* rcie_enetc */ + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + usb1: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; + dr_mode = "host"; + status = "disabled"; + }; + + usb2: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; + dr_mode = "host"; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; + big-endian; + non-removable; + bus-width = <4>; + status = "disabled"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 903d509..eb21c09 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,67 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400 + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define SRDS_MAX_LANES 4 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff..59b224b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,22 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D, + SGMII_T1, + SGMII_T2, + SGMII_T3, + SGMII_T4, + SGMII_S1, + SGMII_S2, + SGMII_S3, + SGMII_S4, + SXGMII1, + SXGMII2, + SXGMII3, + SXGMII4, + QXGMII1, + QXGMII2, + QXGMII3, + QXGMII4, _25GE1, _25GE2, _25GE3, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88a..dbf3215 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -171,6 +171,9 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -375,6 +378,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 #endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 7d95c4e..234440b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index e017d8b..c53cc57 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -87,7 +87,7 @@ #define FSL_PEX_STREAM_ID_NUM (0x100) #endif
-#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18
From: Tang Yuantian andy.tang@nxp.com
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluatoin platform that supports the LS1028A family SoCs. This patch add basic support of the platform.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang Yuantian andy.tang@nxp.com --- v2: - fix many issues arch/arm/Kconfig | 12 ++ arch/arm/cpu/armv8/Kconfig | 1 + arch/arm/dts/fsl-ls1028a-rdb.dts | 92 ++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 2 +- board/freescale/ls1028a/Kconfig | 38 +++++ board/freescale/ls1028a/MAINTAINERS | 10 ++ board/freescale/ls1028a/Makefile | 8 + board/freescale/ls1028a/README | 79 ++++++++++ board/freescale/ls1028a/ddr.c | 284 ++++++++++++++++++++++++++++++++++++ board/freescale/ls1028a/ddr.h | 46 ++++++ board/freescale/ls1028a/ls1028a.c | 194 ++++++++++++++++++++++++ configs/ls1028ardb_tfa_defconfig | 61 ++++++++ include/configs/ls1028a_common.h | 243 ++++++++++++++++++++++++++++++ include/configs/ls1028ardb.h | 82 +++++++++++ 14 files changed, 1151 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts create mode 100644 board/freescale/ls1028a/Kconfig create mode 100644 board/freescale/ls1028a/MAINTAINERS create mode 100644 board/freescale/ls1028a/Makefile create mode 100644 board/freescale/ls1028a/README create mode 100644 board/freescale/ls1028a/ddr.c create mode 100644 board/freescale/ls1028a/ddr.h create mode 100644 board/freescale/ls1028a/ls1028a.c create mode 100644 configs/ls1028ardb_tfa_defconfig create mode 100644 include/configs/ls1028a_common.h create mode 100644 include/configs/ls1028ardb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42ecce..aaaf36a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM development platform that supports the QorIQ LS1012A Layerscape Architecture processor.
+config TARGET_LS1028ARDB + bool "Support ls1028ardb" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS1028ARDB platform + The LS1028A Development System (RDB) is a high-performance + development platform that supports the QorIQ LS1028A + Layerscape Architecture processor. + config TARGET_LS1088ARDB bool "Support ls1088ardb" select ARCH_LS1088A @@ -1585,6 +1596,7 @@ source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" +source "board/freescale/ls1028a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index f053603..a4fa63b 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,6 +104,7 @@ config PSCI_RESET !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ !TARGET_LS1012AFRWY && \ + !TARGET_LS1028ARDB && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts new file mode 100644 index 0000000..e86ba06 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028ARDB device tree source + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "NXP Layerscape 1028a RDB Board"; + compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; +}; + +&dspi0 { + status = "okay"; +}; + +&dspi1 { + status = "okay"; +}; + +&dspi2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&fspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index a38c8ce..31e1aef 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -276,5 +276,5 @@ interrupts = <0 133 4>; clocks = <&clockgen 4 1>; status = "disabled"; - }; + }; }; diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig new file mode 100644 index 0000000..f4733c2 --- /dev/null +++ b/board/freescale/ls1028a/Kconfig @@ -0,0 +1,38 @@ +if TARGET_LS1028ARDB + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028ardb" + +config EMMC_BOOT + bool "Support for booting from EMMC" + default n + +config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +if FSL_LS_PPA +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A + default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA header Addr" + default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A +endif +endif + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS new file mode 100644 index 0000000..135454c --- /dev/null +++ b/board/freescale/ls1028a/MAINTAINERS @@ -0,0 +1,10 @@ +LS1028ARDB BOARD +M: Sudhanshu Gupta sudhanshu.gupta@nxp.com +M: Rai Harninder harninder.rai@nxp.com +M: Rajesh Bhagat rajesh.bhagat@nxp.com +M: Tang Yuantian andy.tang@nxp.com +S: Maintained +F: board/freescale/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028ardb.h +F: configs/ls1028ardb_tfa_defconfig diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile new file mode 100644 index 0000000..9bc144c --- /dev/null +++ b/board/freescale/ls1028a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1028a.o +obj-y += ddr.o diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README new file mode 100644 index 0000000..94a390c --- /dev/null +++ b/board/freescale/ls1028a/README @@ -0,0 +1,79 @@ +Overview +-------- +The LS1028A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports ARM SoC LS1028A and its +derivatives. + +LS1028A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +RDB Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For XSPI NOR boot (default) +SW2: 1111_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For SD Boot +SW2: 1000_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For eMMC Boot +SW2: 1001_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +LS1028ARDB board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Five onboard 1G x8 discrete memory modules (Four data byte lanes + ECC) + - 32-bit data and 4-bit ECC + - One chip select + - Data transfer rates of up to 1.6 GT/s + - Single-bit error correction and double-bit error detection ECC (4-bit + check word across 32-bit data) +High-speed serial ports(SerDes) + - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the + Qualcomm AR8033 PHY + - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected + through the NXP F104S8A PHY + - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3 + (8 Gbit/s) cards + - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B + slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or + SATA Gen 3 cards (6 Gbit/s) at a time +eSDHC + - eSDHC1, eSDHC2 +SPI + - Connects to two mikroBUS sockets to support mikro-click modules, + such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near + field communications (NFC) controller +Octal SPI (XSPI) + - One 256 MB onboard XSPI serial NOR flash memory + - One 512 MB onboard XSPI serial NAND flash memory + - Supports a QSPI emulator for offboard QSPI emulation +I2C + - All system devices are accessed via I2C1, which is multiplexed on + I2C multiplexer PCA9848 to isolate address conflicts and reduce + capacitive load + - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor, + thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules + 1 and 2 +CAN + - The two CAN DB9 ports can support CAN FD fast phase at data rates of + up to 5 Mbit/s +Serial audio interface(SAI) + - Audio codec SGTL5000 provides headphone and audio LINEOUT for + stereo speakers + - IEEE1588 interface to support audio on SAI4 diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c new file mode 100644 index 0000000..63b30d8 --- /dev/null +++ b/board/freescale/ls1028a/ddr.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x46; +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_TARGET_LS1028ARDB +#ifdef CONFIG_SYS_DDR_RAW_TIMING +/* MT40A1G8SA-075:E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 4294967296u, + .capacity = 4294967296u, + .primary_sdram_width = 32, + .ec_sdram_width = 4, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 16, + .n_col_addr = 10, + .bank_addr_bits = 0, + .bank_group_bits = 2, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 750, + .tckmax_ps = 1900, + .caslat_x = 0x0001FFE00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 32000, + .trc_ps = 45500, + .trfc1_ps = 350000, + .trfc2_ps = 260000, + .trfc4_ps = 160000, + .tfaw_ps = 21000, + .trrds_ps = 3000, + .trrdl_ps = 4900, + .tccdl_ps = 5000, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x16, + .dq_mapping[1] = 0x36, + .dq_mapping[2] = 0x16, + .dq_mapping[3] = 0x36, + .dq_mapping[4] = 0x16, + .dq_mapping[5] = 0x36, + .dq_mapping[6] = 0x16, + .dq_mapping[7] = 0x36, + .dq_mapping[8] = 0x16, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 0, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (controller_number == 0 && dimm_number == 0) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#else +static phys_size_t fixed_sdram(void) +{ + size_t ddr_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = 0x000000ff, + .cs[0].config = 0x80040422, + .cs[0].config_2 = 0, + .cs[1].bnds = 0, + .cs[1].config = 0, + .cs[1].config_2 = 0, + + .timing_cfg_3 = 0x01111000, + .timing_cfg_0 = 0xd0550018, + .timing_cfg_1 = 0xFAFC0C42, + .timing_cfg_2 = 0x0048c114, + .ddr_sdram_cfg = 0xe50c000c, + .ddr_sdram_cfg_2 = 0x00401110, + .ddr_sdram_mode = 0x01010230, + .ddr_sdram_mode_2 = 0x0, + + .ddr_sdram_md_cntl = 0x0600001f, + .ddr_sdram_interval = 0x18600618, + .ddr_data_init = 0xdeadbeef, + + .ddr_sdram_clk_cntl = 0x02000000, + .ddr_init_addr = 0, + .ddr_init_ext_addr = 0, + + .timing_cfg_4 = 0x00000002, + .timing_cfg_5 = 0x07401400, + .timing_cfg_6 = 0x0, + .timing_cfg_7 = 0x23300000, + + .ddr_zq_cntl = 0x8A090705, + .ddr_wrlvl_cntl = 0x86550607, + .ddr_sr_cntr = 0, + .ddr_sdram_rcw_1 = 0, + .ddr_sdram_rcw_2 = 0, + .ddr_wrlvl_cntl_2 = 0x0708080A, + .ddr_wrlvl_cntl_3 = 0x0A0B0C09, + + .ddr_sdram_mode_9 = 0x00000400, + .ddr_sdram_mode_10 = 0x04000000, + + .timing_cfg_8 = 0x06115600, + + .dq_map_0 = 0x5b65b658, + .dq_map_1 = 0xd96d8000, + .dq_map_2 = 0, + .dq_map_3 = 0x01600000, + + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x000000C1 + }; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); +#endif + ddr_size = 1ULL << 32; + + return ddr_size; +} +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#endif + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) +#ifdef CONFIG_TARGET_LS1028ARDB + gd->ram_size = 1ULL << 32; +#else + gd->ram_size = fsl_ddr_sdram_size(); +#endif + return 0; +} +#else +int fsl_initdram(void) +{ +#ifdef CONFIG_TARGET_LS1028ARDB +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + gd->ram_size = 1ULL << 32; +#else +#ifdef CONFIG_SYS_DDR_RAW_TIMING + puts("Initializing DDR....\n"); + gd->ram_size = fsl_ddr_sdram(); +#else + puts("Initializing DDR....using fixed timing\n"); + gd->ram_size = fixed_sdram(); +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#endif +#else +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + gd->ram_size = fsl_ddr_sdram(); +#endif +#endif /* !CONFIG_TARGET_LS1028ARDB */ + return 0; +} +#endif /* CONFIG_TFABOOT */ diff --git a/board/freescale/ls1028a/ddr.h b/board/freescale/ls1028a/ddr.h new file mode 100644 index 0000000..aae54e7 --- /dev/null +++ b/board/freescale/ls1028a/ddr.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_TARGET_LS1028ARDB + {1, 1666, 0, 8, 5, 0x06070700, 0x00000008,}, +#else + {2, 1666, 0, 8, 8, 0x090a0b00, 0x0000000c,}, + {1, 1666, 0, 8, 8, 0x090a0b00, 0x0000000c,}, +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c new file mode 100644 index 0000000..853bb92 --- /dev/null +++ b/board/freescale/ls1028a/ls1028a.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <fsl_ddr.h> +#include <asm/io.h> +#include <hwconfig.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/arch-fsl-layerscape/soc.h> +#include <i2c.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif +#include <fsl_immap.h> +#include <netdev.h> + +#include <fdtdec.h> +#include <miiphy.h> +#include "../common/qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + +#ifndef CONFIG_SYS_EARLY_PCI_INIT + /* run PCI init to kick off ENETC */ + pci_init(); +#endif + +#if defined(CONFIG_TARGET_LS1028ARDB) + u8 val = I2C_MUX_CH_DEFAULT; + + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + + fsl_lsch3_early_init_f(); + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + fdt_fixup_memory_banks(blob, base, size, 2); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_QIXIS +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + u8 sw; + + int clock; + char *board; + char buf[64] = {0}; + static const char *freq[6] = {"100.00", "125.00", "156.25", + "161.13", "322.26", "100.00 SS"}; + + cpu_name(buf); + /* find the board details */ + sw = QIXIS_READ(id); + + switch (sw) { + case 0x46: + board = "QDS"; + break; + case 0x47: + board = "RDB"; + break; + case 0x49: + board = "HSSI"; + break; + default: + board = "unknown"; + break; + } + + sw = QIXIS_READ(arch); + printf("Board: %s-%s, Version: %c, boot from ", + buf, board, (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else if (src == BOOT_SOURCE_SD_MMC2) { + puts("eMMC\n"); + } else { +#endif +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif defined(CONFIG_EMMC_BOOT) + puts("eMMC\n"); +#else + switch (sw) { + case 0: + case 4: + printf("NOR\n"); + break; + case 1: + printf("NAND\n"); + break; + default: + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } +#endif +#ifdef CONFIG_TFABOOT + } +#endif + + printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board); + puts("SERDES1 Reference : "); + + sw = QIXIS_READ(brdcfg[2]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 6) & 3; +#else + clock = (sw >> 4) & 0xf; +#endif + + printf("Clock1 = %sMHz ", freq[clock]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 4) & 3; +#else + clock = sw & 0xf; +#endif + printf("Clock2 = %sMHz\n", freq[clock]); + + return 0; +} +#endif diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig new file mode 100644 index 0000000..7a6068d --- /dev/null +++ b/configs/ls1028ardb_tfa_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028ARDB=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h new file mode 100644 index 0000000..c6175a6 --- /dev/null +++ b/include/configs/ls1028a_common.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __L1028A_COMMON_H +#define __L1028A_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_MP + +#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h> + +/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* + * SMP Definitinos + */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* I2C */ +#define CONFIG_SYS_I2C + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=ls1028ardb\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "console=ttyS0,115200\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmcinfo;mmc read $load_addr 0x4800 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmcinfo; mmc dev 1; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 " \ + "&& hdp load $load_addr 0x2000\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define XSPI_NOR_BOOTCOMMAND \ + "run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND \ + "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND \ + "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#elif defined(CONFIG_EMMC_BOOT) +#define CONFIG_BOOTCOMMAND \ + "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND \ + "run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif +#endif /* CONFIG_TFABOOT */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ + +#ifndef CONFIG_CMDLINE_EDITING +#define CONFIG_CMDLINE_EDITING 1 +#endif + +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define OCRAM_NONSECURE_SIZE 0x00010000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else +#if defined(CONFIG_SD_BOOT) || defined(CONFIG_EMMC_BOOT) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define OCRAM_NONSECURE_SIZE 0x00010000 +#else +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#endif /* __L1028A_COMMON_H */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h new file mode 100644 index 0000000..e93288a --- /dev/null +++ b/include/configs/ls1028ardb.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1028A_RDB_H +#define __LS1028A_RDB_H + +#include "ls1028a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* DDR */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Store environment at top of flash */ +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 2 +#define QIXIS_LBMAP_MASK 0xe0 +#define QIXIS_LBMAP_SHIFT 0x5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x00 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_SD 0xf8 +#define QIXIS_RCW_SRC_EMMC 0xf9 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x11 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) +#endif + +/* SATA */ +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 + +#endif /* __LS1028A_RDB_H */
From: Tang Yuantian andy.tang@nxp.com
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang yuantian andy.tang@nxp.com --- v2: - fix many issues arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/dts/fsl-ls1028a-qds.dts | 92 +++++++++++++++++++ board/freescale/ls1028a/Kconfig | 39 ++++++++ board/freescale/ls1028a/MAINTAINERS | 11 +++ board/freescale/ls1028a/README | 85 +++++++++++++++++ board/freescale/ls1028a/ls1028a.c | 38 ++++++++ configs/ls1028aqds_tfa_defconfig | 61 +++++++++++++ include/configs/ls1028aqds.h | 176 ++++++++++++++++++++++++++++++++++++ 9 files changed, 514 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1028a-qds.dts create mode 100644 configs/ls1028aqds_tfa_defconfig create mode 100644 include/configs/ls1028aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aaaf36a..7741ea2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM development platform that supports the QorIQ LS1012A Layerscape Architecture processor.
+config TARGET_LS1028AQDS + bool "Support ls1028aqds" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS1028AQDS platform + The LS1028A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1028A + Layerscape Architecture processor. + config TARGET_LS1028ARDB bool "Support ls1028ardb" select ARCH_LS1028A diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index a4fa63b..3e9d47a 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,7 +104,7 @@ config PSCI_RESET !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ !TARGET_LS1012AFRWY && \ - !TARGET_LS1028ARDB && \ + !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts new file mode 100644 index 0000000..ee8a0c2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028AQDS device tree source + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "NXP Layerscape 1028a QDS Board"; + compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; +}; + +&dspi0 { + status = "okay"; +}; + +&dspi1 { + status = "okay"; +}; + +&dspi2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&fspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig index f4733c2..f8c2fe8 100644 --- a/board/freescale/ls1028a/Kconfig +++ b/board/freescale/ls1028a/Kconfig @@ -1,3 +1,42 @@ +if TARGET_LS1028AQDS + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028aqds" + +config EMMC_BOOT + bool "Support for booting from EMMC" + default n + +config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +if FSL_LS_PPA +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A + default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA header Addr" + default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A +endif +endif + +source "board/freescale/common/Kconfig" + +endif + if TARGET_LS1028ARDB
config SYS_BOARD diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS index 135454c..6f1a95e 100644 --- a/board/freescale/ls1028a/MAINTAINERS +++ b/board/freescale/ls1028a/MAINTAINERS @@ -1,3 +1,14 @@ +LS1028AQDS BOARD +M: Sudhanshu Gupta sudhanshu.gupta@nxp.com +M: Rai Harninder harninder.rai@nxp.com +M: Rajesh Bhagat rajesh.bhagat@nxp.com +M: Tang Yuantian andy.tang@nxp.com +S: Maintained +F: board/freescale/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028aqds.h +F: configs/ls1028aqds_tfa_defconfig + LS1028ARDB BOARD M: Sudhanshu Gupta sudhanshu.gupta@nxp.com M: Rai Harninder harninder.rai@nxp.com diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README index 94a390c..1477705 100644 --- a/board/freescale/ls1028a/README +++ b/board/freescale/ls1028a/README @@ -77,3 +77,88 @@ Serial audio interface(SAI) - Audio codec SGTL5000 provides headphone and audio LINEOUT for stereo speakers - IEEE1588 interface to support audio on SAI4 + +QDS Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For SD Boot +SW1 : 1000_0000 +SW2 : 1110_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0000_0000 +SW6 : 0000_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0001 +SW10: 1110_0000 + +For XSPI Boot +SW1 : 1111_0000 +SW2 : 0000_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0110_0000 +SW6 : 0101_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0000 +SW10: 1110_0000 + +LS1028AQDS board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L + - Supports a single- or dual-ranked SODIMM or UDIMM connector + - 32-bit data and 4-bit ECC + - Supports x8/x16 devices + - Supports ECC error detection and correction + - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to + all devices in case of DDR3L or DDR4, respectively. Power can + switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or + DDR4 devices, respectively +SerDes (Serializer/Deserializer) + - Four-lane (0-3) SerDes: + - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10 + Gbit SXGMII, 1 Gbit SGMII + - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII + - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII + - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, SATA 2.0/3.0 + - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII + add-in cards + - Lane 1 connects to a 2x10 connector with SFP+ through a retimer; + lane 2 (TX lines) connects to an SMA connector + Lane 3 connects to 1x7 header to support SATA devices +eSDHC + - eSDHC1, eSDHC2 +SPI + - SPI1 and SPI2 support three onboard SPI flash memory devices: + 512 Mbit high-speed flash (with speed of up to 108/54 MHz) + memory for storage + 4 Mbit low-speed flash memory (with speed of up to 40 MHz) + 64 Mbit high-speed flash memory (with speed of up to 104/80 + MHz) + - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of + up to 104/80 MHz) + - All memories operate at 1.8 V + - A header is provided on SPI1 to test SPI slave mode +I2C + - LS1028A supports eight I2C controllers +Serial audio interface(SAI) + Two SAI ports with audio codec SGTL5000: + - Include stereo LINEIN with support for external analog input + - Provide headphone and line output +Display + - DisplayPort connector to connect the DP data to a 4K display device + (computer monitor) + - eDP connector to connect the DP data to a 4K display panel diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 853bb92..4697787 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -27,6 +27,35 @@
DECLARE_GLOBAL_DATA_PTR;
+int config_board_mux(void) +{ +#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS) + u8 reg; + + reg = QIXIS_READ(brdcfg[13]); + /* Field| Function + * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): + * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}. + * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): + * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}. + */ + reg &= ~(0xf0); + reg |= 0xb0; + QIXIS_WRITE(brdcfg[13], reg); + + reg = QIXIS_READ(brdcfg[15]); + /* Field| Function + * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY): + * CAN1 | 0= CAN #1 transceiver enabled + * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY): + * CAN2 | 0= CAN #2 transceiver enabled + */ + reg &= ~(0xc0); + QIXIS_WRITE(brdcfg[15], reg); +#endif + return 0; +} + int board_init(void) { #ifdef CONFIG_ENV_IS_NOWHERE @@ -55,6 +84,15 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); }
+#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + config_board_mux(); + + return 0; +} +#endif + int board_early_init_f(void) { #ifdef CONFIG_SYS_I2C_EARLY_INIT diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig new file mode 100644 index 0000000..2a592a0 --- /dev/null +++ b/configs/ls1028aqds_tfa_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028AQDS=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h new file mode 100644 index 0000000..97df1c4 --- /dev/null +++ b/include/configs/ls1028aqds.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1028A_QDS_H +#define __LS1028A_QDS_H + +#include "ls1028a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +/* DDR */ +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 + +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 1 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x00 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_SD 0x8 +#define QIXIS_RCW_SRC_EMMC 0x9 +#define QIXIS_RCW_SRC_QSPI 0xf +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) +#endif + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 1 +#define I2C_MUX_CH_RTC 0xB + +/* Store environment at top of flash */ +#define CONFIG_ENV_SIZE 0x2000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +/* DSPI */ +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif + +#ifndef SPL_NO_ENV +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=ls1028aqds\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "console=ttyS0,115200\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1028aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmcinfo;mmc read $load_addr 0x4800 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmcinfo; mmc dev 1; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 " \ + "&& hdp load $load_addr 0x2000\0" +#endif +#endif /* __LS1028A_QDS_H */
-----Original Message----- From: Yuantian Tang andy.tang@nxp.com Sent: Wednesday, April 3, 2019 12:48 PM To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: albert.u.boot@aribaud.net; Sudhanshu Gupta sudhanshu.gupta@nxp.com; Harninder Rai harninder.rai@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Bhaskar Upadhaya bhaskar.upadhaya@nxp.com; u-boot@lists.denx.de; Andy Tang andy.tang@nxp.com Subject: [PATCH 3/3 v2] armv8: ls1028aqds: Add support of LS1028AQDS
From: Tang Yuantian andy.tang@nxp.com
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang yuantian andy.tang@nxp.com
General comment - avoid FSPI, XSPI related word, configs as no flexspi driver in upstream - avoid enetc related word as no enetc driver in upstream - Avoid #else part of CONFIG_TFABOOT as TFA boot is only supported mechanism, - Remove DDR related code as TFA doing DDR init - generate defconfig using make savedefcofig
Nut shell: Take care of all review comments from RDB patch
--pk
-----Original Message----- From: Yuantian Tang andy.tang@nxp.com Sent: Wednesday, April 3, 2019 12:48 PM To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: albert.u.boot@aribaud.net; Sudhanshu Gupta sudhanshu.gupta@nxp.com; Harninder Rai harninder.rai@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Bhaskar Upadhaya bhaskar.upadhaya@nxp.com; u-boot@lists.denx.de; Andy Tang andy.tang@nxp.com Subject: [PATCH 2/3 v2] armv8: ls1028ardb: Add support for LS1028ARDB platform
From: Tang Yuantian andy.tang@nxp.com
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluatoin platform that supports the LS1028A family SoCs. This patch add basic support of the platform.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang Yuantian andy.tang@nxp.com
v2:
- fix many issues
arch/arm/Kconfig | 12 ++ arch/arm/cpu/armv8/Kconfig | 1 + arch/arm/dts/fsl-ls1028a-rdb.dts | 92 ++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 2 +- board/freescale/ls1028a/Kconfig | 38 +++++ board/freescale/ls1028a/MAINTAINERS | 10 ++ board/freescale/ls1028a/Makefile | 8 + board/freescale/ls1028a/README | 79 ++++++++++ board/freescale/ls1028a/ddr.c | 284 ++++++++++++++++++++++++++++++++++++ board/freescale/ls1028a/ddr.h | 46 ++++++ board/freescale/ls1028a/ls1028a.c | 194 ++++++++++++++++++++++++ configs/ls1028ardb_tfa_defconfig | 61 ++++++++ include/configs/ls1028a_common.h | 243 ++++++++++++++++++++++++++++++ include/configs/ls1028ardb.h | 82 +++++++++++ 14 files changed, 1151 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1028a-rdb.dts create mode 100644 board/freescale/ls1028a/Kconfig create mode 100644 board/freescale/ls1028a/MAINTAINERS create mode 100644 board/freescale/ls1028a/Makefile create mode 100644 board/freescale/ls1028a/README create mode 100644 board/freescale/ls1028a/ddr.c create mode 100644 board/freescale/ls1028a/ddr.h create mode 100644 board/freescale/ls1028a/ls1028a.c create mode 100644 configs/ls1028ardb_tfa_defconfig create mode 100644 include/configs/ls1028a_common.h create mode 100644 include/configs/ls1028ardb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42ecce..aaaf36a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM development platform that supports the QorIQ LS1012A Layerscape Architecture processor.
+config TARGET_LS1028ARDB
- bool "Support ls1028ardb"
- select ARCH_LS1028A
- select ARM64
- select ARMV8_MULTIENTRY
- help
Support for Freescale LS1028ARDB platformThe LS1028A Development System (RDB) is a high-performancedevelopment platform that supports the QorIQ LS1028ALayerscape Architecture processor.config TARGET_LS1088ARDB bool "Support ls1088ardb" select ARCH_LS1088A @@ -1585,6 +1596,7 @@ source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" +source "board/freescale/ls1028a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index f053603..a4fa63b 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,6 +104,7 @@ config PSCI_RESET !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ !TARGET_LS1012AFRWY && \
!TARGET_LS1028ARDB && \git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts new file mode 100644 index 0000000..e86ba06 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP ls1028ARDB device tree source
- Copyright 2019 NXP
- */
+/dts-v1/;
+#include "fsl-ls1028a.dtsi"
+/ {
- model = "NXP Layerscape 1028a RDB Board";
- compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; };
+&dspi0 {
- status = "okay";
+};
+&dspi1 {
- status = "okay";
+};
+&dspi2 {
- status = "okay";
+};
+&esdhc0 {
- status = "okay";
+};
+&esdhc1 {
- status = "okay";
+};
+&fspi {
- status = "okay";
+};
When flexspi driver is not in upstream. Then why fspi status is getting changed to "ok"
+&i2c0 {
- status = "okay";
+};
+&i2c1 {
- status = "okay";
+};
+&i2c2 {
- status = "okay";
+};
+&i2c3 {
- status = "okay";
+};
+&i2c4 {
- status = "okay";
+};
+&i2c5 {
- status = "okay";
+};
+&i2c6 {
- status = "okay";
+};
+&i2c7 {
- status = "okay";
+};
+&sata {
- status = "okay";
+};
+&serial0 {
- status = "okay";
+};
+&serial1 {
- status = "okay";
+};
+&usb1 {
- status = "okay";
+};
+&usb2 {
- status = "okay";
+}; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index a38c8ce..31e1aef 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi
Changes of this file could have been taken in SoC support patch
@@ -276,5 +276,5 @@ interrupts = <0 133 4>; clocks = <&clockgen 4 1>; status = "disabled";
};
- };
}; diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig new file mode 100644 index 0000000..f4733c2 --- /dev/null +++ b/board/freescale/ls1028a/Kconfig @@ -0,0 +1,38 @@ +if TARGET_LS1028ARDB
+config SYS_BOARD
- default "ls1028a"
+config SYS_VENDOR
- default "freescale"
+config SYS_SOC
- default "fsl-layerscape"
+config SYS_CONFIG_NAME
- default "ls1028ardb"
+config EMMC_BOOT
- bool "Support for booting from EMMC"
- default n
+config SYS_TEXT_BASE
- default 0x96000000 if SD_BOOT || EMMC_BOOT
- default 0x82000000 if TFABOOT
- default 0x20100000
+if FSL_LS_PPA +config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
As no FSPI, SYS_LS_PPA_FW_IN_XIP should not be used
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A if
+CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR
- hex "PPA header Addr"
- default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A endif
endif
+source "board/freescale/common/Kconfig"
+endif diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS new file mode 100644 index 0000000..135454c --- /dev/null +++ b/board/freescale/ls1028a/MAINTAINERS @@ -0,0 +1,10 @@ +LS1028ARDB BOARD +M: Sudhanshu Gupta sudhanshu.gupta@nxp.com +M: Rai Harninder harninder.rai@nxp.com +M: Rajesh Bhagat rajesh.bhagat@nxp.com +M: Tang Yuantian andy.tang@nxp.com +S: Maintained +F: board/freescale/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028ardb.h +F: configs/ls1028ardb_tfa_defconfig diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile new file mode 100644 index 0000000..9bc144c --- /dev/null +++ b/board/freescale/ls1028a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += ls1028a.o +obj-y += ddr.o diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README new file mode 100644 index 0000000..94a390c --- /dev/null +++ b/board/freescale/ls1028a/README @@ -0,0 +1,79 @@ +Overview +-------- +The LS1028A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports ARM SoC LS1028A and +its derivatives.
+LS1028A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+RDB Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For XSPI NOR boot (default) +SW2: 1111_1000 +SW3: 1111_0000 +SW5: 0011_1001
As no FSPI driver remove this.
+For SD Boot +SW2: 1000_1000 +SW3: 1111_0000 +SW5: 0011_1001
+For eMMC Boot +SW2: 1001_1000 +SW3: 1111_0000 +SW5: 0011_1001
+LS1028ARDB board Overview +------------------------- +Processor
- Two Arm Cortex- A72 processor cores:
- Based on 64-bit ARMv8 architecture
- Up to 1.3 GHz operation
- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
- data cache
- Arranged as a single cluster of two cores sharing a single 1 MB L2
- cache
+DDR memory
- Five onboard 1G x8 discrete memory modules (Four data byte lanes
- ECC)
- 32-bit data and 4-bit ECC
- One chip select
- Data transfer rates of up to 1.6 GT/s
- Single-bit error correction and double-bit error detection ECC (4-bit
- check word across 32-bit data)
+High-speed serial ports(SerDes)
- Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
- Qualcomm AR8033 PHY
- Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
- through the NXP F104S8A PHY
- Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
- (8 Gbit/s) cards
- Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
- slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
- SATA Gen 3 cards (6 Gbit/s) at a time eSDHC
- eSDHC1, eSDHC2
+SPI
- Connects to two mikroBUS sockets to support mikro-click modules,
- such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
- field communications (NFC) controller Octal SPI (XSPI)
- One 256 MB onboard XSPI serial NOR flash memory
- One 512 MB onboard XSPI serial NAND flash memory
- Supports a QSPI emulator for offboard QSPI emulation I2C
- All system devices are accessed via I2C1, which is multiplexed on
- I2C multiplexer PCA9848 to isolate address conflicts and reduce
- capacitive load
- I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
- thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
- 1 and 2
+CAN
- The two CAN DB9 ports can support CAN FD fast phase at data rates of
- up to 5 Mbit/s
+Serial audio interface(SAI)
- Audio codec SGTL5000 provides headphone and audio LINEOUT for
- stereo speakers
- IEEE1588 interface to support audio on SAI4
diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c new file mode 100644 index 0000000..63b30d8 --- /dev/null +++ b/board/freescale/ls1028a/ddr.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include "ddr.h"
+DECLARE_GLOBAL_DATA_PTR;
+void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,unsigned int ctrl_num)+{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);return;- }
- if (!pdimm->n_ranks)
return;- pbsp = udimms[0];
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.*/- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {if (ddr_freq <= pbsp->datarate_mhz_high) {popts->clk_adjust = pbsp->clk_adjust;popts->wrlvl_start = pbsp->wrlvl_start;popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;popts->cpo_override = pbsp->cpo_override;popts->write_data_delay =pbsp->write_data_delay;goto found;}pbsp_highest = pbsp;}pbsp++;- }
- if (pbsp_highest) {
printf("Error: board specific timing not found for %lu MT/s\n",ddr_freq);printf("Trying to use the highest speed (%u) parameters\n",pbsp_highest->datarate_mhz_high);popts->clk_adjust = pbsp_highest->clk_adjust;popts->wrlvl_start = pbsp_highest->wrlvl_start;popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;- } else {
panic("DIMM is not supported by this board");- }
+found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- /*
* Factors to consider for half-strength driver enable:* - number of DIMMs installed*/- popts->half_strength_driver_enable = 1;
- /*
* Write leveling override*/- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- /*
* Rtt and Rtt_WR override*/- popts->rtt_override = 0;
- /* Enable ZQ calibration */
- popts->zq_en = 1;
+#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x46;
+#else
- popts->cswl_override = DDR_CSWL_CS0;
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
Does LS1028A support other than DDR4?
DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); #endif }
+#ifdef CONFIG_TARGET_LS1028ARDB +#ifdef CONFIG_SYS_DDR_RAW_TIMING +/* MT40A1G8SA-075:E */ +dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 4294967296u,
- .capacity = 4294967296u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 4,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 16,
- .n_col_addr = 10,
- .bank_addr_bits = 0,
- .bank_group_bits = 2,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
- .tckmin_x_ps = 750,
- .tckmax_ps = 1900,
- .caslat_x = 0x0001FFE00,
- .taa_ps = 13500,
- .trcd_ps = 13500,
- .trp_ps = 13500,
- .tras_ps = 32000,
- .trc_ps = 45500,
- .trfc1_ps = 350000,
- .trfc2_ps = 260000,
- .trfc4_ps = 160000,
- .tfaw_ps = 21000,
- .trrds_ps = 3000,
- .trrdl_ps = 4900,
- .tccdl_ps = 5000,
- .refresh_rate_ps = 7800000,
- .dq_mapping[0] = 0x16,
- .dq_mapping[1] = 0x36,
- .dq_mapping[2] = 0x16,
- .dq_mapping[3] = 0x36,
- .dq_mapping[4] = 0x16,
- .dq_mapping[5] = 0x36,
- .dq_mapping[6] = 0x16,
- .dq_mapping[7] = 0x36,
- .dq_mapping[8] = 0x16,
- .dq_mapping[9] = 0x0,
- .dq_mapping[10] = 0x0,
- .dq_mapping[11] = 0x0,
- .dq_mapping[12] = 0x0,
- .dq_mapping[13] = 0x0,
- .dq_mapping[14] = 0x0,
- .dq_mapping[15] = 0x0,
- .dq_mapping[16] = 0x0,
- .dq_mapping[17] = 0x0,
- .dq_mapping_ors = 0,
+};
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,unsigned int dimm_number)+{
- static const char dimm_model[] = "Fixed DDR on board";
- if (controller_number == 0 && dimm_number == 0) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));memset(pdimm->mpart, 0, sizeof(pdimm->mpart));memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) -1);
- }
- return 0;
+} +#else +static phys_size_t fixed_sdram(void) +{
- size_t ddr_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
.cs[0].bnds = 0x000000ff,.cs[0].config = 0x80040422,.cs[0].config_2 = 0,.cs[1].bnds = 0,.cs[1].config = 0,.cs[1].config_2 = 0,.timing_cfg_3 = 0x01111000,.timing_cfg_0 = 0xd0550018,.timing_cfg_1 = 0xFAFC0C42,.timing_cfg_2 = 0x0048c114,.ddr_sdram_cfg = 0xe50c000c,.ddr_sdram_cfg_2 = 0x00401110,.ddr_sdram_mode = 0x01010230,.ddr_sdram_mode_2 = 0x0,.ddr_sdram_md_cntl = 0x0600001f,.ddr_sdram_interval = 0x18600618,.ddr_data_init = 0xdeadbeef,.ddr_sdram_clk_cntl = 0x02000000,.ddr_init_addr = 0,.ddr_init_ext_addr = 0,.timing_cfg_4 = 0x00000002,.timing_cfg_5 = 0x07401400,.timing_cfg_6 = 0x0,.timing_cfg_7 = 0x23300000,.ddr_zq_cntl = 0x8A090705,.ddr_wrlvl_cntl = 0x86550607,.ddr_sr_cntr = 0,.ddr_sdram_rcw_1 = 0,.ddr_sdram_rcw_2 = 0,.ddr_wrlvl_cntl_2 = 0x0708080A,.ddr_wrlvl_cntl_3 = 0x0A0B0C09,.ddr_sdram_mode_9 = 0x00000400,.ddr_sdram_mode_10 = 0x04000000,.timing_cfg_8 = 0x06115600,.dq_map_0 = 0x5b65b658,.dq_map_1 = 0xd96d8000,.dq_map_2 = 0,.dq_map_3 = 0x01600000,.ddr_cdr1 = 0x80040000,.ddr_cdr2 = 0x000000C1- };
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #endif
- ddr_size = 1ULL << 32;
- return ddr_size;
+} +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#endif
+#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{
- gd->ram_size = tfa_get_dram_size();
- if (!gd->ram_size)
+#ifdef CONFIG_TARGET_LS1028ARDB
gd->ram_size = 1ULL << 32;+#else
gd->ram_size = fsl_ddr_sdram_size();+#endif
- return 0;
+} +#else +int fsl_initdram(void) +{ +#ifdef CONFIG_TARGET_LS1028ARDB +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- gd->ram_size = 1ULL << 32;
+#else +#ifdef CONFIG_SYS_DDR_RAW_TIMING
- puts("Initializing DDR....\n");
- gd->ram_size = fsl_ddr_sdram();
+#else
- puts("Initializing DDR....using fixed timing\n");
- gd->ram_size = fixed_sdram();
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#endif +#else +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- gd->ram_size = fsl_ddr_sdram_size();
+#else
- puts("Initializing DDR....using SPD\n");
- gd->ram_size = fsl_ddr_sdram();
+#endif +#endif /* !CONFIG_TARGET_LS1028ARDB */
- return 0;
+} +#endif /* CONFIG_TFABOOT */
Considering only tfa boot will there.
Ddr.c and ddr.h is even required?
diff --git a/board/freescale/ls1028a/ddr.h b/board/freescale/ls1028a/ddr.h new file mode 100644 index 0000000..aae54e7 --- /dev/null +++ b/board/freescale/ls1028a/ddr.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- */
+#ifndef __DDR_H__ +#define __DDR_H__
+struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo_override;
- u32 write_data_delay;
- u32 force_2t;
+};
+/*
- These tables contain all valid speeds we want to override with board
- specific parameters. datarate_mhz_high values need to be in
+ascending order
- for each n_ranks group.
- */
+static const struct board_specific_parameters udimm0[] = {
- /*
* memory controller 0* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |*/+#ifdef CONFIG_TARGET_LS1028ARDB
- {1, 1666, 0, 8, 5, 0x06070700, 0x00000008,},
+#else
- {2, 1666, 0, 8, 8, 0x090a0b00, 0x0000000c,},
- {1, 1666, 0, 8, 8, 0x090a0b00, 0x0000000c,},
+#endif
- {}
+};
+static const struct board_specific_parameters *udimms[] = {
- udimm0,
+};
+#endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c new file mode 100644 index 0000000..853bb92 --- /dev/null +++ b/board/freescale/ls1028a/ls1028a.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <fsl_ddr.h> +#include <asm/io.h> +#include <hwconfig.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/arch-fsl-layerscape/soc.h> #include <i2c.h> #include +<asm/arch/soc.h> #ifdef CONFIG_FSL_LS_PPA #include <asm/arch/ppa.h> +#endif #include <fsl_immap.h> #include <netdev.h>
+#include <fdtdec.h> +#include <miiphy.h> +#include "../common/qixis.h"
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0]; #endif
+#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
+#endif
+#ifndef CONFIG_SYS_EARLY_PCI_INIT
- /* run PCI init to kick off ENETC */
- pci_init();
No reference of ENETC please
+#endif
+#if defined(CONFIG_TARGET_LS1028ARDB)
- u8 val = I2C_MUX_CH_DEFAULT;
- i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); #endif
- return 0;
+}
+int board_eth_init(bd_t *bis) +{
- return pci_eth_init(bis);
+}
+int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT
- i2c_early_init_f();
+#endif
- fsl_lsch3_early_init_f();
- return 0;
+}
+void detail_board_ddr_info(void) +{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
+}
+#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) {
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
- ft_cpu_setup(blob, bd);
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
- /* reduce size if reserved memory is within this bank */
- if (gd->arch.resv_ram >= base[0] &&
gd->arch.resv_ram < base[0] + size[0])size[0] = gd->arch.resv_ram - base[0];- else if (gd->arch.resv_ram >= base[1] &&
gd->arch.resv_ram < base[1] + size[1])size[1] = gd->arch.resv_ram - base[1]; #endif- fdt_fixup_memory_banks(blob, base, size, 2);
- return 0;
+} +#endif
+#ifdef CONFIG_FSL_QIXIS +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT
- enum boot_src src = get_boot_src();
+#endif
- u8 sw;
- int clock;
- char *board;
- char buf[64] = {0};
- static const char *freq[6] = {"100.00", "125.00", "156.25",
"161.13", "322.26", "100.00 SS"};- cpu_name(buf);
- /* find the board details */
- sw = QIXIS_READ(id);
- switch (sw) {
- case 0x46:
board = "QDS";break;- case 0x47:
board = "RDB";break;- case 0x49:
board = "HSSI";break;- default:
board = "unknown";break;- }
- sw = QIXIS_READ(arch);
- printf("Board: %s-%s, Version: %c, boot from ",
buf, board, (sw & 0xf) + 'A' - 1);- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+#ifdef CONFIG_TFABOOT
- if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");- } else if (src == BOOT_SOURCE_SD_MMC2) {
puts("eMMC\n");- } else {
+#endif +#ifdef CONFIG_SD_BOOT
puts("SD\n");+#elif defined(CONFIG_EMMC_BOOT)
puts("eMMC\n");+#else
switch (sw) {case 0:case 4:printf("NOR\n");break;case 1:printf("NAND\n");break;default:printf("invalid setting of SW%u\n",QIXIS_LBMAP_SWITCH);
break;}+#endif +#ifdef CONFIG_TFABOOT
- }
+#endif
- printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
- puts("SERDES1 Reference : ");
- sw = QIXIS_READ(brdcfg[2]);
+#ifdef CONFIG_TARGET_LS1028ARDB
- clock = (sw >> 6) & 3;
+#else
- clock = (sw >> 4) & 0xf;
+#endif
- printf("Clock1 = %sMHz ", freq[clock]); #ifdef
+CONFIG_TARGET_LS1028ARDB
- clock = (sw >> 4) & 3;
+#else
- clock = sw & 0xf;
+#endif
- printf("Clock2 = %sMHz\n", freq[clock]);
- return 0;
+} +#endif diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig new file mode 100644 index 0000000..7a6068d --- /dev/null +++ b/configs/ls1028ardb_tfa_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028ARDB=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080- 32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
Generate this file using make savedefconfig
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h new file mode 100644 index 0000000..c6175a6 --- /dev/null +++ b/include/configs/ls1028a_common.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- */
+#ifndef __L1028A_COMMON_H +#define __L1028A_COMMON_H
+#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_MP
+#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h>
+/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
+#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+/*
- SMP Definitinos
- */
+#define CPU_RELEASE_ADDR secondary_boot_func
Is it now being used? Secondary cores are getting released from Linux
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* I2C */ +#define CONFIG_SYS_I2C
+/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128
+/* Allow to overwrite serial and ethaddr */ #define +CONFIG_ENV_OVERWRITE
+#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
- "board=ls1028ardb\0" \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "fdt_addr=0x00f00000\0" \
- "kernel_addr=0x01000000\0" \
- "scriptaddr=0x80000000\0" \
- "scripthdraddr=0x80080000\0" \
- "fdtheader_addr_r=0x80100000\0" \
- "kernelheader_addr_r=0x80200000\0" \
- "load_addr=0xa0000000\0" \
- "kernel_addr_r=0x81000000\0" \
- "fdt_addr_r=0x90000000\0" \
- "ramdisk_addr_r=0xa0000000\0" \
- "kernel_start=0x1000000\0" \
- "kernelheader_start=0x800000\0" \
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
- "kernelheader_size=0x40000\0" \
- "kernel_addr_sd=0x8000\0" \
- "kernel_size_sd=0x14000\0" \
- "kernelhdr_addr_sd=0x4000\0" \
- "kernelhdr_size_sd=0x10\0" \
- "console=ttyS0,115200\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- BOOTENV \
- "boot_scripts=ls1028ardb_boot.scr\0" \
- "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
- "scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \"env exists devplist || setenv devplist 1; " \"for distro_bootpart in ${devplist}; do " \"if fstype ${devtype} " \"${devnum}:${distro_bootpart} " \"bootfstype; then " \"run scan_dev_for_boot; " \"fi; " \"done\0" \- "scan_dev_for_boot=" \
"echo Scanning ${devtype} " \"${devnum}:${distro_bootpart}...; " \"for prefix in ${boot_prefixes}; do " \"run scan_dev_for_scripts; " \"done;" \"\0" \- "boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \"${scriptaddr} ${prefix}${script}; " \"env exists secureboot && load ${devtype} " \"${devnum}:${distro_bootpart} " \"${scripthdraddr} ${prefix}${boot_script_hdr} " \"&& esbc_validate ${scripthdraddr};" \"source ${scriptaddr}\0" \- "sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \"$kernel_addr_sd $kernel_size_sd && " \"env exists secureboot && mmc read $kernelheader_addr_r " \"$kernelhdr_addr_sd $kernelhdr_size_sd " \" && esbc_validate ${kernelheader_addr_r};" \"bootm $load_addr#$board\0" \- "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
"mmcinfo;mmc read $load_addr 0x4800 0x200 " \"&& hdp load $load_addr 0x2000\0" \- "emmc_bootcmd=echo Trying load from EMMC ..;" \
"mmcinfo; mmc dev 1; mmc read $load_addr " \"$kernel_addr_sd $kernel_size_sd && " \"env exists secureboot && mmc read $kernelheader_addr_r " \"$kernelhdr_addr_sd $kernelhdr_size_sd " \" && esbc_validate ${kernelheader_addr_r};" \"bootm $load_addr#$board\0" \- "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"
\
"mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 ""&& hdp load $load_addr 0x2000\0"+#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define XSPI_NOR_BOOTCOMMAND \
XSPI??
- "run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND \
- "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
+#else +#if defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND \
- "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
+#elif defined(CONFIG_EMMC_BOOT) +#define CONFIG_BOOTCOMMAND \
- "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
- "env exists secureboot && esbc_halt;"
+#else +#define CONFIG_BOOTCOMMAND \
- "run qspi_hdploadcmd; run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;"
+#endif +#endif /* CONFIG_TFABOOT */
+/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#ifndef CONFIG_CMDLINE_EDITING +#define CONFIG_CMDLINE_EDITING 1 +#endif
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif
+#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define OCRAM_NONSECURE_SIZE 0x00010000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else
Does else part really required?
+#if defined(CONFIG_SD_BOOT) || defined(CONFIG_EMMC_BOOT) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define OCRAM_NONSECURE_SIZE 0x00010000 +#else +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif +#endif
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif
+/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8
+/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#endif /* __L1028A_COMMON_H */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h new file mode 100644 index 0000000..e93288a --- /dev/null +++ b/include/configs/ls1028ardb.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- */
+#ifndef __LS1028A_RDB_H +#define __LS1028A_RDB_H
+#include "ls1028a_common.h"
+#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_RTC_BUS_NUM 0
+/* DDR */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Store environment at top of flash */ +#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT
+/*
- QIXIS Definitions
- */
+#define CONFIG_FSL_QIXIS
+#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 2 +#define QIXIS_LBMAP_MASK 0xe0 +#define QIXIS_LBMAP_SHIFT 0x5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x00 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_SD 0xf8 +#define QIXIS_RCW_SRC_EMMC 0xf9 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x11 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \CSPR_MSEL_GPCM | \CSPR_V)+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \CSOR_NOR_TRHZ_80)+#endif
+/* SATA */ +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)+#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} #define +CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
+#endif /* __LS1028A_RDB_H */
General comment - avoid FSPI, XSPI related word, configs as no flexspi driver in upstream - avoid enetc related word as no enetc driver in upstream - Avoid #else part of CONFIG_TFABOOT as TFA boot is only supported mechanism, - Remove DDR related code as TFA doing DDR init
--pk
-----Original Message----- From: Yuantian Tang andy.tang@nxp.com Sent: Wednesday, April 3, 2019 12:48 PM To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: albert.u.boot@aribaud.net; Sudhanshu Gupta sudhanshu.gupta@nxp.com; Harninder Rai harninder.rai@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Bhaskar Upadhaya bhaskar.upadhaya@nxp.com; u-boot@lists.denx.de; Andy Tang andy.tang@nxp.com Subject: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support
LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a GPU and LCD controller, as well as TSN-enabled Ethernet ports and a TSN-enabled switch with four external ports. The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a number of industrial and embedded applications. The device provides excellent integration with the new Time-Sensitive Networking standards and enables a number of TSN applications
Features Summary
- Two 32/64-bit Arm v8 Cortex-A72 CPUs
- Cache coherent interconnect fabric (CCI-400)
- 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support
- LCD controller and DisplayPort/eDP interface
- Graphics processing unit
- TSN-capable Ethernet Switch with four external ports
- Ethernet Controller (ENETC) with TSN functionality
- Four SerDes lanes with two PLLs for high-speed peripheral interfaces
- Additional peripheral interfaces
- Two high-speed USB 3.0 controllers
- Two eSDHC controllers
- Two controller area network (FlexCAN) modules
- supporting flexible datarate (FD)
- Three serial peripheral interface (SPI) controllers
- Flexible SPI interface (FlexSPI) controller
- Eight I2C controllers
- Six LPUARTs
- 16550-compliant DUART
- General Purpose IO (GPIO)
- Eight FlexTimers/PWM controllers
- Six asynchronous audio interface (SAI)
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Queue direct memory access controller (qDMA)
- Enhanced direct memory access controller (eDMA)
- Global programmable interrupt controller (GIC)
- Arm generic timer
- Thermal Monitor Unit (TMU)
It looks to be marketing description This patch is not supporting all above features. So update description with whatever supported by this patch.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang Yuantian andy.tang@nxp.com
v2:
- fix many issues
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++ arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++++++ arch/arm/dts/fsl-ls1028a.dtsi | 280 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- 11 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..8ecd095 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -20,6 +20,40 @@ config ARCH_LS1012A select SYS_I2C_MXC_I2C2 imply PANIC_HANG
+config ARCH_LS1028A
- bool
- select ARMV8_SET_SMPEN
- select FSL_LSCH3
- select NXP_LSCH3_2
- select SYS_FSL_HAS_CCI400
- select SYS_FSL_SRDS_1
- select SYS_HAS_SERDES
- select SYS_FSL_DDR
- select SYS_FSL_DDR_LE
- select SYS_FSL_DDR_VER_50
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_DDR4
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_COMPAT_5
- select SYS_FSL_SEC_LE
- select FSL_TZASC_1
- select ARCH_EARLY_INIT_R
- select BOARD_EARLY_INIT_F
- select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
- select SYS_I2C_MXC_I2C5
- select SYS_I2C_MXC_I2C6
- select SYS_I2C_MXC_I2C7
- select SYS_I2C_MXC_I2C8
- select SYS_FSL_ERRATUM_A009007
- select SYS_FSL_ERRATUM_A008514 if !TFABOOT
- select SYS_FSL_ERRATUM_A009663 if !TFABOOT
- select SYS_FSL_ERRATUM_A009942 if !TFABOOT
- imply PANIC_HANG
config ARCH_LS1043A bool select ARMV8_SET_SMPEN @@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE default "fsl,ls1012a-pcie" if ARCH_LS1012A
- default "fsl,ls1028a-pcie" if ARCH_LS1028A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@
config SYS_FSL_ERRATUM_A010539
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape"
- default 2 if ARCH_LS1028A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A
@@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400
- default 0x3090000 if ARCH_LS1088A
- default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A default 0x180000 if FSL_LSCH2 help Offset for CCI400 base
@@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ
config SYS_FSL_PCLK_DIV int "Platform clock divider"
- default 1 if ARCH_LS1028A default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A default 1 if ARCH_LS1088A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e9bc987..a8d3cf9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -48,3 +48,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif
+ifneq ($(CONFIG_ARCH_LS1028A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b..657d13c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
- CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
@@ -246,11 +247,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifndef CONFIG_ARCH_LS1028A
Please avoid using SoC specific #ifndef. Use #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR And change code accordingly.
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#endif #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a0e2621..ad55573 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -8,6 +8,7 @@ SoC overview 6. LS2088A 7. LS2081A 8. LX2160A
- LS1028A
LS1043A
@@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities
2)LX2080A, few difference w.r.t. LX2160A: a) Eight 64-bit ARM v8 Cortex-A72 CPUs
+LS1028A +-------- +The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores +with a GPU and LCD controller, as well as two TSN-enabled Ethernet +controllers and a TSNenabled 4-port switch.
+The high performance Cortex-A72 cores, performing above 16,000 +CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA +3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a +number of industrial and embedded applications. The device provides +excellent integration with the new Time-Sensitive Networking standard, +and enables a number of TSN applications.
+The LS1028A SoC includes the following function and features:
- Two 64-bit ARM v8 A72 CPUs
- Cache Coherent interconnect (CCI-400)
- One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
- eDP/Displayport interface
- Graphics processing unit
- One Configurable x4 SerDes
- Ethernet interfaces
- Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
- ethernet MAC supporting 1G, 100M, 10M.
- Switched: TSN IP to support four 2.5/1G interfaces.
- None of the MACs support MACSEC
- Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
- Support for 10G-SXGMII and 10G-QXGMII.
- Energy efficient Ethernet support (802.3az)
- IEEE 1588 support
- High-speed peripheral interfaces
- Two PCIe 3.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controller
- Additional peripheral interfaces
- Two high-speed USB 2.0/3.0 controllers with integrated PHY each
supporting host or device modes
- Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
- Two Serial peripheral interface (SPI) controllers
- Eight I2C controllers
- Two UART controllers
- Additional six Industrual UARTs (LPUART).
- One FlexSPI controller
- General Purpose IO (GPIO)
- Two CAN-FD interfaces
- Eight Flextimers with PWM I/O
- Support for hardware virtualization and partitioning enforcement
- Layerscape Trust Architecture
- Service Processor (SP) provides pre-boot initialization and secure-boot
- capabilities
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c new file mode 100644 index 0000000..f5f264c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+#include <common.h> +#include <asm/arch/fsl_serdes.h>
+struct serdes_config {
- u32 protocol;
- u8 lanes[SRDS_MAX_LANES];
- u8 rcw_lanes[SRDS_MAX_LANES];
+};
+static struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
- {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
- {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
- {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
- {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
- {0xCC51, {SXGMII1, QSGMII_B, PCIE2, PCIE2} },
- {0xCC3B, {PCIE1, QXGMII2, PCIE2, PCIE2} },
- {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
- {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
- {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
- {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
- {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
- {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
- {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
- {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
- {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
- {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
- {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
- {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
- {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
- {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
- {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
- {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
- {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
- serdes1_cfg_tbl,
+};
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) {
- struct serdes_config *ptr;
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
if (ptr->protocol == cfg)return ptr->lanes[lane];ptr++;- }
- return 0;
+}
+int is_serdes_prtcl_valid(int serdes, u32 prtcl) {
- int i;
- struct serdes_config *ptr;
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
if (ptr->protocol == prtcl)break;ptr++;- }
- if (!ptr->protocol)
return 0;- for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)return 1;- }
- return 0;
+} diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi new file mode 100644 index 0000000..a38c8ce --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP ls1028a SOC common device tree source
- Copyright 2019 NXP
- */
+/ {
- compatible = "fsl,ls1028a";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- sysclk: sysclk {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <100000000>;clock-output-names = "sysclk";- };
- clockgen: clocking@1300000 {
compatible = "fsl,ls1028a-clockgen";reg = <0x0 0x1300000 0x0 0xa0000>;#clock-cells = <2>;clocks = <&sysclk>;- };
- memory@01080000 {
device_type = "memory";reg = <0x00000000 0x01080000 0 0x80000000>;/* DRAM space - 1, size : 2 GB DRAM */- };
- gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */<0x0 0x06040000 0 0x40000>;#interrupt-cells = <3>;interrupt-controller;interrupts = <1 9 0x4>;- };
- timer {
compatible = "arm,armv8-timer";interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */<1 14 0x8>, /* Physical Non-Secure PPI, active-low*/
<1 11 0x8>, /* Virtual PPI, active-low */<1 10 0x8>; /* Hypervisor PPI, active-low */- };
- fspi: flexspi@20C0000 {
compatible = "nxp,dn-fspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x20C0000 0x0 0x10000>,<0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/reg-names = "FSPI", "FSPI-memory";num-cs = <1>;status = "disabled";- };
- serial0: serial@21c0500 {
device_type = "serial";compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0500 0x0 0x100>;interrupts = <0 32 0x1>; /* edge triggered */status = "disabled";- };
- serial1: serial@21c0600 {
device_type = "serial";compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0600 0x0 0x100>;interrupts = <0 32 0x1>; /* edge triggered */status = "disabled";- };
- pcie@3400000 { /* rcie_enetc */
This patch does not have support of enetc. So avoid references of entc
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";reg = <0x00 0x03400000 0x0 0x800000x00 0x03480000 0x0 0x40000 /* lut registers */0x00 0x034c0000 0x0 0x40000 /* pf controls registers */0x80 0x00000000 0x0 0x20000>; /* configuration space */reg-names = "dbi", "lut", "ctrl", "config";#address-cells = <3>;#size-cells = <2>;device_type = "pci";num-lanes = <4>;bus-range = <0x0 0xff>;ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x00x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x00x40000000>; /* non-prefetchable memory */
- };
- pcie@3500000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";reg = <0x00 0x03500000 0x0 0x800000x00 0x03580000 0x0 0x40000 /* lut registers */0x00 0x035c0000 0x0 0x40000 /* pf controls registers */0x88 0x00000000 0x0 0x20000>; /* configuration space */reg-names = "dbi", "lut", "ctrl", "config";#address-cells = <3>;#size-cells = <2>;device_type = "pci";num-lanes = <4>;bus-range = <0x0 0xff>;ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x00x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x00x40000000>; /* non-prefetchable memory */
- };
- i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2000000 0x0 0x10000>;interrupts = <0 34 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2010000 0x0 0x10000>;interrupts = <0 34 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2020000 0x0 0x10000>;interrupts = <0 35 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2030000 0x0 0x10000>;interrupts = <0 35 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c4: i2c@2040000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2040000 0x0 0x10000>;interrupts = <0 74 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c5: i2c@2050000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2050000 0x0 0x10000>;interrupts = <0 74 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c6: i2c@2060000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2060000 0x0 0x10000>;interrupts = <0 75 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c7: i2c@2070000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2070000 0x0 0x10000>;interrupts = <0 75 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- usb1: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";reg = <0x0 0x3100000 0x0 0x10000>;interrupts = <0 80 0x4>;dr_mode = "host";status = "disabled";- };
- usb2: usb3@3110000 {
compatible = "fsl,layerscape-dwc3";reg = <0x0 0x3110000 0x0 0x10000>;interrupts = <0 81 0x4>;dr_mode = "host";status = "disabled";- };
- dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2100000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;litte-endian;status = "disabled";- };
- dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2110000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;little-endian;status = "disabled";- };
- dspi2: dspi@2120000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2120000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;little-endian;status = "disabled";- };
- esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";reg = <0x0 0x2140000 0x0 0x10000>;interrupts = <0 28 0x4>;big-endian;bus-width = <4>;status = "disabled";- };
- esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";reg = <0x0 0x2150000 0x0 0x10000>;interrupts = <0 63 0x4>;big-endian;non-removable;bus-width = <4>;status = "disabled";- };
- sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";reg = <0x0 0x3200000 0x0 0x10000>;interrupts = <0 133 4>;clocks = <&clockgen 4 1>;status = "disabled";};+}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 903d509..eb21c09 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,67 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400
+/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000
+/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */
+/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE
+/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE
+/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS
+/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE
#elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff..59b224b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,22 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D,
- SGMII_T1,
- SGMII_T2,
- SGMII_T3,
- SGMII_T4,
- SGMII_S1,
- SGMII_S2,
- SGMII_S3,
- SGMII_S4,
Can existing SGMII enum not be used?
- SXGMII1,
- SXGMII2,
- SXGMII3,
- SXGMII4,
- QXGMII1,
- QXGMII2,
- QXGMII3,
- QXGMII4, _25GE1, _25GE2, _25GE3,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88a..dbf3215 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -171,6 +171,9 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -375,6 +378,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 #endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 7d95c4e..234440b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index e017d8b..c53cc57 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -87,7 +87,7 @@ #define FSL_PEX_STREAM_ID_NUM (0x100) #endif
-#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A)
#define FSL_PEX_STREAM_ID_END 18
2.7.4
--pk
Hi Prabhakar,
-----Original Message----- From: Prabhakar Kushwaha Sent: 2019年4月7日 17:58 To: Andy Tang andy.tang@nxp.com Cc: albert.u.boot@aribaud.net; Sudhanshu Gupta sudhanshu.gupta@nxp.com; Harninder Rai harninder.rai@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Bhaskar Upadhaya bhaskar.upadhaya@nxp.com; u-boot@lists.denx.de; Andy Tang andy.tang@nxp.com Subject: RE: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support
-----Original Message----- From: Yuantian Tang andy.tang@nxp.com Sent: Wednesday, April 3, 2019 12:48 PM To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: albert.u.boot@aribaud.net; Sudhanshu Gupta sudhanshu.gupta@nxp.com; Harninder Rai harninder.rai@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; Bhaskar Upadhaya bhaskar.upadhaya@nxp.com; u-boot@lists.denx.de; Andy Tang andy.tang@nxp.com Subject: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support
LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a GPU and LCD controller, as well as TSN-enabled Ethernet ports and a TSN-enabled switch with four external ports. The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a number of industrial and embedded applications. The device provides excellent integration with the new Time-Sensitive Networking standards and enables a number of TSN applications
Features Summary
- Two 32/64-bit Arm v8 Cortex-A72 CPUs
- Cache coherent interconnect fabric (CCI-400)
- 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support
- LCD controller and DisplayPort/eDP interface
- Graphics processing unit
- TSN-capable Ethernet Switch with four external ports
- Ethernet Controller (ENETC) with TSN functionality
- Four SerDes lanes with two PLLs for high-speed peripheral interfaces
- Additional peripheral interfaces
- Two high-speed USB 3.0 controllers
- Two eSDHC controllers
- Two controller area network (FlexCAN) modules
- supporting flexible datarate (FD)
- Three serial peripheral interface (SPI) controllers
- Flexible SPI interface (FlexSPI) controller
- Eight I2C controllers
- Six LPUARTs
- 16550-compliant DUART
- General Purpose IO (GPIO)
- Eight FlexTimers/PWM controllers
- Six asynchronous audio interface (SAI)
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Queue direct memory access controller (qDMA)
- Enhanced direct memory access controller (eDMA)
- Global programmable interrupt controller (GIC)
- Arm generic timer
- Thermal Monitor Unit (TMU)
It looks to be marketing description This patch is not supporting all above features. So update description with whatever supported by this patch.
It listed all the features SOC supports, not the features this PATCH supports. We should give a full feature list when a new soc was added.
Signed-off-by: Sudhanshu Gupta sudhanshu.gupta@nxp.com Signed-off-by: Rai Harninder harninder.rai@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com Signed-off-by: Bhaskar Upadhaya Bhaskar.Upadhaya@nxp.com Signed-off-by: Tang Yuantian andy.tang@nxp.com
v2:
- fix many issues
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++ arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++++++ arch/arm/dts/fsl-ls1028a.dtsi | 280
+++++++++++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- 11 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..8ecd095 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -20,6 +20,40 @@ config ARCH_LS1012A select SYS_I2C_MXC_I2C2 imply PANIC_HANG
+config ARCH_LS1028A
- bool
- select ARMV8_SET_SMPEN
- select FSL_LSCH3
- select NXP_LSCH3_2
- select SYS_FSL_HAS_CCI400
- select SYS_FSL_SRDS_1
- select SYS_HAS_SERDES
- select SYS_FSL_DDR
- select SYS_FSL_DDR_LE
- select SYS_FSL_DDR_VER_50
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_DDR4
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_COMPAT_5
- select SYS_FSL_SEC_LE
- select FSL_TZASC_1
- select ARCH_EARLY_INIT_R
- select BOARD_EARLY_INIT_F
- select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
- select SYS_I2C_MXC_I2C5
- select SYS_I2C_MXC_I2C6
- select SYS_I2C_MXC_I2C7
- select SYS_I2C_MXC_I2C8
- select SYS_FSL_ERRATUM_A009007
- select SYS_FSL_ERRATUM_A008514 if !TFABOOT
- select SYS_FSL_ERRATUM_A009663 if !TFABOOT
- select SYS_FSL_ERRATUM_A009942 if !TFABOOT
- imply PANIC_HANG
config ARCH_LS1043A bool select ARMV8_SET_SMPEN @@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE default "fsl,ls1012a-pcie" if ARCH_LS1012A
- default "fsl,ls1028a-pcie" if ARCH_LS1028A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@
config SYS_FSL_ERRATUM_A010539
config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape"
- default 2 if ARCH_LS1028A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A
@@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400
- default 0x3090000 if ARCH_LS1088A
- default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A default 0x180000 if FSL_LSCH2 help Offset for CCI400 base
@@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ
config SYS_FSL_PCLK_DIV int "Platform clock divider"
- default 1 if ARCH_LS1028A default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A default 1 if ARCH_LS1088A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e9bc987..a8d3cf9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -48,3 +48,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif
+ifneq ($(CONFIG_ARCH_LS1028A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b..657d13c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
- CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
@@ -246,11 +247,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifndef CONFIG_ARCH_LS1028A
Please avoid using SoC specific #ifndef. Use #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR And change code accordingly.
A: Okay
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#endif #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a0e2621..ad55573 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -8,6 +8,7 @@ SoC overview 6. LS2088A 7. LS2081A 8. LX2160A
- LS1028A
LS1043A
@@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities
2)LX2080A, few difference w.r.t. LX2160A: a) Eight 64-bit ARM v8 Cortex-A72 CPUs
+LS1028A +-------- +The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores +with a GPU and LCD controller, as well as two TSN-enabled Ethernet +controllers and a TSNenabled 4-port switch.
+The high performance Cortex-A72 cores, performing above 16,000 +CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA +3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a +number of industrial and embedded applications. The device provides +excellent integration with the new Time-Sensitive Networking standard, +and enables a number of TSN applications.
+The LS1028A SoC includes the following function and features:
- Two 64-bit ARM v8 A72 CPUs
- Cache Coherent interconnect (CCI-400)
- One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
- eDP/Displayport interface
- Graphics processing unit
- One Configurable x4 SerDes
- Ethernet interfaces
- Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
- ethernet MAC supporting 1G, 100M, 10M.
- Switched: TSN IP to support four 2.5/1G interfaces.
- None of the MACs support MACSEC
- Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
- Support for 10G-SXGMII and 10G-QXGMII.
- Energy efficient Ethernet support (802.3az)
- IEEE 1588 support
- High-speed peripheral interfaces
- Two PCIe 3.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controller
- Additional peripheral interfaces
- Two high-speed USB 2.0/3.0 controllers with integrated PHY each
supporting host or device modes
- Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
- Two Serial peripheral interface (SPI) controllers
- Eight I2C controllers
- Two UART controllers
- Additional six Industrual UARTs (LPUART).
- One FlexSPI controller
- General Purpose IO (GPIO)
- Two CAN-FD interfaces
- Eight Flextimers with PWM I/O
- Support for hardware virtualization and partitioning enforcement
- Layerscape Trust Architecture
- Service Processor (SP) provides pre-boot initialization and secure-boot
- capabilities
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c new file mode 100644 index 0000000..f5f264c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+#include <common.h> +#include <asm/arch/fsl_serdes.h>
+struct serdes_config {
- u32 protocol;
- u8 lanes[SRDS_MAX_LANES];
- u8 rcw_lanes[SRDS_MAX_LANES];
+};
+static struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
- {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
- {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
- {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
- {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
- {0xCC51, {SXGMII1, QSGMII_B, PCIE2, PCIE2} },
- {0xCC3B, {PCIE1, QXGMII2, PCIE2, PCIE2} },
- {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
- {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
- {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
- {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
- {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
- {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
- {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
- {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
- {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
- {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
- {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
- {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
- {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
- {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
- {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
- {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
- {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
- serdes1_cfg_tbl,
+};
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) {
- struct serdes_config *ptr;
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
if (ptr->protocol == cfg)return ptr->lanes[lane];ptr++;- }
- return 0;
+}
+int is_serdes_prtcl_valid(int serdes, u32 prtcl) {
- int i;
- struct serdes_config *ptr;
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
if (ptr->protocol == prtcl)break;ptr++;- }
- if (!ptr->protocol)
return 0;- for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)return 1;- }
- return 0;
+} diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
new
file mode 100644 index 0000000..a38c8ce --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP ls1028a SOC common device tree source
- Copyright 2019 NXP
- */
+/ {
- compatible = "fsl,ls1028a";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- sysclk: sysclk {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <100000000>;clock-output-names = "sysclk";- };
- clockgen: clocking@1300000 {
compatible = "fsl,ls1028a-clockgen";reg = <0x0 0x1300000 0x0 0xa0000>;#clock-cells = <2>;clocks = <&sysclk>;- };
- memory@01080000 {
device_type = "memory";reg = <0x00000000 0x01080000 0 0x80000000>;/* DRAM space - 1, size : 2 GB DRAM */- };
- gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */<0x0 0x06040000 0 0x40000>;#interrupt-cells = <3>;interrupt-controller;interrupts = <1 9 0x4>;- };
- timer {
compatible = "arm,armv8-timer";interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */<1 14 0x8>, /* Physical Non-Secure PPI, active-low*/
<1 11 0x8>, /* Virtual PPI, active-low */<1 10 0x8>; /* Hypervisor PPI, active-low */- };
- fspi: flexspi@20C0000 {
compatible = "nxp,dn-fspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x20C0000 0x0 0x10000>,<0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/reg-names = "FSPI", "FSPI-memory";num-cs = <1>;status = "disabled";- };
- serial0: serial@21c0500 {
device_type = "serial";compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0500 0x0 0x100>;interrupts = <0 32 0x1>; /* edge triggered */status = "disabled";- };
- serial1: serial@21c0600 {
device_type = "serial";compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0600 0x0 0x100>;interrupts = <0 32 0x1>; /* edge triggered */status = "disabled";- };
- pcie@3400000 { /* rcie_enetc */
This patch does not have support of enetc. So avoid references of entc
A: many IPs this patch doesn't support, like USB, sata, clock..., they all should be removed?
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";reg = <0x00 0x03400000 0x0 0x800000x00 0x03480000 0x0 0x40000 /* lut registers */0x00 0x034c0000 0x0 0x40000 /* pf controls registers */0x80 0x00000000 0x0 0x20000>; /* configuration space */reg-names = "dbi", "lut", "ctrl", "config";#address-cells = <3>;#size-cells = <2>;device_type = "pci";num-lanes = <4>;bus-range = <0x0 0xff>;ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x00x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x00x40000000>; /* non-prefetchable memory */
- };
- pcie@3500000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";reg = <0x00 0x03500000 0x0 0x800000x00 0x03580000 0x0 0x40000 /* lut registers */0x00 0x035c0000 0x0 0x40000 /* pf controls registers */0x88 0x00000000 0x0 0x20000>; /* configuration space */reg-names = "dbi", "lut", "ctrl", "config";#address-cells = <3>;#size-cells = <2>;device_type = "pci";num-lanes = <4>;bus-range = <0x0 0xff>;ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x00x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x00x40000000>; /* non-prefetchable memory */
- };
- i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2000000 0x0 0x10000>;interrupts = <0 34 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2010000 0x0 0x10000>;interrupts = <0 34 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2020000 0x0 0x10000>;interrupts = <0 35 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2030000 0x0 0x10000>;interrupts = <0 35 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c4: i2c@2040000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2040000 0x0 0x10000>;interrupts = <0 74 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c5: i2c@2050000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2050000 0x0 0x10000>;interrupts = <0 74 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c6: i2c@2060000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2060000 0x0 0x10000>;interrupts = <0 75 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- i2c7: i2c@2070000 {
compatible = "fsl,vf610-i2c";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2070000 0x0 0x10000>;interrupts = <0 75 0x4>;clock-names = "i2c";clocks = <&clockgen 4 0>;status = "disabled";- };
- usb1: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";reg = <0x0 0x3100000 0x0 0x10000>;interrupts = <0 80 0x4>;dr_mode = "host";status = "disabled";- };
- usb2: usb3@3110000 {
compatible = "fsl,layerscape-dwc3";reg = <0x0 0x3110000 0x0 0x10000>;interrupts = <0 81 0x4>;dr_mode = "host";status = "disabled";- };
- dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2100000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;litte-endian;status = "disabled";- };
- dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2110000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;little-endian;status = "disabled";- };
- dspi2: dspi@2120000 {
compatible = "fsl,vf610-dspi";#address-cells = <1>;#size-cells = <0>;reg = <0x0 0x2120000 0x0 0x10000>;interrupts = <0 26 0x4>;clock-names = "dspi";clocks = <&clockgen 4 0>;num-cs = <5>;little-endian;status = "disabled";- };
- esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";reg = <0x0 0x2140000 0x0 0x10000>;interrupts = <0 28 0x4>;big-endian;bus-width = <4>;status = "disabled";- };
- esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";reg = <0x0 0x2150000 0x0 0x10000>;interrupts = <0 63 0x4>;big-endian;non-removable;bus-width = <4>;status = "disabled";- };
- sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";reg = <0x0 0x3200000 0x0 0x10000>;interrupts = <0 133 4>;clocks = <&clockgen 4 1>;status = "disabled";};+}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 903d509..eb21c09 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,67 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400
+/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size
256K
*/
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000
+/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */
+/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE
+/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE
+/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS
+/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE
#elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff..59b224b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,22 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D,
- SGMII_T1,
- SGMII_T2,
- SGMII_T3,
- SGMII_T4,
- SGMII_S1,
- SGMII_S2,
- SGMII_S3,
- SGMII_S4,
Can existing SGMII enum not be used?
A: not sure, will remove it.
BR, Andy
- SXGMII1,
- SXGMII2,
- SXGMII3,
- SXGMII4,
- QXGMII1,
- QXGMII2,
- QXGMII3,
- QXGMII4, _25GE1, _25GE2, _25GE3,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88a..dbf3215 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -171,6 +171,9 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -375,6 +378,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 #endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 7d95c4e..234440b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER
*/
#define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index e017d8b..c53cc57 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -87,7 +87,7 @@ #define FSL_PEX_STREAM_ID_NUM (0x100) #endif
-#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A)
#define FSL_PEX_STREAM_ID_END 18
2.7.4
--pk
participants (3)
-
Andy Tang -
Prabhakar Kushwaha -
Yuantian Tang