[U-Boot] [PATCH v2 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin jilin@nvidia.com --- arch/arm/dts/tegra114.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/dts/tegra30.dtsi | 27 +++++++++++++++++++++++++++ board/nvidia/dts/tegra114-dalmore.dts | 7 +++++++ board/nvidia/dts/tegra30-beaver.dts | 6 ++++++ board/nvidia/dts/tegra30-cardhu.dts | 6 ++++++ include/fdtdec.h | 2 ++ lib/fdtdec.c | 2 ++ 7 files changed, 77 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index f86d18d..f87d05a 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -216,4 +216,31 @@ clocks = <&tegra_car 15>; status = "disable"; }; + + usb@7d000000 { + compatible = "nvidia,tegra114-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <52>; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra114-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = <53>; + phy_type = "utmi"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra114-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = <129>; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + status = "disabled"; + }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index ccf154f..e5275c2 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -216,4 +216,31 @@ clocks = <&tegra_car 15>; status = "disabled"; }; + + usb@7d000000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <52>; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = <53>; + phy_type = "utmi"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra30-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = <129>; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + status = "disabled"; + }; }; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 86e9459..435c01e 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -14,6 +14,7 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000400"; + usb0 = "/usb@7d008000"; };
memory { @@ -61,4 +62,10 @@ bus-width = <8>; status = "okay"; }; + + usb@7d008000 { + /* SPDIF_IN: USB_VBUS_EN1 */ + nvidia,vbus-gpio = <&gpio 86 0>; + status = "okay"; + }; }; diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts index 836169f..b003ae1 100644 --- a/board/nvidia/dts/tegra30-beaver.dts +++ b/board/nvidia/dts/tegra30-beaver.dts @@ -14,6 +14,7 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000000"; + usb0 = "/usb@7d008000"; };
memory { @@ -68,4 +69,9 @@ status = "okay"; bus-width = <8>; }; + + usb@7d008000 { + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5, USB13_VBUS_PULLUP */ + status = "okay"; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 4d22b48..071a464 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -14,6 +14,7 @@ i2c4 = "/i2c@7000c700"; sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000000"; + usb0 = "/usb@7d008000"; };
memory { @@ -63,4 +64,9 @@ status = "okay"; bus-width = <8>; }; + + usb@7d008000 { + nvidia,vbus-gpio = <&gpio 233 3>; /* PDD1, EN_3V3_PU */ + status = "okay"; + }; }; diff --git a/include/fdtdec.h b/include/fdtdec.h index 4e8032b..d19b9f3 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -64,6 +64,8 @@ struct fdt_memory { enum fdt_compat_id { COMPAT_UNKNOWN, COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */ + COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */ + COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */ COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */ COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */ COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index ac1fe0b..ffc4369 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, "<none>"), COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), + COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"), + COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"), COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"), COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Signed-off-by: Jim Lin jilin@nvidia.com --- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 182 ++++-------------- arch/arm/include/asm/arch-tegra114/usb.h | 156 +++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 155 +++++++++++++++ arch/arm/include/asm/arch-tegra30/usb.h | 168 ++++++++++++++++ board/nvidia/common/board.c | 2 +- drivers/usb/host/ehci-tegra.c | 297 +++++++++++++++++++++++++---- 7 files changed, 796 insertions(+), 174 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index c754ec7..9b8de9c 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -225,6 +225,16 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, };
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_XOBP_SHIFT 1 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index ef6c089..cefe0d2 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2013 NVIDIA Corporation * See file CREDITS for list of people who contributed to this * project. * @@ -22,120 +23,6 @@ #ifndef _TEGRA_USB_H_ #define _TEGRA_USB_H_
- -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[6]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - - /* USB1_LEGACY_CTRL */ #define USB1_NO_LEGACY_MODE 1
@@ -146,25 +33,18 @@ struct usb_ctlr { #define VBUS_SENSE_CTL_AB_SESS_VLD 2 #define VBUS_SENSE_CTL_A_SESS_VLD 3
-/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - /* USBx_IF_USB_SUSP_CTRL_0 */ -#define ULPI_PHY_ENB (1 << 13) #define UTMIP_PHY_ENB (1 << 12) #define UTMIP_RESET (1 << 11) #define USB_PHY_CLK_VALID (1 << 7) #define USB_SUSP_CLR (1 << 5)
+/* USB2_IF_USB_SUSP_CTRL_0 */ +#define ULPI_PHY_ENB (1 << 13) + +/* USBx_UTMIP_MISC_CFG0 */ +#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) + /* USBx_UTMIP_MISC_CFG1 */ #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 #define UTMIP_PLLU_STABLE_COUNT_MASK \ @@ -177,15 +57,28 @@ struct usb_ctlr { /* USBx_UTMIP_PLL_CFG1_0 */ #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) + (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
+/* USBx_UTMIP_BIAS_CFG0_0 */ +#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) +#define UTMIP_OTGPD (1 << 11) +#define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSDISCON_LEVEL_SHIFT 2 +#define UTMIP_HSDISCON_LEVEL_MASK \ + (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) +#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 +#define UTMIP_HSSQUELCH_LEVEL_MASK \ + (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) + /* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_FORCE_PDTRK_POWERDOWN 1 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 #define UTMIP_BIAS_PDTRK_COUNT_MASK \ (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ #define UTMIP_DEBOUNCE_CFG0_SHIFT 0 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
@@ -195,9 +88,6 @@ struct usb_ctlr { /* USBx_UTMIP_BAT_CHRG_CFG0_0 */ #define UTMIP_PD_CHRG 1
-/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) - /* USBx_UTMIP_SPARE_CFG0_0 */ #define FUSE_SETUP_SEL (1 << 3)
@@ -208,23 +98,26 @@ struct usb_ctlr { #define UTMIP_ELASTIC_LIMIT_MASK \ (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
-/* USBx_UTMIP_HSRX_CFG0_1 */ +/* USBx_UTMIP_HSRX_CFG1_0 */ #define UTMIP_HS_SYNC_START_DLY_SHIFT 1 #define UTMIP_HS_SYNC_START_DLY_MASK \ - (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ #define IC_ENB1 (1 << 3)
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) -#define PTS_UTMI 0 +/* PORTSC1, USB1, defined for Tegra20 */ +#define PTS1_SHIFT 31 +#define PTS1_MASK (1 << PTS1_SHIFT) +#define STS1 (1 << 30) + +#define PTS_UTMI 0 #define PTS_RESERVED 1 -#define PTS_ULPI 2 +#define PTS_ULPI 2 #define PTS_ICUSB_SER 3 +#define PTS_HSIC 4
-#define STS (1 << 29) +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ #define WKOC (1 << 22) #define WKDS (1 << 21) #define WKCN (1 << 20) @@ -233,8 +126,19 @@ struct usb_ctlr { #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) +#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 +#define UTMIP_XCVR_HSSLEW_MSB_MASK \ + (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 +#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_SHIFT 0 +#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 +#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ + (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h new file mode 100644 index 0000000..d46048c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/usb.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2013 NVIDIA Corporation + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA114_USB_H_ +#define _TEGRA114_USB_H_ + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7[3]; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) + +#define STS (1 << 28) +#endif /* _TEGRA114_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h new file mode 100644 index 0000000..3d94cc7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/usb.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2013 NVIDIA Corporation + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA20_USB_H_ +#define _TEGRA20_USB_H_ + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[4]; + + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) + +/* PORTSC, USB2, USB3 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) + +#define STS (1 << 29) +#endif /* _TEGRA20_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/usb.h b/arch/arm/include/asm/arch-tegra30/usb.h new file mode 100644 index 0000000..ab9b760 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/usb.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2013 NVIDIA Corporation + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA30_USB_H_ +#define _TEGRA30_USB_H_ + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7[3]; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) + +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) + +#define STS (1 << 28) +#endif /* _TEGRA30_USB_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 8d7a227..f0f81c9 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -46,7 +46,7 @@ #include <asm/arch/emc.h> #endif #ifdef CONFIG_USB_EHCI_TEGRA -#include <asm/arch-tegra/usb.h> +#include <asm/arch/usb.h> #endif #ifdef CONFIG_TEGRA_MMC #include <asm/arch-tegra/tegra_mmc.h> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 554145a..4e73915 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2009-2012 NVIDIA Corporation + * Copyright (c) 2009-2013 NVIDIA Corporation * Copyright (c) 2013 Lucas Stach * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,8 @@ #include <asm-generic/gpio.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/usb.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch/usb.h> #include <usb.h> #include <usb/ulpi.h> #include <libfdt.h> @@ -35,6 +37,11 @@
#include "ehci.h"
+#define USB1_ADDR_MASK 0xFFFF0000 + +#define HOSTPC1_DEVLC 0x84 +#define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) + #ifdef CONFIG_USB_ULPI #ifndef CONFIG_USB_ULPI_VIEWPORT #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ @@ -87,6 +94,9 @@ struct fdt_usb {
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ static unsigned port_count; /* Number of available ports */ +static u32 port_clear_csc; /* Port that needs to clear CSC after Port Reset */ +static unsigned is_T30_compatible; +static unsigned is_T114_compatible;
/* * This table has USB timing parameters for each Oscillator frequency we @@ -129,7 +139,7 @@ static unsigned port_count; /* Number of available ports */ * * 4. The 20 microsecond delay after bias cell operation. */ -static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { +static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, @@ -137,6 +147,22 @@ static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } };
+static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, + { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, + { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } +}; + /* UTMIP Idle Wait Delay */ static const u8 utmip_idle_wait_delay = 17;
@@ -156,13 +182,52 @@ static const u8 utmip_hs_sync_start_delay = 9; void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) { mdelay(50); - if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE) + /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ + if (is_T30_compatible) + *reg |= EHCI_PS_PE; + + if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_clear_csc) return; /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ if (ehci_readl(status_reg) & EHCI_PS_CSC) *reg |= EHCI_PS_CSC; }
+/* + * This ehci_set_usbmode overrides the weak function ehci_set_usbmode + * in "ehci-hcd.c". + */ +void ehci_set_usbmode(int index) +{ + struct fdt_usb *config; + struct usb_ctlr *usbctlr; + uint32_t tmp; + + config = &port[index]; + usbctlr = config->reg; + + tmp = ehci_readl(&usbctlr->usb_mode); + tmp |= USBMODE_CM_HC; + ehci_writel(&usbctlr->usb_mode, tmp); +} + +/* + * This ehci_get_port_speed overrides the weak function ehci_get_port_speed + * in "ehci-hcd.c". + */ +int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) +{ + uint32_t tmp; + uint32_t *reg_ptr; + + if (is_T30_compatible) { + reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC); + tmp = ehci_readl(reg_ptr); + return HOSTPC1_PSPD(tmp); + } else + return PORTSC_PSPD(reg); +} + /* Put the port into host mode */ static void set_host_mode(struct fdt_usb *config) { @@ -209,6 +274,22 @@ void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); }
+static const unsigned *get_pll_timing(void) +{ + const unsigned *timing; + + if (is_T30_compatible) { + if (is_T114_compatible) + timing = T114_usb_pll[clock_get_osc_freq()]; + else + timing = T30_usb_pll[clock_get_osc_freq()]; + } else { + timing = T20_usb_pll[clock_get_osc_freq()]; + } + + return timing; +} + /* set up the UTMI USB controller with the parameters provided */ static int init_utmi_usb_controller(struct fdt_usb *config) { @@ -216,6 +297,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config) int loop_count; const unsigned *timing; struct usb_ctlr *usbctlr = config->reg; + struct clk_rst_ctlr *clkrst; + struct usb_ctlr *usb1ctlr;
clock_enable(config->periph_id);
@@ -232,35 +315,97 @@ static int init_utmi_usb_controller(struct fdt_usb *config) * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { + if (config->dr_mode == DR_MODE_OTG && + fdt_gpio_isvalid(&config->vbus_gpio)) clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, VBUS_SENSE_CTL_MASK, VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); - }
/* * PLL Delay CONFIGURATION settings. The following parameters control * the bring up of the plls. */ - timing = usb_pll[clock_get_osc_freq()]; + timing = get_pll_timing();
- val = readl(&usbctlr->utmip_misc_cfg1); - clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, - timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); - clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, - timing[PARAM_ACTIVE_DELAY_COUNT] << - UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); - writel(val, &usbctlr->utmip_misc_cfg1); + if (!is_T30_compatible) { + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << + UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1);
- /* Set PLL enable delay count and crystal frequency count */ - val = readl(&usbctlr->utmip_pll_cfg1); - clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, - timing[PARAM_ENABLE_DELAY_COUNT] << - UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); - clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, - timing[PARAM_XTAL_FREQ_COUNT] << - UTMIP_XTAL_FREQ_COUNT_SHIFT); - writel(val, &usbctlr->utmip_pll_cfg1); + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + } else { + clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + val = readl(&clkrst->crc_utmip_pll_cfg2); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << + UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &clkrst->crc_utmip_pll_cfg2); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&clkrst->crc_utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &clkrst->crc_utmip_pll_cfg1); + + /* Disable Power Down state for PLL */ + clrbits_le32(&clkrst->crc_utmip_pll_cfg1, + PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | + PLL_ACTIVE_POWERDOWN); + + /* Recommended PHY settings for EYE diagram */ + val = readl(&usbctlr->utmip_xcvr_cfg0); + clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, + 0x4 << UTMIP_XCVR_SETUP_SHIFT); + clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, + 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); + clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, + 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); + writel(val, &usbctlr->utmip_xcvr_cfg0); + clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, + UTMIP_XCVR_TERM_RANGE_ADJ_MASK, + 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); + + /* Some registers can be controlled from USB1 only. */ + if (config->periph_id != PERIPH_ID_USBD) { + clock_enable(PERIPH_ID_USBD); + /* Disable Reset if in Reset state */ + reset_set_enable(PERIPH_ID_USBD, 0); + } + usb1ctlr = (struct usb_ctlr *) + ((u32)config->reg & USB1_ADDR_MASK); + val = readl(&usb1ctlr->utmip_bias_cfg0); + setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); + clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, + 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); + clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, + 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); + writel(val, &usb1ctlr->utmip_bias_cfg0); + + /* Miscellaneous setting mentioned in Programming Guide */ + clrbits_le32(&usbctlr->utmip_misc_cfg0, + UTMIP_SUSPEND_EXIT_ON_EDGE); + }
/* Setting the tracking length time */ clrsetbits_le32(&usbctlr->utmip_bias_cfg1, @@ -308,6 +453,14 @@ static int init_utmi_usb_controller(struct fdt_usb *config) /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+ if (is_T30_compatible) { + if (config->periph_id == PERIPH_ID_USBD) + clrbits_le32(&clkrst->crc_utmip_pll_cfg2, + UTMIP_FORCE_PD_SAMP_A_POWERDOWN); + if (config->periph_id == PERIPH_ID_USB3) + clrbits_le32(&clkrst->crc_utmip_pll_cfg2, + UTMIP_FORCE_PD_SAMP_C_POWERDOWN); + } /* Finished the per-controller init. */
/* De-assert UTMIP_RESET to bring out of reset. */ @@ -336,6 +489,18 @@ static int init_utmi_usb_controller(struct fdt_usb *config) clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+ if (is_T30_compatible) { + /* + * BIAS Pad Power Down is common among all 3 USB + * controllers and can be controlled from USB1 only. + */ + usb1ctlr = (struct usb_ctlr *) + ((u32)config->reg & USB1_ADDR_MASK); + clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); + udelay(25); + clrbits_le32(&usb1ctlr->utmip_bias_cfg1, + UTMIP_FORCE_PDTRK_POWERDOWN); + } return 0; }
@@ -438,7 +603,7 @@ static void config_clock(const u32 timing[]) timing[PARAM_CPCON], timing[PARAM_LFCON]); }
-int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) +static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) { const char *phy, *mode;
@@ -466,6 +631,8 @@ int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) config->enabled = fdtdec_get_is_enabled(blob, node); config->has_legacy_mode = fdtdec_get_bool(blob, node, "nvidia,has-legacy-mode"); + if (config->has_legacy_mode) + port_clear_csc = (u32) config->reg; config->periph_id = clock_decode_periph_id(blob, node); if (config->periph_id == PERIPH_ID_NONE) { debug("%s: Missing/invalid peripheral ID\n", __func__); @@ -483,20 +650,22 @@ int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) return 0; }
-int board_usb_init(const void *blob) +/* + * process_usb_nodes() - Process a list of USB nodes, adding them to our list + * of USB ports. + * @blob: fdt blob + * @node_list: list of nodes to process (any <=0 are ignored) + * @count: number of nodes to process + * + * Return: 0 - ok, -1 - error + */ +static int process_usb_nodes(const void *blob, int node_list[], int count) { struct fdt_usb config; - enum clock_osc_freq freq; - int node_list[USB_PORTS_MAX]; - int node, count, i; - - /* Set up the USB clocks correctly based on our oscillator frequency */ - freq = clock_get_osc_freq(); - config_clock(usb_pll[freq]); + int node, i; + int clk_done = 0;
- /* count may return <0 on error */ - count = fdtdec_find_aliases_for_id(blob, "usb", - COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + port_count = 0; for (i = 0; i < count; i++) { if (port_count == USB_PORTS_MAX) { printf("tegrausb: Cannot register more than %d ports\n", @@ -513,6 +682,10 @@ int board_usb_init(const void *blob) fdt_get_name(blob, node, NULL)); return -1; } + if (!clk_done) { + config_clock(get_pll_timing()); + clk_done = 1; + } config.initialized = 0;
/* add new USB port to the list of available ports */ @@ -522,6 +695,48 @@ int board_usb_init(const void *blob) return 0; }
+int board_usb_init(const void *blob) +{ + int node_list[USB_PORTS_MAX]; + int count, err = 0; + + is_T30_compatible = 0; + is_T114_compatible = 0; + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + if (count) { + err = process_usb_nodes(blob, node_list, count); + if (err) + printf("%s: Error processing T20 USB node!\n", + __func__); + return err; + } + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA114_USB, node_list, USB_PORTS_MAX); + if (count) + is_T114_compatible = 1; + else + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA30_USB, node_list, USB_PORTS_MAX); + if (count) { + /* T114 is also mostly compatible to T30 */ + is_T30_compatible = 1; + err = process_usb_nodes(blob, node_list, count); + if (err) { + if (is_T114_compatible) + printf("%s: Error processing T114 USB node!\n", + __func__); + else + printf("%s: Error processing T30 USB node!\n", + __func__); + } + } + + return err; +} + /** * Start up the given port number (ports are numbered from 0 on each board). * This returns values for the appropriate hccr and hcor addresses to use for @@ -564,6 +779,20 @@ success: usbctlr = config->reg; *hccr = (struct ehci_hccr *)&usbctlr->cap_length; *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; + + if (is_T30_compatible) { + /* Set to Host mode after Controller Reset was done */ + clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, + USBMODE_CM_HC); + /* Select UTMI parallel interface after setting host mode */ + if (config->utmi) { + clrsetbits_le32((char *)&usbctlr->usb_cmd + + HOSTPC1_DEVLC, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32((char *)&usbctlr->usb_cmd + + HOSTPC1_DEVLC, STS); + } + } return 0; }
Add USB EHCI, storage and network support.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Signed-off-by: Jim Lin jilin@nvidia.com --- include/configs/beaver.h | 14 ++++++++++++++ include/configs/cardhu.h | 14 ++++++++++++++ include/configs/dalmore.h | 14 ++++++++++++++ include/configs/tegra114-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 5 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 058da4f..165de13 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -71,6 +71,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20)
+/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 6a99175..fd46083 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -70,6 +70,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20)
+/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 7b68f7c..2723843 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -75,6 +75,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20)
+/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra-common-post.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 721b29c..44e98e5 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -77,4 +77,7 @@ /* Total I2C ports on Tegra114 */ #define TEGRA_I2C_NUM_CONTROLLERS 5
+/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index ed36e11..7ea36be 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -90,4 +90,7 @@ /* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5
+/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA30_COMMON_H_ */
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote:
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin jilin@nvidia.com
Hi Jim,
none of the patches in this series have a changelog that list the changes between v1 to v2. It's customary to include one between the separator and the diffstat (as pointed out below). That makes it easier for people reviewing or testing your patches because they know what to look for or test.
Changelog goes here.
arch/arm/dts/tegra114.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/dts/tegra30.dtsi | 27 +++++++++++++++++++++++++++ board/nvidia/dts/tegra114-dalmore.dts | 7 +++++++ board/nvidia/dts/tegra30-beaver.dts | 6 ++++++ board/nvidia/dts/tegra30-cardhu.dts | 6 ++++++ include/fdtdec.h | 2 ++ lib/fdtdec.c | 2 ++ 7 files changed, 77 insertions(+), 0 deletions(-)
Thierry
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote:
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin jilin@nvidia.com
Hi Jim,
none of the patches in this series have a changelog that list the changes between v1 to v2. It's customary to include one between the separator and the diffstat (as pointed out below). That makes it easier for people reviewing or testing your patches because they know what to look for or test.
Good point. Unless anyone is against this patchset, I'll pick it after I know what changed in this version.
Best regards, Marek Vasut
Dear Jim Lin,
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
I'd like to get ACK from someone with the actual hardware.
btw. How usable is the cardhu with current U-Boot ? That's the ASUS TF700, right? How can I install U-Boot on it, is there any howto?
Best regards, Marek Vasut
On Sun, 2013-06-16 at 03:46 +0800, Marek Vasut wrote:
Dear Jim Lin,
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
I'd like to get ACK from someone with the actual hardware.
btw. How usable is the cardhu with current U-Boot ? That's the ASUS TF700, right? How can I install U-Boot on it, is there any howto?
I know nothing about ASUS TF700. The T30-Cardhu board I have is a demo board.
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On Sat, Jun 15, 2013 at 09:46:19PM +0200, Marek Vasut wrote:
Dear Jim Lin,
Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
I'd like to get ACK from someone with the actual hardware.
btw. How usable is the cardhu with current U-Boot ? That's the ASUS TF700, right? How can I install U-Boot on it, is there any howto?
I don't think Cardhu and TF700 are the same hardware. I'm not familiar with the TF700, but if you have access to the recovery mode you should be able to put mainline U-Boot on it using documentation found here:
ftp://download.nvidia.com/tegra-public-appnotes/index.html
There's also a pretty new tool to perform almost all of the required steps automatically:
https://github.com/NVIDIA/tegra-uboot-flasher-scripts
You should follow the instructions in the README-developer.txt to get started.
But given that the hardware might not be the same as Cardhu, I'm not sure you can actually run mainline U-Boot on it. I don't suppose the schematics for the TF700 are available anywhere? =)
Thierry
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@ status = "okay"; bus-width = <8>; };
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5, USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into this:
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed something strange. When I try to use USB, I get this:
Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
So no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however, the storage device is detected:
Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
Any idea what might be going on here?
Thierry
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>;};
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5, USB13_VBUS_PULLUP */This doesn't work for me on Beaver. I need to turn the above line into this:
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed something strange. When I try to use USB, I get this:
Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
So no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however, the storage device is detected:
Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
Best regards, Marek Vasut
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>;};
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5, USB13_VBUS_PULLUP */This doesn't work for me on Beaver. I need to turn the above line into this:
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed something strange. When I try to use USB, I get this:
Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
So no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however, the storage device is detected:
Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Thierry
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>;};
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this: nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this: Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundSo no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however,
the storage device is detected: Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundAny idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
Best regards, Marek Vasut
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>;};
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this: nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this: Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundSo no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however,
the storage device is detected: Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundAny idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches:
0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>;};
- usb@7d008000 {
nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this: nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this: Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundSo no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however,
the storage device is detected: Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundAny idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches:
0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
Best regards, Marek Vasut
On 06/17/2013 02:39 PM, Marek Vasut wrote:
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
> diff --git a/board/nvidia/dts/tegra30-beaver.dts > b/board/nvidia/dts/tegra30-beaver.dts
[...]
> @@ -68,4 +69,9 @@ > > status = "okay"; > bus-width = <8>; > > }; > > + > + usb@7d008000 { > + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this: nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this: Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundSo no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however,
the storage device is detected: Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundAny idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches:
0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
The problem is definitely caused by 020bbcb "usb: hub: Power-cycle on root-hub ports"; I reverted just that locally and it fixed my problems.
Dear Stephen Warren,
On 06/17/2013 02:39 PM, Marek Vasut wrote:
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
> On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: > [...] > >> diff --git a/board/nvidia/dts/tegra30-beaver.dts >> b/board/nvidia/dts/tegra30-beaver.dts > > [...] > >> @@ -68,4 +69,9 @@ >> >> status = "okay"; >> bus-width = <8>; >> >> }; >> >> + >> + usb@7d008000 { >> + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
> This doesn't work for me on Beaver. I need to turn the above line > into > > this: > nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ > > PDD4 is the correct GPIO according to the schematics and the pin is > high-active. Also as far as I can tell, 3 is not a meaningful value > for the U-Boot GPIO bindings. Only the value 1 (low-active) is > used. > > With that change applied on top of your patches I can see that a > USB flash drive connected to USB3 is indeed powered. However I > noticed > > something strange. When I try to use USB, I get this: > Tegra30 (Beaver) # usb start > (Re)start USB... > USB0: set_host_mode: GPIO 236 high > USB EHCI 1.00 > scanning bus 0 for devices... 1 USB Device(s) found > > scanning usb for storage devices... 0 Storage Device(s) > found scanning usb for ethernet devices... 0 Ethernet > Device(s) found > > So no storage device is detected, even though a USB flash drive is > connected and powered properly. If I repeat the same command, > however, > > the storage device is detected: > Tegra30 (Beaver) # usb reset > (Re)start USB... > USB0: set_host_mode: GPIO 236 high > USB EHCI 1.00 > scanning bus 0 for devices... 2 USB Device(s) found > > scanning usb for storage devices... 1 Storage Device(s) > found scanning usb for ethernet devices... 0 Ethernet > Device(s) found > > Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches: 0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
The problem is definitely caused by 020bbcb "usb: hub: Power-cycle on root-hub ports"; I reverted just that locally and it fixed my problems.
Even this one ? Did we already get any reply from the patch author?
Best regards, Marek Vasut
On 06/18/2013 05:29 AM, Marek Vasut wrote:
Dear Stephen Warren,
On 06/17/2013 02:39 PM, Marek Vasut wrote:
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote: > Dear Thierry Reding, > >> On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: >> [...] >> >>> diff --git a/board/nvidia/dts/tegra30-beaver.dts >>> b/board/nvidia/dts/tegra30-beaver.dts >> >> [...] >> >>> @@ -68,4 +69,9 @@ >>> >>> status = "okay"; >>> bus-width = <8>; >>> >>> }; >>> >>> + >>> + usb@7d008000 { >>> + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
>> This doesn't work for me on Beaver. I need to turn the above line >> into >> >> this: >> nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ >> >> PDD4 is the correct GPIO according to the schematics and the pin is >> high-active. Also as far as I can tell, 3 is not a meaningful value >> for the U-Boot GPIO bindings. Only the value 1 (low-active) is >> used. >> >> With that change applied on top of your patches I can see that a >> USB flash drive connected to USB3 is indeed powered. However I >> noticed >> >> something strange. When I try to use USB, I get this: >> Tegra30 (Beaver) # usb start >> (Re)start USB... >> USB0: set_host_mode: GPIO 236 high >> USB EHCI 1.00 >> scanning bus 0 for devices... 1 USB Device(s) found >> >> scanning usb for storage devices... 0 Storage Device(s) >> found scanning usb for ethernet devices... 0 Ethernet >> Device(s) found >> >> So no storage device is detected, even though a USB flash drive is >> connected and powered properly. If I repeat the same command, >> however, >> >> the storage device is detected: >> Tegra30 (Beaver) # usb reset >> (Re)start USB... >> USB0: set_host_mode: GPIO 236 high >> USB EHCI 1.00 >> scanning bus 0 for devices... 2 USB Device(s) found >> >> scanning usb for storage devices... 1 Storage Device(s) >> found scanning usb for ethernet devices... 0 Ethernet >> Device(s) found >> >> Any idea what might be going on here? > > Try waiting a little after setting the GPIO maybe? The drive might > need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches: 0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
The problem is definitely caused by 020bbcb "usb: hub: Power-cycle on root-hub ports"; I reverted just that locally and it fixed my problems.
Even this one ? Did we already get any reply from the patch author?
Oh, it's possible this is a different symptom, although I'd wager since it's narrowed down to a patch that's known to cause another problem already, it's the same patch that caused it, but yes that should be verified explicitly.
No, I haven't heard anything at all from the patch author.
On Mon, Jun 17, 2013 at 10:39:12PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
> diff --git a/board/nvidia/dts/tegra30-beaver.dts > b/board/nvidia/dts/tegra30-beaver.dts
[...]
> @@ -68,4 +69,9 @@ > > status = "okay"; > bus-width = <8>; > > }; > > + > + usb@7d008000 { > + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this: nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this: Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundSo no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however,
the storage device is detected: Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) foundAny idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches:
0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
I should repeat that things work fine for a more recent flash drive, so it doesn't look all that bad. Bisecting will be difficult because the patches for Tegra30 haven't been merged upstream yet. Also I can't tell for sure if this particular flash driver ever worked as expected since I've never tried it before.
Given that I have limited time over the next few weeks, I'll see if I can come up with a successful bisection. If I do I'll let you know.
Thierry
Dear Thierry Reding,
On Mon, Jun 17, 2013 at 10:39:12PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
> On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: > [...] > > > diff --git a/board/nvidia/dts/tegra30-beaver.dts > > b/board/nvidia/dts/tegra30-beaver.dts > > [...] > > > @@ -68,4 +69,9 @@ > > > > status = "okay"; > > bus-width = <8>; > > > > }; > > > > + > > + usb@7d008000 { > > + nvidia,vbus-gpio = <&gpio 61 3>; /* PH5,
USB13_VBUS_PULLUP */
> This doesn't work for me on Beaver. I need to turn the above > line into > > this: > nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ > > PDD4 is the correct GPIO according to the schematics and the > pin is high-active. Also as far as I can tell, 3 is not a > meaningful value for the U-Boot GPIO bindings. Only the value > 1 (low-active) is used. > > With that change applied on top of your patches I can see that > a USB flash drive connected to USB3 is indeed powered. However > I noticed > > something strange. When I try to use USB, I get this: > Tegra30 (Beaver) # usb start > (Re)start USB... > USB0: set_host_mode: GPIO 236 high > USB EHCI 1.00 > scanning bus 0 for devices... 1 USB Device(s) found > > scanning usb for storage devices... 0 Storage Device(s) > found scanning usb for ethernet devices... 0 Ethernet > Device(s) found > > So no storage device is detected, even though a USB flash drive > is connected and powered properly. If I repeat the same > command, however, > > the storage device is detected: > Tegra30 (Beaver) # usb reset > (Re)start USB... > USB0: set_host_mode: GPIO 236 high > USB EHCI 1.00 > scanning bus 0 for devices... 2 USB Device(s) found > > scanning usb for storage devices... 1 Storage Device(s) > found scanning usb for ethernet devices... 0 Ethernet > Device(s) found > > Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Try reverting 020bbcb "usb: hub: Power-cycle on root-hub ports" ... there's a thread in the ML that it caused issues.
I reverted the following two patches: 0bf796f usb: hub: Parallelize power-cycling of root-hub ports 020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it didn't change anything regarding the problem I was seeing.
Thierry
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
I should repeat that things work fine for a more recent flash drive, so it doesn't look all that bad. Bisecting will be difficult because the patches for Tegra30 haven't been merged upstream yet. Also I can't tell for sure if this particular flash driver ever worked as expected since I've never tried it before.
Given that I have limited time over the next few weeks, I'll see if I can come up with a successful bisection. If I do I'll let you know.
You can try checking 2013.01, I recall merging some usb-storage related changes after that release.
Best regards, Marek Vasut
On 06/18/2013 04:58 AM, Thierry Reding wrote:
On Mon, Jun 17, 2013 at 10:39:12PM +0200, Marek Vasut wrote:
...
Ok, this looks ugly and calls for a bisect. Can you check it ? I'll try to test if USB works for me on some EHCI-enabled device.
I should repeat that things work fine for a more recent flash drive, so it doesn't look all that bad. Bisecting will be difficult because the patches for Tegra30 haven't been merged upstream yet. Also I can't tell for sure if this particular flash driver ever worked as expected since I've never tried it before.
You can easily cherry-pick changes on top of each commit while you're doing a bisect to add the board support in if you need; just be careful to say "git bisect good|bad the_commit_which_git_bisect_told_me_to_test" where "the_commit_which_git_bisect_told_me_to_test" is before the cherry-picks you did.
Doesn't the problem happen on a Tegra20 board though; it might be easier to test there since no cherry-picks would be needed.
On 06/16/2013 04:30 AM, Thierry Reding wrote:
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote: [...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = "okay"; bus-width = <8>; };
- usb@7d008000 { + nvidia,vbus-gpio = <&gpio 61 3>; /*
PH5, USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into this:
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is high-active. Also as far as I can tell, 3 is not a meaningful value for the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB flash drive connected to USB3 is indeed powered. However I noticed something strange. When I try to use USB, I get this:
Tegra30 (Beaver) # usb start (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
So no storage device is detected, even though a USB flash drive is connected and powered properly. If I repeat the same command, however, the storage device is detected:
Tegra30 (Beaver) # usb reset (Re)start USB... USB0: set_host_mode: GPIO 236 high USB EHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found
Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need some time to settle.
I can make it work on the first invocation of "usb start" by adding a rather long mdelay() at the very end of ehci_hcd_init() in the Tegra EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle, and keeping it in the driver probably isn't a good idea. Furthermore I cannot reproduce the same issue with a newer flash drive, which works fine with no additional delays.
Interesting. I see this exact same issue on Dalmore (Tegra114) with my SD card reader too. I tried inserting a 1000ms delay at the end of ehci_hcd_init() and that solves the problem for me too.
I already have 020bbcb "usb: hub: Power-cycle on root-hub ports" reverted locally, although when I reverted it, IIRC there was a conflict, so it's possible I just hacked around that and ended up reverting all/part of 0bf796f "usb: hub: Parallelize power-cycling of root-hub ports" too; see my branch at:
git://github.com:swarren/u-boot.git mainline_dev
... if you want to see the revert (about 8 commits down).
Another interesting aspect to this: An NVIDIA intern is trying to get the Linux Tegra USB driver working on Tegra114. All the devices we've tried except this SD card reader work fine with that driver, so there's obviously something quirky with it. However, once I've run "usb start" twice in U-Boot, or added the mdelay() to U-Boot and run "usb start" once in U-Boot, then the kernel driver works with the problematic SD card reader...
participants (4)
-
Jim Lin -
Marek Vasut -
Stephen Warren -
Thierry Reding