From: John Rigby john.rigby@linaro.org

Signed-off-by: John Rigby john.rigby@linaro.org --- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 2 + tools/mkimage.h | 1 + tools/omapimage.c | 229 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/omapimage.h | 50 ++++++++++++ 7 files changed, 286 insertions(+), 0 deletions(-) create mode 100644 tools/omapimage.c create mode 100644 tools/omapimage.h

diff --git a/common/image.c b/common/image.c index f63a2ff..4198d76 100644 --- a/common/image.c +++ b/common/image.c @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, + { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP CH/GP Boot Image",}, { -1, "", "", }, };

diff --git a/include/image.h b/include/image.h index 005e0d2..f74e2b9 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ +#define IH_TYPE_OMAPIMAGE 11 /* TI OMAP Config Header Image */

/* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 623f908..a1c4ed7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o NOPED_OBJ_FILES-y += imximage.o +NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o @@ -180,6 +181,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)fit_image.o \ $(obj)image.o \ $(obj)imximage.o \ + $(obj)omapimage.o \ $(obj)kwbimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index f5859d7..ec6d75e 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -155,6 +155,8 @@ main (int argc, char **argv) init_imx_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); + /* Init TI OMAP Boot image generation/list support */ + init_omap_image_type(); /* Init Default image generation/list support */ init_default_image_type ();

diff --git a/tools/mkimage.h b/tools/mkimage.h index 9033a7d..3b49645 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -143,5 +143,6 @@ void init_kwb_image_type (void); void init_imx_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); +void init_omap_image_type(void);

#endif /* _MKIIMAGE_H_ */ diff --git a/tools/omapimage.c b/tools/omapimage.c new file mode 100644 index 0000000..67fa056 --- /dev/null +++ b/tools/omapimage.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby john.rigby@linaro.org + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "omapimage.h" + +/* Header size is CH header rounded up to 512 bytes plus GP header */ +#define OMAP_CH_HDR_SIZE 512 +#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) + +static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; + +static int omapimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_OMAPIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +/* + * Only the simplest image type is currently supported: + * TOC pointing to CHSETTINGS + * TOC terminator + * CHSETTINGS + * + * padding to OMAP_CH_HDR_SIZE bytes + * + * gp header + * size + * load_addr + */ +static int valid_gph_size(uint32_t size) +{ + return size; +} + +static int valid_gph_load_addr(uint32_t load_addr) +{ + return load_addr; +} + +static int omapimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + if (!offset || !size) + return -1; + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + return -1; + toc++; + } + if (!valid_gph_size(gph->size)) + return -1; + if (!valid_gph_load_addr(gph->load_addr)) + return -1; + + return 0; +} + +static void omapimage_print_section(struct ch_settings *chs) +{ + switch (chs->section_key) { + case KEY_CHSETTINGS: + printf("CHSETTINGS (%x) " + "valid:%x " + "version:%x " + "reserved:%x " + "flags:%x\n", + chs->section_key, + chs->valid, + chs->version, + chs->reserved, + chs->flags); + break; + default: + printf("UNKNOWNKEY (%x) " + "valid:%x " + "version:%x " + "reserved:%x " + "flags:%x\n", + chs->section_key, + chs->valid, + chs->version, + chs->reserved, + chs->flags); + break; + } +} + +static void omapimage_print_header(const void *ptr) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + exit(EXIT_FAILURE); + + printf("Section %s offset %x length %x\n", + toc->section_name, + toc->section_offset, + toc->section_size); + + omapimage_print_section((struct ch_settings *)(ptr+offset)); + toc++; + } + + if (!valid_gph_size(gph->size)) { + fprintf(stderr, + "Error: invalid image size %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + if (!valid_gph_load_addr(gph->load_addr)) { + fprintf(stderr, + "Error: invalid image load address %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + printf("GP Header: Size %x LoadAddr %x\n", + gph->size, gph->load_addr); +} + +static int toc_offset(void *hdr, void *member) +{ + return member - hdr; +} + +static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct ch_settings *chs = (struct ch_settings *) + (ptr + 2 * sizeof(*toc)); + struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE); + + toc->section_offset = toc_offset(ptr, chs); + toc->section_size = sizeof(struct ch_settings); + strcpy((char *)toc->section_name, "CHSETTINGS"); + + chs->section_key = KEY_CHSETTINGS; + chs->valid = 0; + chs->version = 1; + chs->reserved = 0; + chs->flags = 0; + + toc++; + memset(toc, 0xff, sizeof(*toc)); + + gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; + gph->load_addr = params->addr; +} + +int omapimage_check_params(struct mkimage_params *params) +{ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +/* + * omapimage parameters + */ +static struct image_type_params omapimage_params = { + .name = "TI OMAP CH/GP Boot Image support", + .header_size = OMAP_FILE_HDR_SIZE, + .hdr = (void *)&omapimage_header, + .check_image_type = omapimage_check_image_types, + .verify_header = omapimage_verify_header, + .print_header = omapimage_print_header, + .set_header = omapimage_set_header, + .check_params = omapimage_check_params, +}; + +void init_omap_image_type(void) +{ + mkimage_register(&omapimage_params); +} diff --git a/tools/omapimage.h b/tools/omapimage.h new file mode 100644 index 0000000..7ff5404 --- /dev/null +++ b/tools/omapimage.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author John Rigby john.rigby@linaro.org + * Based on TI's signGP.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAPIMAGE_H_ +#define _OMAPIMAGE_H_ + +struct ch_toc { + uint32_t section_offset; + uint32_t section_size; + uint8_t unused[12]; + uint8_t section_name[12]; +} __attribute__ ((__packed__)); + +struct ch_settings { + uint32_t section_key; + uint8_t valid; + uint8_t version; + uint16_t reserved; + uint32_t flags; +} __attribute__ ((__packed__)); + +struct gp_header { + uint32_t size; + uint32_t load_addr; +} __attribute__ ((__packed__)); + +#define KEY_CHSETTINGS 0xC0C0C0C1 +#endif /* _OMAPIMAGE_H_ */

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/omap4/board.c | 35 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/omap4.h | 17 +++++++++----- arch/arm/include/asm/armv7.h | 31 +++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/armv7.h

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index fcd29a7..7583a0d 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -28,6 +28,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <asm/armv7.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> #include <asm/sizes.h> @@ -127,3 +128,37 @@ int arch_cpu_init(void) set_muxconf_regs(); return 0; } + +static u32 cortex_a9_rev(void) +{ + + unsigned int rev; + + /* Read Main ID Register (MIDR) */ + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); + + return rev; +} + +u32 omap4_revision(void) +{ + if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1) + return OMAP4430_ES2_1; + else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2) + return OMAP4430_ES2_2; + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int rev = cortex_a9_rev(); + + switch (rev) { + case MIDR_CORTEX_A9_R0P1: + return OMAP4430_ES1_0; + case MIDR_CORTEX_A9_R1P2: + return OMAP4430_ES2_0; + default: + return OMAP4430_SILICON_ID_INVALID; + } +} diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index a30bb33..1f88732 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -51,6 +51,11 @@ #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)

+/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE (CTRL_BASE + 0x204) + +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) @@ -121,11 +126,11 @@ struct s32ktimer { /* Temporary SRAM stack used while low level init is done */ #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END

-/* - * OMAP4 real hardware: - * TODO: Change this to the IDCODE in the hw regsiter - */ -#define CPU_OMAP4430_ES10 1 -#define CPU_OMAP4430_ES20 2 +/* Silicon revisions */ +#define OMAP4430_SILICON_ID_INVALID 0 +#define OMAP4430_ES1_0 1 +#define OMAP4430_ES2_0 2 +#define OMAP4430_ES2_1 3 +#define OMAP4430_ES2_2 4

#endif diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h new file mode 100644 index 0000000..6c24a80 --- /dev/null +++ b/arch/arm/include/asm/armv7.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef ARMV7_H +#define ARMV7_H + +#define MIDR_CORTEX_A9_R0P1 0x410FC091 +#define MIDR_CORTEX_A9_R1P2 0x411FC092 + +#endif /* ARMV7_H */

_bss_start_ofs is used in start.S to indicate end of copied image. This may not be correct when we have a discontiguous memory map. For instance, .bss may be placed in SDRAM for some SPLS while rest of the image is placed in SRAM.

Define a new label in linker script to indicate the end of the image copied during relocation and use it appropriately in start.S.

Also, add a new label to indicate the end of flash image. This will be useful in identifying the size of flash image

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/start.S | 6 +++++- arch/arm/cpu/armv7/u-boot.lds | 4 ++++ 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 3618190..8215d26 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -77,6 +77,10 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start

+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word _end - _start @@ -172,7 +176,7 @@ stack_setup: beq clear_bss /* skip relocation */ #endif mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */

copy_loop: diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index 5725c30..c3ad587 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -55,6 +55,8 @@ SECTIONS

. = ALIGN(4);

+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -66,6 +68,8 @@ SECTIONS *(.dynsym) }

+ __flash_image_end = .; + .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; *(.bss)

Changes for supporting SPL

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/start.S | 36 +++++++++++++++++++++++++----------- 1 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 8215d26..f5f08d9 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -42,7 +42,16 @@ _start: b reset ldr pc, _not_used ldr pc, _irq ldr pc, _fiq - +#ifdef CONFIG_PRELOADER +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -51,6 +60,8 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_PRELOADER */ + .global _end_vect _end_vect:

@@ -171,10 +182,9 @@ stack_setup: mov sp, r4

adr r0, _start -#ifndef CONFIG_PRELOADER cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ -#endif mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -224,6 +234,15 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_PRELOADER */

clear_bss: ldr r0, _bss_start_ofs @@ -237,7 +256,6 @@ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */

/* * We are done. Do not return, instead branch to second part of board @@ -257,13 +275,6 @@ jump_2_ram: _board_init_r_ofs: .word board_init_r - _start

-_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start - /************************************************************************* * * CPU_init_critical registers @@ -300,6 +311,8 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller + +#ifndef CONFIG_PRELOADER /* ************************************************************************* * @@ -488,3 +501,4 @@ fiq: bl do_fiq

#endif +#endif /* CONFIG_PRELOADER */

Adapted from: nand_spl/board/samsung/smdk6400/Makefile

- Add the SPL makefile for OMAP4430 SDP - Add the necessary CONFIG flags in the board config file

Signed-off-by: Aneesh V aneesh@ti.com --- board/ti/sdp4430/config.mk | 3 +- include/configs/omap4_sdp4430.h | 19 ++++++ spl/board/ti/sdp4430/Makefile | 120 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+), 1 deletions(-) create mode 100644 spl/board/ti/sdp4430/Makefile

diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk index 33901a7..c62965d 100644 --- a/board/ti/sdp4430/config.mk +++ b/board/ti/sdp4430/config.mk @@ -28,4 +28,5 @@ # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 # (mem base + reserved)

-CONFIG_SYS_TEXT_BASE = 0x80e80000 +# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM +CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 9a8bb73..5b20841 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -122,7 +122,9 @@

/* USB device configuration */ #define CONFIG_USB_DEVICE 1 +#ifndef CONFIG_PRELOADER #define CONFIG_USB_TTY 1 +#endif #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1

/* Flash */ @@ -240,4 +242,21 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)

+/* Defines for Clock init */ +#define CONFIG_SYS_OMAP4_ABE_SYSCK + +/* Defines for SDRAM init */ +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 +#define CONFIG_SYS_EMIF_UPDATE_TIMINGS 1 +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 +#define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ +#define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + #endif /* __CONFIG_H */ diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile new file mode 100644 index 0000000..dd56a40 --- /dev/null +++ b/spl/board/ti/sdp4430/Makefile @@ -0,0 +1,120 @@ +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +splobj := $(OBJTREE)/spl/ +include $(TOPDIR)/config.mk +SOBJS = +COBJS = + +# armv7 +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ + +$(obj)syslib.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@ + +SOBJS += start.o +COBJS += syslib.o + +# omap-common +$(obj)timer.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@ + +$(obj)reset.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@ + +$(obj)spl-omap.c: + @rm -f $@ + @ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@ + +SOBJS += reset.o +COBJS += timer.o spl-omap.o + +$(OBJTREE)/MLO: $(splobj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage \ + -a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@ + +LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds + +# omap4 +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@ + +$(obj)omap4_mux_data.h: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@ + +$(obj)board.c:$(obj)omap4_mux_data.h + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ + +SOBJS += lowlevel_init.o +COBJS += board.o + +# rules +LDPPFLAGS += -include $(TOPDIR)/include/config.h +LDSCRIPT = $(splobj)u-boot-spl-generated.lds +$(LDSCRIPT): $(LDSCRIPT_SOURCE) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +LDFLAGS = -Bstatic -T $(LDSCRIPT) \ + $(PLATFORM_LDFLAGS) --gc-sections +AFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 +CFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \ + -fdata-sections -march=armv7-a -mthumb +PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \ + -print-libgcc-file-name`) -lgcc + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/spl/board/$(BOARDDIR) + +$(splobj)u-boot-spl.bin: $(splobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(splobj)u-boot-spl: $(OBJS) $(LDSCRIPT) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + $(PLATFORM_LIBGCC) \ + -Map $(splobj)u-boot-spl.map \ + -o $(splobj)u-boot-spl + +ALL = $(OBJTREE)/MLO +all: $(obj).depend $(ALL) + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend

The basic hardware init of OMAP4(s_init()) can happen in 4 different contexts: 1. SPL running from SRAM 2. U-Boot running from FLASH 3. Non-XIP U-Boot loaded to SDRAM by SPL 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the Configuration Header feature

What level of hw initialization gets done depends on this context. Add a utility function to find this context.

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/include/asm/arch-omap4/sys_proto.h | 47 +++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 6 +++ 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ce86b36..19da2e1 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -38,6 +38,53 @@ void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long);

+static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && + (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * Configuration Header is not supported yet, so u-boot init running + * from SDRAM implies that it was loaded by SPL. When this situation + * changes one of these approaches could be taken: + * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known + * location. + * ii. Check the OPP. CH can support only 50% OPP while SPL initializes + * the DPLLs at 100% OPP. + */ + return running_from_sdram(); +} +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap4_hw_init_context(void) +{ +#ifdef CONFIG_PRELOADER + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH; + else + return OMAP_INIT_CONTEXT_XIP_UBOOT; +#endif +} + extern const struct omap_sysinfo sysinfo;

#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 95116f4..50247af 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -65,6 +65,12 @@ /* Magic number passed from SPL to U-Boot */ #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER 0xDEADBEEF

+/* HW Init Context */ +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_XIP_UBOOT 1 +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH 3 + u32 omap_boot_device(void); u32 omap_boot_mode(void); void preloader_console_init(void);

sync up mux settings with the latest in x-loader

Signed-off-by: Aneesh V aneesh@ti.com --- board/ti/panda/panda_mux_data.h | 89 ++++++++++++++++++----------------- board/ti/sdp4430/sdp4430_mux_data.h | 29 ++++++----- 2 files changed, 61 insertions(+), 57 deletions(-)

diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 8bb7fe5..16cc0ad 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -23,11 +23,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef _SDP4430_MUX_DATA_H +#define _SDP4430_MUX_DATA_H

-#ifndef _PANDA_MUX_DATA_H_ -#define _PANDA_MUX_DATA_H_ - -#include <asm/io.h> #include <asm/arch/mux_omap4.h>

const struct pad_conf_entry core_padconf_array_non_essential[] = { @@ -45,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ {GPMC_A20, (IEN | M3)}, /* gpio_44 */ {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ {GPMC_A24, (PTD | M3)}, /* gpio_48 */ {GPMC_A25, (PTD | M3)}, /* gpio_49 */ @@ -59,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ {C2C_DATA14, (M1)}, /* dsi2_te0 */ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ @@ -86,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ @@ -106,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ - {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ @@ -143,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {UART4_RX, (IEN | M0)}, /* uart4_rx */ {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ @@ -157,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ + {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ + {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ @@ -173,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {SYS_BOOT1, (M3)}, /* gpio_185 */ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ {SYS_BOOT4, (M3)}, /* gpio_188 */ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ @@ -205,25 +203,28 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { };

const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ - {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ };

-#endif /* _PANDA_MUX_DATA_H_ */ +#endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index e6081dc..16cc0ad 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -84,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ @@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ - {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ @@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {UART4_RX, (IEN | M0)}, /* uart4_rx */ {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ @@ -173,11 +173,11 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {SYS_BOOT1, (M3)}, /* gpio_185 */ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ {SYS_BOOT4, (M3)}, /* gpio_188 */ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ @@ -222,6 +222,9 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ };

#endif /* _SDP4430_MUX_DATA_H */

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/omap4/Makefile | 3 + arch/arm/cpu/armv7/omap4/board.c | 2 +- arch/arm/cpu/armv7/omap4/emif.c | 281 +++++++++++ arch/arm/cpu/armv7/omap4/sdram_elpida.c | 118 +++++ arch/arm/include/asm/arch-omap4/emif.h | 719 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/omap4.h | 11 + arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + include/configs/omap4_sdp4430.h | 5 - spl/board/ti/sdp4430/Makefile | 10 +- 9 files changed, 1143 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap4/emif.c create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 6154e86..d9714fe 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += mem.o COBJS += sys_info.o COBJS += clocks.o +COBJS += emif.o +COBJS += sdram_elpida.o +

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 62a59ad..89b1213 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -109,6 +109,7 @@ void s_init(void) #ifdef CONFIG_PRELOADER preloader_console_init(); #endif + sdram_init(); }

/* @@ -169,7 +170,6 @@ u32 sdram_size(void) */ int dram_init(void) { - gd->ram_size = sdram_size();

return 0; diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c new file mode 100644 index 0000000..ee77743 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -0,0 +1,281 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/emif.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> + +static inline u32 emif_num(u32 base) +{ + if (base == OMAP44XX_EMIF1) + return 1; + else if (base == OMAP44XX_EMIF2) + return 2; + else + return 0; +} + +static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) +{ + u32 mr; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + if (omap4_revision() == OMAP4430_ES2_0) + mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); + else + mr = readl(&emif->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), + cs, mr_addr, mr); + return mr; +} + +static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); +} +void emif_reset_phy(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 iodft; + + iodft = readl(&emif->emif_iodft_tlgc); + iodft |= OMAP44XX_REG_RESET_PHY_MASK; + writel(iodft, &emif->emif_iodft_tlgc); +} + +static void do_lpddr2_init(u32 base, u32 cs) +{ + u32 mr_addr; + + /* Wait till device auto initialization is complete */ + while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); + sdelay(10); + set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); + set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + /* + * Enable refresh along with writing MR2 + * Encoding of RL in MR2 is (RL - 2) + */ + mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; + set_mr(base, cs, mr_addr, RL_FINAL - 2); +} + +static void lpddr2_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 nvm; + + /* Not NVM */ + nvm = readl(&emif->emif_lpddr2_nvm_config); + nvm &= (~OMAP44XX_REG_CS1NVMEN_MASK); + writel(nvm, &emif->emif_lpddr2_nvm_config); + /* + * Set the SDRAM_CONFIG and PHY_CTRL for the + * un-locked frequency & default RL + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + do_lpddr2_init(base, CS0); + if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) + do_lpddr2_init(base, CS1); + + writel(regs->sdram_config, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); +} + +static void emif_update_timings(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); + if (omap4_revision() == OMAP4430_ES1_0) { + /* ES1 bug EMIF should be in force idle during freq_update */ + writel(0, &emif->emif_pwr_mgmt_ctrl); + } else { + writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); + writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); + } + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + /* + * Workaround: + * In a specific situation, the OCP interface between the DMM and + * EMIF may hang. + * 1. A TILER port is used to perform 2D burst writes of + * width 1 and height 8 + * 2. ELLAn port is used to perform reads + * 3. All accesses are routed to the same EMIF controller + * + * Work around to avoid this issue REG_SYS_THRESH_MAX value should + * be kept higher than default 0x7. As per recommondation 0x0A will + * be used for better performance with REG_LL_THRESH_MAX = 0x00 + */ + if (omap4_revision() == OMAP4430_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00, + &emif->emif_l3_config); + } +} + +static void do_sdram_init(u32 base) +{ + const struct emif_regs *regs, *tmp_regs; + u32 in_sdram, emif_nr; + + in_sdram = running_from_sdram(); + emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; + + emif_get_reg_dump(&regs, &tmp_regs); + regs = (emif_nr == 1) ? regs : tmp_regs; + + /* + * Initializing the LPDDR2 device can not happen from SDRAM. + * Changing the timing registers in EMIF can happen(going from one + * OPP to another) + */ + if (!in_sdram) + lpddr2_init(base, regs); + + /* Write to the shadow registers */ + emif_update_timings(base, regs); +} + +void sdram_init_pads(void) +{ + u32 lpddr2io; + u32 omap4_rev = omap4_revision(); + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + return; /* Post ES2.1 reset values will work */ + + writel(lpddr2io, CONTROL_LPDDR2IO1_0); + writel(lpddr2io, CONTROL_LPDDR2IO1_1); + writel(lpddr2io, CONTROL_LPDDR2IO1_2); + writel(lpddr2io, CONTROL_LPDDR2IO2_0); + writel(lpddr2io, CONTROL_LPDDR2IO2_1); + writel(lpddr2io, CONTROL_LPDDR2IO2_2); + + writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2); +} + +static void emif_post_init_config(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 omap4_rev = omap4_revision(); + + /* reset phy on ES2.0 */ + if (omap4_rev == OMAP4430_ES2_0) + emif_reset_phy(base); + + /* Put EMIF back in smart idle on ES1.0 */ + if (omap4_rev == OMAP4430_ES1_0) + writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); +} + +static void dmm_init(u32 base) +{ + const struct dmm_lisa_map_regs *lisa_map_regs; + + emif_get_dmm_regs(&lisa_map_regs); + + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)base; + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); +} + +/* + * SDRAM initialization: + * SDRAM initialization has two parts: + * 1. Configuring the SDRAM device + * 2. Update the AC timings related parameters in the EMIF module + * (1) should be done only once and should not be done while we are + * running from SDRAM. + * (2) can and should be done more than once if OPP changes. + * Particularly, this may be needed when we boot without SPL and + * and using Configuration Header(CH). ROM code supports only at 50% OPP + * at boot (low power boot). So u-boot has to switch to OPP100 and update + * the frequency. So, + * Doing (1) and (2) makes sense - first time initialization + * Doing (2) and not (1) makes sense - OPP change (when using CH) + * Doing (1) and not (2) doen't make sense + * See do_sdram_init() for the details + */ +void sdram_init(void) +{ + u32 in_sdram; + + in_sdram = running_from_sdram(); + + if (!in_sdram) { + sdram_init_pads(); + bypass_dpll(CM_CLKMODE_DPLL_CORE); + } + + do_sdram_init(OMAP44XX_EMIF1); + do_sdram_init(OMAP44XX_EMIF2); + + if (!in_sdram) { + dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); + emif_post_init_config(OMAP44XX_EMIF1); + emif_post_init_config(OMAP44XX_EMIF2); + } + + /* for the shadow registers to take effect */ + freq_update_core(); +} diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c new file mode 100644 index 0000000..37e808c --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -0,0 +1,118 @@ +/* + * Timing and Organization details of the Elpida parts used in OMAP4 + * SDPs and Panda + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/emif.h> +#include <asm/arch/sys_proto.h> + +static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x0000030c, + .sdram_tim1 = 0x08648311, + .sdram_tim2 = 0x101b06ca, + .sdram_tim3 = 0x0048a19f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff808 +}; + +static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { + .sdram_config_init = 0x80000eb1, + .sdram_config = 0x80001ab1, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80540300 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300 +}; + +void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs) +{ + u32 omap4_rev = omap4_revision(); + + if (omap4_rev == OMAP4430_ES1_0) { + *emif1_regs = &emif_regs_elpida_380_mhz_1cs; + *emif2_regs = &emif_regs_elpida_380_mhz_1cs; + } else if (omap4_rev == OMAP4430_ES2_0) { + *emif1_regs = &emif_regs_elpida_200_mhz_2cs; + *emif2_regs = &emif_regs_elpida_200_mhz_2cs; + } else { + *emif1_regs = &emif_regs_elpida_400_mhz_2cs; + *emif2_regs = &emif_regs_elpida_400_mhz_2cs; + } +} +void emif_get_reg_dump(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + u32 omap_rev = omap4_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h new file mode 100644 index 0000000..f2d54cb --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/emif.h @@ -0,0 +1,719 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V aneesh@ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ +#include <asm/types.h> +#include <common.h> + +/* Base address */ +#define OMAP44XX_EMIF1 0x4c000000 +#define OMAP44XX_EMIF2 0x4d000000 + +/* Registers shifts and masks */ + +/* EMIF_MOD_ID_REV */ +#define OMAP44XX_REG_SCHEME_SHIFT 30 +#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) +#define OMAP44XX_REG_MODULE_ID_SHIFT 16 +#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) +#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 +#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) +#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 +#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 +#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define OMAP44XX_REG_BE_SHIFT 31 +#define OMAP44XX_REG_BE_MASK (1 << 31) +#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 +#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define OMAP44XX_REG_FAST_INIT_SHIFT 29 +#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) +#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 +#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 +#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define OMAP44XX_REG_IBANK_POS_SHIFT 27 +#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) +#define OMAP44XX_REG_DDR_TERM_SHIFT 24 +#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) +#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 +#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) +#define OMAP44XX_REG_DYN_ODT_SHIFT 21 +#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) +#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 +#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 +#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define OMAP44XX_REG_CWL_SHIFT 16 +#define OMAP44XX_REG_CWL_MASK (0x3 << 16) +#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 +#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) +#define OMAP44XX_REG_CL_SHIFT 10 +#define OMAP44XX_REG_CL_MASK (0xf << 10) +#define OMAP44XX_REG_ROWSIZE_SHIFT 7 +#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) +#define OMAP44XX_REG_IBANK_SHIFT 4 +#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) +#define OMAP44XX_REG_EBANK_SHIFT 3 +#define OMAP44XX_REG_EBANK_MASK (1 << 3) +#define OMAP44XX_REG_PAGESIZE_SHIFT 0 +#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 +#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) +#define OMAP44XX_REG_EBANK_POS_SHIFT 27 +#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) +#define OMAP44XX_REG_RDBNUM_SHIFT 4 +#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) +#define OMAP44XX_REG_RDBSIZE_SHIFT 0 +#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 +#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) +#define OMAP44XX_REG_SRT_SHIFT 29 +#define OMAP44XX_REG_SRT_MASK (1 << 29) +#define OMAP44XX_REG_ASR_SHIFT 28 +#define OMAP44XX_REG_ASR_MASK (1 << 28) +#define OMAP44XX_REG_PASR_SHIFT 24 +#define OMAP44XX_REG_PASR_MASK (0x7 << 24) +#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define OMAP44XX_REG_T_RP_SHIFT 25 +#define OMAP44XX_REG_T_RP_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHIFT 21 +#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHIFT 17 +#define OMAP44XX_REG_T_WR_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHIFT 12 +#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHIFT 6 +#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHIFT 3 +#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHIFT 0 +#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 +#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 +#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define OMAP44XX_REG_T_XP_SHIFT 28 +#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHIFT 25 +#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHIFT 3 +#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHIFT 0 +#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define OMAP44XX_REG_T_CKESR_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHIFT 4 +#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 +#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define OMAP44XX_REG_IDLEMODE_SHIFT 30 +#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30) +#define OMAP44XX_REG_PD_TIM_SHIFT 12 +#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) +#define OMAP44XX_REG_DPD_EN_SHIFT 11 +#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) +#define OMAP44XX_REG_LP_MODE_SHIFT 8 +#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) +#define OMAP44XX_REG_SR_TIM_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8 +#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define OMAP44XX_REG_VALUE_0_SHIFT 0 +#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define OMAP44XX_REG_CS_SHIFT 31 +#define OMAP44XX_REG_CS_MASK (1 << 31) +#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 +#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) +#define OMAP44XX_REG_ADDRESS_SHIFT 0 +#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 +#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 +#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 +#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 +#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 +#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define OMAP44XX_REG_TLEC_SHIFT 16 +#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) +#define OMAP44XX_REG_MT_SHIFT 14 +#define OMAP44XX_REG_MT_MASK (1 << 14) +#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 +#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) +#define OMAP44XX_REG_OPG_LD_SHIFT 12 +#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) +#define OMAP44XX_REG_RESET_PHY_SHIFT 10 +#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) +#define OMAP44XX_REG_MMS_SHIFT 8 +#define OMAP44XX_REG_MMS_MASK (1 << 8) +#define OMAP44XX_REG_MC_SHIFT 4 +#define OMAP44XX_REG_MC_MASK (0x3 << 4) +#define OMAP44XX_REG_PC_SHIFT 1 +#define OMAP44XX_REG_PC_MASK (0x7 << 1) +#define OMAP44XX_REG_TM_SHIFT 0 +#define OMAP44XX_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 +#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) +#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 +#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 +#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define OMAP44XX_REG_COUNTER1_SHIFT 0 +#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define OMAP44XX_REG_COUNTER2_SHIFT 0 +#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 +#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 +#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) +#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 +#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 +#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define OMAP44XX_REG_MCONNID2_SHIFT 24 +#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) +#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 +#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) +#define OMAP44XX_REG_MCONNID1_SHIFT 8 +#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) +#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 +#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 +#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define OMAP44XX_REG_EOI_SHIFT 0 +#define OMAP44XX_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define OMAP44XX_REG_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define OMAP44XX_REG_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_TA_LL_SHIFT 1 +#define OMAP44XX_REG_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 +#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 +#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 +#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 +#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 +#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 +#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 +#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) +#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 +#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) +#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 +#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) +#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 +#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) +#define OMAP44XX_REG_MCMD_SHIFT 8 +#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) +#define OMAP44XX_REG_MCONNID_SHIFT 0 +#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_2 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) + +/* DMM */ +#define OMAP44XX_DMM_BASE 0x4E000000 +#define OMAP44XX_DMM_LISA_MAP_BASE (0x4E000000 + 0x40) + +/* DMM_LISA_MAP */ +#define OMAP44XX_SYS_ADDR_SHIFT 24 +#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) +#define OMAP44XX_SYS_SIZE_SHIFT 20 +#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) +#define OMAP44XX_SDRC_INTL_SHIFT 18 +#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) +#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 +#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) +#define OMAP44XX_SDRC_MAP_SHIFT 8 +#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) +#define OMAP44XX_SDRC_ADDR_SHIFT 0 +#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_LISA_MAP fields */ +#define DMM_SDRC_MAP_UNMAPPED 0 +#define DMM_SDRC_MAP_EMIF1_ONLY 1 +#define DMM_SDRC_MAP_EMIF2_ONLY 2 +#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 + +#define DMM_SDRC_INTL_NONE 0 +#define DMM_SDRC_INTL_128B 1 +#define DMM_SDRC_INTL_256B 2 +#define DMM_SDRC_INTL_512 3 + +#define DMM_SDRC_ADDR_SPC_SDRAM 0 +#define DMM_SDRC_ADDR_SPC_NVM 1 +#define DMM_SDRC_ADDR_SPC_INVALID 2 + +#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\ + (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\ + (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT)) + +#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) + +#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) + +/* Trap for invalid TILER PAT entries */ +#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ + (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ + (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) + + +/* Reg mapping structure */ +struct __attribute__ ((__packed__)) emif_reg_struct{ + u32 emif_mod_id_rev; + u32 emif_status; + u32 emif_sdram_config; + u32 emif_lpddr2_nvm_config; + u32 emif_sdram_ref_ctrl; + u32 emif_sdram_ref_ctrl_shdw; + u32 emif_sdram_tim_1; + u32 emif_sdram_tim_1_shdw; + u32 emif_sdram_tim_2; + u32 emif_sdram_tim_2_shdw; + u32 emif_sdram_tim_3; + u32 emif_sdram_tim_3_shdw; + u32 emif_lpddr2_nvm_tim; + u32 emif_lpddr2_nvm_tim_shdw; + u32 emif_pwr_mgmt_ctrl; + u32 emif_pwr_mgmt_ctrl_shdw; + u32 emif_lpddr2_mode_reg_data; + u32 padding1[1]; + u32 emif_lpddr2_mode_reg_data_es2; + u32 padding11[1]; + u32 emif_lpddr2_mode_reg_cfg; + u32 emif_l3_config; + u32 emif_l3_cfg_val_1; + u32 emif_l3_cfg_val_2; + u32 emif_iodft_tlgc; + u32 padding2[7]; + u32 emif_perf_cnt_1; + u32 emif_perf_cnt_2; + u32 emif_perf_cnt_cfg; + u32 emif_perf_cnt_sel; + u32 emif_perf_cnt_tim; + u32 padding3; + u32 emif_read_idlectrl; + u32 emif_read_idlectrl_shdw; + u32 padding4; + u32 emif_irqstatus_raw_sys; + u32 emif_irqstatus_raw_ll; + u32 emif_irqstatus_sys; + u32 emif_irqstatus_ll; + u32 emif_irqenable_set_sys; + u32 emif_irqenable_set_ll; + u32 emif_irqenable_clr_sys; + u32 emif_irqenable_clr_ll; + u32 padding5; + u32 emif_zq_config; + u32 emif_temp_alert_config; + u32 emif_l3_err_log; + u32 padding6[4]; + u32 emif_ddr_phy_ctrl_1; + u32 emif_ddr_phy_ctrl_1_shdw; + u32 emif_ddr_phy_ctrl_2; +}; + +struct __attribute__ ((__packed__)) dmm_lisa_map_regs { + u32 dmm_lisa_map_0; + u32 dmm_lisa_map_1; + u32 dmm_lisa_map_2; + u32 dmm_lisa_map_3; +}; + +#define CS0 0 +#define CS1 1 +/* Read Latency used by the device at reset */ +#define RL_BOOT 3 +/* Read Latency for the highest frequency you want to use */ +#define RL_FINAL 6 +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* Maximum delay before Low Power Modes */ +#define REG_CS_TIM 0xF +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF + +/* EMIF_PWR_MGMT_CTRL register */ +#define EMIF_PWR_MGMT_CTRL (\ + ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ + ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ + ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\ + & OMAP44XX_REG_LP_MODE_MASK) |\ + ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ + & OMAP44XX_REG_DPD_EN_MASK))\ + +#define EMIF_PWR_MGMT_CTRL_SHDW (\ + ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ + ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_PD_TIM_SHDW_MASK)) + +/* EMIF_L3_CONFIG register value for ES1*/ +#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00 0x0A0000FF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 + +/* MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_REF_FULL_ARRAY 0 + +/* LPDDR2 IO reg values */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR0 */ +#define LPDDR2_MR0_DAI_SHIFT 0 +#define LPDDR2_MR0_DAI_MASK 1 +#define LPDDR2_MR0_DI_SHIFT 1 +#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DNVI_SHIFT 2 +#define LPDDR2_MR0_DNVI_MASK (1 << 2) + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u32 sdram_config_init; + u32 sdram_config; + u32 ref_ctrl; + u32 sdram_tim1; + u32 sdram_tim2; + u32 sdram_tim3; + u32 read_idle_ctrl; + u32 zq_config; + u32 temp_alert_config; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1; +}; + +void emif_get_reg_dump(const struct emif_regs **emif1_regs, + const struct emif_regs **emif2_regs); +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); + +#endif diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 740ca9d..a1c4883 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -51,6 +51,17 @@ #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)

+/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO1_0 (CONTROL_PADCONF_CORE + 0x0638) +#define CONTROL_LPDDR2IO1_1 (CONTROL_PADCONF_CORE + 0x063C) +#define CONTROL_LPDDR2IO1_2 (CONTROL_PADCONF_CORE + 0x0640) +#define CONTROL_LPDDR2IO1_3 (CONTROL_PADCONF_CORE + 0x0644) +#define CONTROL_LPDDR2IO2_0 (CONTROL_PADCONF_CORE + 0x0648) +#define CONTROL_LPDDR2IO2_1 (CONTROL_PADCONF_CORE + 0x064C) +#define CONTROL_LPDDR2IO2_2 (CONTROL_PADCONF_CORE + 0x0650) +#define CONTROL_LPDDR2IO2_3 (CONTROL_PADCONF_CORE + 0x0654) +#define CONTROL_EFUSE_2 (CONTROL_PADCONF_CORE + 0x0704) + /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE (CTRL_BASE + 0x204)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index fd21afd..4beff42 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -44,6 +44,7 @@ void bypass_dpll(u32 base); void freq_update_core(void); u32 get_syc_clk_freq(void); u32 omap4_ddr_clk(void); +void sdram_init(void); u32 omap4_revision(void);

static inline u32 running_from_sdram(void) diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 5b20841..07d45a0 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -245,11 +245,6 @@ /* Defines for Clock init */ #define CONFIG_SYS_OMAP4_ABE_SYSCK

-/* Defines for SDRAM init */ -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 -#define CONFIG_SYS_EMIF_UPDATE_TIMINGS 1 -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 - /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile index 40e3e79..1f25f77 100644 --- a/spl/board/ti/sdp4430/Makefile +++ b/spl/board/ti/sdp4430/Makefile @@ -115,12 +115,20 @@ $(obj)board.c:$(obj)omap4_mux_data.h @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@

+$(obj)emif.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@ + +$(obj)sdram_elpida.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@ + $(obj)clocks.c: @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@

SOBJS += lowlevel_init.o -COBJS += board.o clocks.o +COBJS += board.o clocks.o emif.o sdram_elpida.o

# rules LDPPFLAGS += -include $(TOPDIR)/include/config.h

Identify SDRAM devices connected to EMIF automatically: LPDDR2 devices have some Mode Registers that provide details about the device such as the type, density, bus width etc. EMIF has the capability to read these registers. If there are not devices connected to a given chip-select reading mode registers will return junk values. After reading as many such registers as possible and matching with expected ranges of values the driver can identify if there is a device connected to the respective CS. If we identify that a device is connected the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2 allows us to do a complete automatic initialization of SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2 will be safe for all devices but not necessarily optimal. However, for the Elpida devices used on Panda and SDP the default timings are both safe and optimal.

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/omap4/emif.c | 177 +++++++++++++++++++++++++++++- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 9 +- include/configs/omap4_sdp4430.h | 1 + 3 files changed, 176 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index 1bdb1d2..006d065 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -165,7 +165,8 @@ static const struct lpddr2_min_tck min_tck_jedec = { .tFAW = 8 };

-static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = { +static const struct lpddr2_ac_timings const* + jedec_ac_timings[MAX_NUM_SPEEDBINS] = { &timings_jedec_200_mhz, &timings_jedec_333_mhz, &timings_jedec_400_mhz @@ -779,6 +780,146 @@ void emif_reset_phy(u32 base) writel(iodft, &emif->emif_iodft_tlgc); }

+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +static void display_sdram_details(u32 emif_nr, u32 cs, + struct lpddr2_device_details *device) +{ + const char *mfg_str; + const char *type_str; + char density_str[10]; + u32 density; + + debug("EMIF%d CS%d\t", emif_nr, cs); + + if (!device) { + debug("None\n"); + return; + } + + mfg_str = get_lpddr2_manufacturer(device->manufacturer); + type_str = get_lpddr2_type(device->type); + + density = lpddr2_density_2_size_in_mbytes[device->density]; + if ((density / 1024 * 1024) == density) { + density /= 1024; + sprintf(density_str, "%d GB", density); + } else + sprintf(density_str, "%d MB", density); + if (mfg_str && type_str) + debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); +} + +static u8 is_lpddr2_sdram_present(u32 base, u32 cs, + struct lpddr2_device_details *lpddr2_device) +{ + u32 mr = 0, temp; + + mr = get_mr(base, cs, LPDDR2_MR0); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = get_bit_field(mr, LPDDR2_MR0_DI_SHIFT, LPDDR2_MR0_DI_MASK); + if (temp) { + /* Not SDRAM */ + return 0; + } + temp = get_bit_field(mr, LPDDR2_MR0_DNVI_SHIFT, LPDDR2_MR0_DNVI_MASK); + + if (temp) { + /* DNV supported - But DNV is only supported for NVM */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR4); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR5); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + if (!get_lpddr2_manufacturer(mr)) { + /* Manufacturer not identified */ + return 0; + } + lpddr2_device->manufacturer = mr; + + mr = get_mr(base, cs, LPDDR2_MR6); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR7); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR8); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = get_bit_field(mr, MR8_TYPE_SHIFT, MR8_TYPE_MASK); + if (!get_lpddr2_type(temp)) { + /* Not SDRAM */ + return 0; + } + lpddr2_device->type = temp; + + temp = get_bit_field(mr, MR8_DENSITY_SHIFT, MR8_DENSITY_MASK); + if (temp > LPDDR2_DENSITY_32Gb) { + /* Density not supported */ + return 0; + } + lpddr2_device->density = temp; + + temp = get_bit_field(mr, MR8_IO_WIDTH_SHIFT, MR8_IO_WIDTH_MASK); + if (!get_lpddr2_io_width(temp)) { + /* IO width unsupported value */ + return 0; + } + lpddr2_device->io_width = temp; + + /* + * If all the above tests pass we should + * have a device on this chip-select + */ + return 1; +} + +static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + u32 phy; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (!lpddr2_dev_details) + return NULL; + + /* Do the minimum init for mode register accesses */ + if (!running_from_sdram()) { + phy = get_ddr_phy_ctrl_1(get_syc_clk_freq() / 2, RL_BOOT); + writel(phy, &emif->emif_ddr_phy_ctrl_1); + } + + if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) + return NULL; + + display_sdram_details(emif_num(base), cs, lpddr2_dev_details); + + return lpddr2_dev_details; +} +#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ + static void do_lpddr2_init(u32 base, u32 cs) { u32 mr_addr; @@ -862,9 +1003,7 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)

static void do_sdram_init(u32 base) { - struct emif_device_details dev_details; const struct emif_regs *regs; - u32 in_sdram, emif_nr;

in_sdram = running_from_sdram(); @@ -872,6 +1011,7 @@ static void do_sdram_init(u32 base)

#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS const struct emif_regs *tmp_regs; + emif_get_reg_dump(&regs, &tmp_regs); regs = (emif_nr == 1) ? regs : tmp_regs; #else @@ -879,23 +1019,48 @@ static void do_sdram_init(u32 base) * The user has not provided the register values. We need to * calculate it based on the timings and the DDR frequency */ + struct emif_device_details dev_details = { NULL, NULL }; + struct emif_regs calculated_regs;

+#if !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ + !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS) + + /* We need some input about the devices from the user */ const struct emif_device_details *dev_details_user_provided; const struct emif_device_details *tmp_details; - struct emif_regs calculated_regs;

- /* We need some input about the devices from the user */ emif_get_device_details(&dev_details_user_provided, &tmp_details); dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided : tmp_details; if (!dev_details_user_provided) return; +#endif

+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + + /* Automatically find the device details */ + if (!in_sdram) { + dev_details.cs0_device_details = + get_lpddr2_details(base, CS0, &cs0_dev_details); + dev_details.cs1_device_details = + get_lpddr2_details(base, CS1, &cs1_dev_details); + /* + * Reset the PHY - if there is nothing connected on any + * of the chip selects(typically CS1) mode register reads + * will mess up with the PHY state and subsequent + * initialization won't work. PHY reset brings back PHY to + * a good state. + */ + emif_reset_phy(base); + } +#else dev_details.cs0_device_details = dev_details_user_provided->cs0_device_details; dev_details.cs1_device_details = dev_details_user_provided->cs1_device_details;

+#endif /* Return if no devices on this EMIF */ if (!dev_details.cs0_device_details && !dev_details.cs1_device_details) { diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index e7d2bd5..8dfe6f9 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -86,10 +86,8 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .dmm_lisa_map_3 = 0x80640300 };

-void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs, - const struct emif_regs **emif2_regs) - -#else +#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ + !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)

static const struct lpddr2_ac_timings timings_elpida_400_mhz = { .max_freq = 400000000, @@ -245,7 +243,8 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) __attribute__((weak, alias("emif_get_dmm_regs_sdp")));

-#else +#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \ + !defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)

static void emif_get_device_details_sdp( const struct emif_device_details **emif1_details, diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index c29b184..a4332b7 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -247,6 +247,7 @@

/* Defines for SDRAM init */ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 #endif

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/start.S | 1 + arch/arm/include/asm/omap_common.h | 4 + include/configs/omap4_sdp4430.h | 7 ++- spl/board/ti/sdp4430/Makefile | 35 +++++++++++ spl/board/ti/spl-omap.c | 112 +++++++++++++++++++++++++++++++++++- 5 files changed, 156 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 1cbd128..927476c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -64,6 +64,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */

.global _end_vect _end_vect: +/* This label should be at the same location for SPL and U-Boot */ .global _u_boot_size _u_boot_size: .word 0xDEADBEEF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 9f2616c..c2efa7c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -99,4 +99,8 @@ u32 omap_boot_device(void); u32 omap_boot_mode(void); void preloader_console_init(void);

+/* symbols from start.S */ +extern u32 _u_boot_size; +extern u32 _start; + #endif /* _OMAP_COMMON_H_ */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index a4332b7..0ed474d 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -257,7 +257,10 @@ #define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ #define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK

-#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + +#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */

#endif /* __CONFIG_H */ diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile index d89dea0..18c5b8e 100644 --- a/spl/board/ti/sdp4430/Makefile +++ b/spl/board/ti/sdp4430/Makefile @@ -68,6 +68,41 @@ $(obj)ctype.c: COBJS += serial.o ns16550.o string.o vsprintf.o console.o stdio.o COBJS += ctype.o eabi_compat.o div64.o

+ +# mmc +$(obj)mmc.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mmc/mmc.c $@ + +$(obj)omap_hsmmc.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@ + +$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h + @rm -f $@ + @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@ + +$(obj)omap24xx_i2c.h: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@ + +$(obj)time.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/time.c $@ + +$(obj)part.c: + @rm -f $@ + @ln -s $(TOPDIR)/disk/part.c $@ + +$(obj)part_dos.c: $(obj)part_dos.h + @rm -f $@ + @ln -s $(TOPDIR)/disk/part_dos.c $@ + +$(obj)part_dos.h: + @rm -f $@ + @ln -s $(TOPDIR)/disk/part_dos.h $@ + +COBJS += omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o # armv7 $(obj)start.S: @rm -f $@ diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c index 57ddb7d..b64eac9 100644 --- a/spl/board/ti/spl-omap.c +++ b/spl/board/ti/spl-omap.c @@ -28,24 +28,134 @@ #include <common.h> #include <asm/u-boot.h> #include <asm/arch/sys_proto.h> +#include <mmc.h> #include <timestamp_autogenerated.h> +#include <asm/omap_common.h> +#include <asm/arch/mmc_host_def.h> +#include <i2c.h>

/* Define global data structure pointer to it*/ gd_t gdata __attribute__ ((section(".data"))); bd_t bdata __attribute__ ((section(".data"))); gd_t *gd = &gdata;

+typedef void (*u_boot_entry_t)(void)__attribute__ ((noreturn)); + void board_init_f(ulong dummy) { relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE); }

-void board_init_r(gd_t *id, ulong dummy) +inline void hang(void) { + puts("### ERROR ### Please RESET the board ###\n"); for (;;) ; }

+#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + omap_mmc_init(1); + return 0; +} +#endif + +static void mmc_load_uboot_raw(struct mmc *mmc, u32 mmc_dev) +{ + u32 u_boot_size_sectors, err; + u32 *u_boot_size = (u32 *)(CONFIG_SYS_TEXT_BASE + + (u32) &_u_boot_size - (u32) &_start); + + /* read one sector first to find u-boot size */ + err = mmc->block_dev.block_read(mmc_dev, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1, + (void *)CONFIG_SYS_TEXT_BASE); + if (err <= 0) + goto end; + + if (*u_boot_size != 0xDEADBEEF) { + err = 0xDEADBEEF; + goto end; + } + + /* move to the next word that has size */ + u_boot_size++; + + /* + * convert size to sectors - round down is fine because we have + * already read 1 sector + */ + u_boot_size_sectors = *u_boot_size/MMCSD_SECTOR_SIZE; + debug("spl: u-boot raw sectors - %d\n", u_boot_size_sectors + 1); + /* read one sector first to find u-boot size */ + err = mmc->block_dev.block_read(mmc_dev, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + 1, + u_boot_size_sectors, + (void *)(CONFIG_SYS_TEXT_BASE + MMCSD_SECTOR_SIZE)); +end: + if (err <= 0) { + printf("spl: mmc blk read err - %d\n", err); + hang(); + } +} + +static void mmc_load_uboot(u32 mmc_dev) +{ + struct mmc *mmc; + int err; + u32 boot_mode; + + mmc_initialize(gd->bd); + mmc = find_mmc_device(mmc_dev); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + err = mmc_init(mmc); + if (err) { + printf("spl: mmc init failed: mmc_dev - %d err - %d\n", + mmc_dev, err); + hang(); + } + + boot_mode = omap_boot_mode(); + if (boot_mode == MMCSD_MODE_RAW) + mmc_load_uboot_raw(mmc, mmc_dev); + else { + puts("spl: wrong MMC boot mode\n"); + hang(); + } +} + +void board_init_r(gd_t *id, ulong dummy) +{ + u32 boot_device; + u_boot_entry_t u_boot_entry = (u_boot_entry_t) CONFIG_SYS_TEXT_BASE; + + timer_init(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + boot_device = omap_boot_device(); + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1); + break; + default: + printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); + hang(); + break; + } + + /* + * Jump to u-boot with magic number as input to indicate that it + * was loaded by SPL + */ + u_boot_entry(); +} + void preloader_console_init(void) { gd->bd = &bdata;

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/include/asm/arch-omap4/emif.h | 10 +- include/configs/omap4_panda.h | 24 ++++ spl/board/ti/panda/Makefile | 219 ++++++++++++++++++++++++++++++++ 3 files changed, 248 insertions(+), 5 deletions(-) create mode 100644 spl/board/ti/panda/Makefile

diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h index 8cc3230..b95e545 100644 --- a/arch/arm/include/asm/arch-omap4/emif.h +++ b/arch/arm/include/asm/arch-omap4/emif.h @@ -520,11 +520,11 @@

/* Trap for invalid TILER PAT entries */ #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ - (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ - (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ - (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) + (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ + (0xFF << OMAP44XX_SYS_ADDR_SHIFT))

/* Reg mapping structure */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 2b03b0f..b389035 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -117,7 +117,9 @@

/* USB device configuration */ #define CONFIG_USB_DEVICE 1 +#ifndef CONFIG_PRELOADER #define CONFIG_USB_TTY 1 +#endif #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1

/* Flash */ @@ -234,4 +236,26 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)

+/* Defines for Clock init */ +#define CONFIG_SYS_OMAP4_ABE_SYSCK + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 1 +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 1 +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SYS_SPL_TEXT_BASE 0x40304360 +#define CONFIG_SYS_SPL_MAX_SIZE 0x7800 /* 30 K */ +#define CONFIG_SYS_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 + +#define CONFIG_SYS_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SYS_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + #endif /* __CONFIG_H */ diff --git a/spl/board/ti/panda/Makefile b/spl/board/ti/panda/Makefile new file mode 100644 index 0000000..8310db9 --- /dev/null +++ b/spl/board/ti/panda/Makefile @@ -0,0 +1,219 @@ +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +splobj := $(OBJTREE)/spl/ +include $(TOPDIR)/config.mk +SOBJS = +COBJS = + +# serial console +$(obj)eabi_compat.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@ + +$(obj)string.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/string.c $@ + +$(obj)vsprintf.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/vsprintf.c $@ + +$(obj)console.c: + @rm -f $@ + @ln -s $(TOPDIR)/common/console.c $@ + +$(obj)stdio.c: + @rm -f $@ + @ln -s $(TOPDIR)/common/stdio.c $@ + +$(obj)serial.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/serial/serial.c $@ + +$(obj)ns16550.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/serial/ns16550.c $@ + +$(obj)div64.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/div64.c $@ + +$(obj)ctype.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/ctype.c $@ + +COBJS += serial.o ns16550.o string.o vsprintf.o console.o stdio.o +COBJS += ctype.o eabi_compat.o div64.o + + +# mmc +$(obj)mmc.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mmc/mmc.c $@ + +$(obj)omap_hsmmc.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@ + +$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h + @rm -f $@ + @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@ + +$(obj)omap24xx_i2c.h: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@ + +$(obj)time.c: + @rm -f $@ + @ln -s $(TOPDIR)/lib/time.c $@ + +$(obj)part.c: + @rm -f $@ + @ln -s $(TOPDIR)/disk/part.c $@ + +$(obj)part_dos.c: $(obj)part_dos.h + @rm -f $@ + @ln -s $(TOPDIR)/disk/part_dos.c $@ + +$(obj)part_dos.h: + @rm -f $@ + @ln -s $(TOPDIR)/disk/part_dos.h $@ + +COBJS += omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o + +# fat +$(obj)fat.c: + @rm -f $@ + @ln -s $(TOPDIR)/fs/fat/fat.c $@ + +COBJS += fat.o + +# armv7 +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ + +$(obj)syslib.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@ + +SOBJS += start.o +COBJS += syslib.o + +# omap-common +$(obj)utils.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@ + +$(obj)timer.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@ + +$(obj)reset.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@ + +$(obj)spl-omap.c: + @rm -f $@ + @ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@ + +SOBJS += reset.o +COBJS += utils.o timer.o spl-omap.o + +$(OBJTREE)/MLO: $(splobj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage \ + -a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@ + +LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds + +# omap4 +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@ + +$(obj)omap4_mux_data.h: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@ + +$(obj)board.c:$(obj)omap4_mux_data.h + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@ + +$(obj)emif.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@ + +$(obj)sdram_elpida.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@ + +$(obj)clocks.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@ + +SOBJS += lowlevel_init.o +COBJS += board.o clocks.o emif.o sdram_elpida.o + +# rules +LDPPFLAGS += -include $(TOPDIR)/include/config.h +LDSCRIPT = $(splobj)u-boot-spl-generated.lds +$(LDSCRIPT): $(LDSCRIPT_SOURCE) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +LDFLAGS = -Bstatic -T $(LDSCRIPT) \ + $(PLATFORM_LDFLAGS) --gc-sections +AFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 +CFLAGS += -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \ + -fdata-sections -march=armv7-a -mthumb +PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \ + -print-libgcc-file-name`) -lgcc + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/spl/board/$(BOARDDIR) + +$(splobj)u-boot-spl.bin: $(splobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(splobj)u-boot-spl: $(OBJS) $(LDSCRIPT) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + $(PLATFORM_LIBGCC) \ + -Map $(splobj)u-boot-spl.map \ + -o $(splobj)u-boot-spl + +ALL = $(OBJTREE)/MLO +all: $(obj).depend $(ALL) + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend

From: John Rigby john.rigby@linaro.org

Signed-off-by: John Rigby john.rigby@linaro.org --- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 2 + tools/mkimage.h | 1 + tools/omapimage.c | 229 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/omapimage.h | 50 ++++++++++++ 7 files changed, 286 insertions(+), 0 deletions(-) create mode 100644 tools/omapimage.c create mode 100644 tools/omapimage.h

diff --git a/common/image.c b/common/image.c index e542a57..7f6fe1c 100644 --- a/common/image.c +++ b/common/image.c @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, + { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP CH/GP Boot Image",}, { -1, "", "", }, };

diff --git a/include/image.h b/include/image.h index c31e862..c606644 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ +#define IH_TYPE_OMAPIMAGE 11 /* TI OMAP Config Header Image */

/* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 623f908..a1c4ed7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o NOPED_OBJ_FILES-y += imximage.o +NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o @@ -180,6 +181,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)fit_image.o \ $(obj)image.o \ $(obj)imximage.o \ + $(obj)omapimage.o \ $(obj)kwbimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index 60f7263..b6a7cb7 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -156,6 +156,8 @@ main (int argc, char **argv) init_imx_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); + /* Init TI OMAP Boot image generation/list support */ + init_omap_image_type(); /* Init Default image generation/list support */ init_default_image_type ();

diff --git a/tools/mkimage.h b/tools/mkimage.h index 9033a7d..3b49645 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -143,5 +143,6 @@ void init_kwb_image_type (void); void init_imx_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); +void init_omap_image_type(void);

#endif /* _MKIIMAGE_H_ */ diff --git a/tools/omapimage.c b/tools/omapimage.c new file mode 100644 index 0000000..67fa056 --- /dev/null +++ b/tools/omapimage.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby john.rigby@linaro.org + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "omapimage.h" + +/* Header size is CH header rounded up to 512 bytes plus GP header */ +#define OMAP_CH_HDR_SIZE 512 +#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) + +static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; + +static int omapimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_OMAPIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +/* + * Only the simplest image type is currently supported: + * TOC pointing to CHSETTINGS + * TOC terminator + * CHSETTINGS + * + * padding to OMAP_CH_HDR_SIZE bytes + * + * gp header + * size + * load_addr + */ +static int valid_gph_size(uint32_t size) +{ + return size; +} + +static int valid_gph_load_addr(uint32_t load_addr) +{ + return load_addr; +} + +static int omapimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + if (!offset || !size) + return -1; + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + return -1; + toc++; + } + if (!valid_gph_size(gph->size)) + return -1; + if (!valid_gph_load_addr(gph->load_addr)) + return -1; + + return 0; +} + +static void omapimage_print_section(struct ch_settings *chs) +{ + switch (chs->section_key) { + case KEY_CHSETTINGS: + printf("CHSETTINGS (%x) " + "valid:%x " + "version:%x " + "reserved:%x " + "flags:%x\n", + chs->section_key, + chs->valid, + chs->version, + chs->reserved, + chs->flags); + break; + default: + printf("UNKNOWNKEY (%x) " + "valid:%x " + "version:%x " + "reserved:%x " + "flags:%x\n", + chs->section_key, + chs->valid, + chs->version, + chs->reserved, + chs->flags); + break; + } +} + +static void omapimage_print_header(const void *ptr) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + exit(EXIT_FAILURE); + + printf("Section %s offset %x length %x\n", + toc->section_name, + toc->section_offset, + toc->section_size); + + omapimage_print_section((struct ch_settings *)(ptr+offset)); + toc++; + } + + if (!valid_gph_size(gph->size)) { + fprintf(stderr, + "Error: invalid image size %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + if (!valid_gph_load_addr(gph->load_addr)) { + fprintf(stderr, + "Error: invalid image load address %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + printf("GP Header: Size %x LoadAddr %x\n", + gph->size, gph->load_addr); +} + +static int toc_offset(void *hdr, void *member) +{ + return member - hdr; +} + +static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct ch_settings *chs = (struct ch_settings *) + (ptr + 2 * sizeof(*toc)); + struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE); + + toc->section_offset = toc_offset(ptr, chs); + toc->section_size = sizeof(struct ch_settings); + strcpy((char *)toc->section_name, "CHSETTINGS"); + + chs->section_key = KEY_CHSETTINGS; + chs->valid = 0; + chs->version = 1; + chs->reserved = 0; + chs->flags = 0; + + toc++; + memset(toc, 0xff, sizeof(*toc)); + + gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; + gph->load_addr = params->addr; +} + +int omapimage_check_params(struct mkimage_params *params) +{ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +/* + * omapimage parameters + */ +static struct image_type_params omapimage_params = { + .name = "TI OMAP CH/GP Boot Image support", + .header_size = OMAP_FILE_HDR_SIZE, + .hdr = (void *)&omapimage_header, + .check_image_type = omapimage_check_image_types, + .verify_header = omapimage_verify_header, + .print_header = omapimage_print_header, + .set_header = omapimage_set_header, + .check_params = omapimage_check_params, +}; + +void init_omap_image_type(void) +{ + mkimage_register(&omapimage_params); +} diff --git a/tools/omapimage.h b/tools/omapimage.h new file mode 100644 index 0000000..7ff5404 --- /dev/null +++ b/tools/omapimage.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author John Rigby john.rigby@linaro.org + * Based on TI's signGP.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAPIMAGE_H_ +#define _OMAPIMAGE_H_ + +struct ch_toc { + uint32_t section_offset; + uint32_t section_size; + uint8_t unused[12]; + uint8_t section_name[12]; +} __attribute__ ((__packed__)); + +struct ch_settings { + uint32_t section_key; + uint8_t valid; + uint8_t version; + uint16_t reserved; + uint32_t flags; +} __attribute__ ((__packed__)); + +struct gp_header { + uint32_t size; + uint32_t load_addr; +} __attribute__ ((__packed__)); + +#define KEY_CHSETTINGS 0xC0C0C0C1 +#endif /* _OMAPIMAGE_H_ */

Define a new type of SPL that is not tied to any particular media. - Create a top level directory 'spl' that has a structure similar to the existing 'nand_spl' - Make necessary changes to top-level Makefile to build such an spl

Rationale for this approach: - There may be SPLs(like the OMAP x-loader) that support booting from multiple media. - Also, there is no harm in keeping SPLs specific to a particular media also under this directory. In fact it makes sense to merge all the different spl directories into this one.

Signed-off-by: Aneesh V aneesh@ti.com --- This patch generates 1 checkpatch warning due to declaration of DECLARE_GLOBAL_DATA_PTR. This is un-avoidable --- Makefile | 24 ++++++++++++++++++++++++ arch/arm/include/asm/global_data.h | 5 +++++ 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile index 384a59e..d3f4bef 100644 --- a/Makefile +++ b/Makefile @@ -289,6 +289,22 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version ([0-9][0-9]*).([0-9][0-9]*).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')

+ifeq ($(CONFIG_NAND_U_BOOT),y) +NAND_SPL = nand_spl +U_BOOT_NAND = $(obj)u-boot-nand.bin +endif + +ifeq ($(CONFIG_SPL),y) +.PHONEY : SPL +ALL += SPL +endif + +ifeq ($(CONFIG_ONENAND_U_BOOT),y) +ONENAND_IPL = onenand_ipl +U_BOOT_ONENAND = $(obj)u-boot-onenand.bin +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin +endif + __OBJS := $(subst $(obj),,$(OBJS)) __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))

@@ -402,8 +418,13 @@ $(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@

nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend + +$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C nand_spl/board/$(BOARDDIR) all

+SPL :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools + $(MAKE) -C spl/board/$(BOARDDIR) all + $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin

@@ -1122,6 +1143,7 @@ clean: @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)lib/asm-offsets.s @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} + @rm -f $(obj)spl/{u-boot-spl-generated.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} @rm -f $(ONENAND_BIN) @rm -f $(obj)onenand_ipl/u-boot.lds @@ -1141,12 +1163,14 @@ clobber: clean @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.imx + @rm -f $(obj)MLO @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f + @[ ! -d $(obj)spl ] || find $(obj)spl -name "*" -type l -print | xargs rm -f

ifeq ($(OBJTREE),$(SRCTREE)) mrproper \ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2a84d27..2ce020e 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -89,6 +89,11 @@ typedef struct global_data { #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */

+#ifdef CONFIG_PRELOADER +/* SPL works from internal RAM. gd pointer can be in .data section */ +#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd +#else #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#endif

#endif /* __ASM_GBL_DATA_H */

Changes for supporting SPL

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/start.S | 36 +++++++++++++++++++++++++----------- 1 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 13178cd..f92c6d9 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -42,7 +42,16 @@ _start: b reset ldr pc, _not_used ldr pc, _irq ldr pc, _fiq - +#ifdef CONFIG_PRELOADER +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -51,6 +60,8 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_PRELOADER */ + .global _end_vect _end_vect:

@@ -187,10 +198,9 @@ stack_setup: mov sp, r4

adr r0, _start -#ifndef CONFIG_PRELOADER cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ -#endif mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -240,6 +250,15 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_PRELOADER */

clear_bss: ldr r0, _bss_start_ofs @@ -253,7 +272,6 @@ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */

/* * We are done. Do not return, instead branch to second part of board @@ -281,13 +299,6 @@ jump_2_ram: _board_init_r_ofs: .word board_init_r - _start

-_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start - /************************************************************************* * * CPU_init_critical registers @@ -332,6 +343,8 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller + +#ifndef CONFIG_PRELOADER /* ************************************************************************* * @@ -520,3 +533,4 @@ fiq: bl do_fiq

#endif +#endif /* CONFIG_PRELOADER */

Add the basic spl framework and linker script common for OMAP3/4 platforms.

Signed-off-by: Aneesh V aneesh@ti.com --- spl/board/ti/spl-omap.c | 47 ++++++++++++++++++++++++++++++++++ spl/board/ti/spl-omap.lds | 62 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+), 0 deletions(-) create mode 100644 spl/board/ti/spl-omap.c create mode 100644 spl/board/ti/spl-omap.lds

diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c new file mode 100644 index 0000000..0e08f4f --- /dev/null +++ b/spl/board/ti/spl-omap.c @@ -0,0 +1,47 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/arch/sys_proto.h> +#include <timestamp_autogenerated.h> + +/* Define global data structure pointer to it*/ +gd_t gdata __attribute__ ((section(".data"))); +bd_t bdata __attribute__ ((section(".data"))); +gd_t *gd = &gdata; + +void board_init_f(ulong dummy) +{ + relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE); +} + +void board_init_r(gd_t *id, ulong dummy) +{ + for (;;) + ; +} diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds new file mode 100644 index 0000000..674ef05 --- /dev/null +++ b/spl/board/ti/spl-omap.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SYS_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram +}

The basic hardware init of OMAP4(s_init()) can happen in 4 different contexts: 1. SPL running from SRAM 2. U-Boot running from FLASH 3. Non-XIP U-Boot loaded to SDRAM by SPL 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the Configuration Header feature

What level of hw initialization gets done depends on this context. Add a utility function to find this context.

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/include/asm/arch-omap4/sys_proto.h | 47 +++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 6 +++ 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 0026b75..fb4c72f 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,6 +37,53 @@ void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long);

+static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && + (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * Configuration Header is not supported yet, so u-boot init running + * from SDRAM implies that it was loaded by SPL. When this situation + * changes one of these approaches could be taken: + * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known + * location. + * ii. Check the OPP. CH can support only 50% OPP while SPL initializes + * the DPLLs at 100% OPP. + */ + return running_from_sdram(); +} +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap4_hw_init_context(void) +{ +#ifdef CONFIG_PRELOADER + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH; + else + return OMAP_INIT_CONTEXT_XIP_UBOOT; +#endif +} + extern const struct omap_sysinfo sysinfo;

#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 7e28e28..2063c36 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -42,6 +42,12 @@ /* Magic number passed from SPL to U-Boot */ #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER 0xDEADBEEF

+/* HW Init Context */ +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_XIP_UBOOT 1 +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH 3 + u32 omap_boot_device(void); u32 omap_boot_mode(void);

Do the essential part from SPL and non-essential part from U-Boot - Essential part is what is essential for u-boot to function - Essential part is also largely board independent(at least as of now) - So essential part is moved out to SoC directory instead of keeping in board directory. This helps in having single SPL that works for Panda and SDP. - Non-essential part is what is set by u-boot for kernel to function correctly - Ideally non-essential part should be phased out eventually

Signed-off-by: Aneesh V aneesh@ti.com --- arch/arm/cpu/armv7/omap4/board.c | 53 ++++++++++++++++- arch/arm/cpu/armv7/omap4/omap4_mux_data.h | 76 ++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 4 +- board/ti/panda/panda.c | 25 ++------ board/ti/panda/{panda.h => panda_mux_data.h} | 45 ++------------ board/ti/sdp4430/sdp.c | 25 ++------ board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} | 47 ++------------- 7 files changed, 151 insertions(+), 124 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h rename board/ti/panda/{panda.h => panda_mux_data.h} (83%) rename board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} (83%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 046e3bf..30bf801 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -32,9 +32,30 @@ #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> #include <asm/sizes.h> +#include "omap4_mux_data.h"

DECLARE_GLOBAL_DATA_PTR;

+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +static void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + #ifdef CONFIG_PRELOADER u32 omap4_boot_device = BOOT_DEVICE_MMC1; u32 omap4_boot_mode = MMCSD_MODE_FAT; @@ -49,14 +70,41 @@ u32 omap_boot_mode(void) } #endif

+static void set_mux_conf_regs(void) +{ + switch (omap4_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + set_muxconf_regs_essential(); + break; + case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL: + set_muxconf_regs_non_essential(); + break; + case OMAP_INIT_CONTEXT_XIP_UBOOT: + case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH: + set_muxconf_regs_essential(); + set_muxconf_regs_non_essential(); + break; + } +} + /* * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with SRAM stack. + * Description: Does early system init of watchdog, muxing, clocks, and + * sdram. Watchdog disable is done always. For the rest what gets done + * depends on the boot mode in which this function is executed + * 1. s_init of SPL running from SRAM + * 2. s_init of U-Boot running from FLASH + * 3. s_init of U-Boot loaded to SDRAM by SPL + * 4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration + * Header feature + * Please have a look at the respective functions to see what gets done in + * each of these cases + * This function is called with SRAM stack. */ void s_init(void) { watchdog_init(); + set_mux_conf_regs(); }

/* @@ -139,7 +187,6 @@ int checkboard(void) */ int arch_cpu_init(void) { - set_muxconf_regs(); return 0; }

diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h new file mode 100644 index 0000000..00c52f8 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h @@ -0,0 +1,76 @@ + /* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy balajitk@ti.com + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP4_MUX_DATA_H_ +#define _OMAP4_MUX_DATA_H_ + +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +#endif /* _OMAP4_MUX_DATA_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index fb4c72f..ebd5b7a 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -24,6 +24,7 @@ #include <asm/arch/omap4.h> #include <asm/io.h> #include <asm/omap_common.h> +#include <asm/arch/mux_omap4.h>

struct omap_sysinfo { char *board_string; @@ -32,7 +33,8 @@ struct omap_sysinfo { void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); -void set_muxconf_regs(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 78e1910..9afed80 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -25,7 +25,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h>

-#include "panda.h" +#include "panda_mux_data.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -65,27 +65,14 @@ int misc_init_r(void) return 0; }

-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +void set_muxconf_regs_non_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -/** - * @brief set_muxconf_regs Setting up the configuration Mux registers - * specific to the board. - */ -void set_muxconf_regs(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, - sizeof(core_padconf_array) / + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry));

- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, - sizeof(wkup_padconf_array) / + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); }

diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda_mux_data.h similarity index 83% rename from board/ti/panda/panda.h rename to board/ti/panda/panda_mux_data.h index e3d090e..8bb7fe5 100644 --- a/board/ti/panda/panda.h +++ b/board/ti/panda/panda_mux_data.h @@ -24,21 +24,13 @@ * MA 02111-1307 USA */

-#ifndef _PANDA_H_ -#define _PANDA_H_ +#ifndef _PANDA_MUX_DATA_H_ +#define _PANDA_MUX_DATA_H_

#include <asm/io.h> #include <asm/arch/mux_omap4.h>

-const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ - {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ - {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ - {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ - {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ - {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ - {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ - {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ @@ -64,8 +56,6 @@ const struct pad_conf_entry core_padconf_array[] = { {GPMC_NWP, (M3)}, /* gpio_54 */ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ - {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ @@ -112,16 +102,6 @@ const struct pad_conf_entry core_padconf_array[] = { {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ - {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ - {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ - {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ @@ -144,14 +124,6 @@ const struct pad_conf_entry core_padconf_array[] = { {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ {UART2_TX, (M0)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ @@ -159,10 +131,6 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ @@ -236,14 +204,12 @@ const struct pad_conf_entry core_padconf_array[] = { {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ };

-const struct pad_conf_entry wkup_padconf_array[] = { +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ @@ -252,7 +218,6 @@ const struct pad_conf_entry wkup_padconf_array[] = { {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ - {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ @@ -261,4 +226,4 @@ const struct pad_conf_entry wkup_padconf_array[] = { {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ };

-#endif +#endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index b13c4c5..a5ea682 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -27,7 +27,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h>

-#include "sdp.h" +#include "sdp4430_mux_data.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -70,27 +70,14 @@ int misc_init_r(void) return 0; }

-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +void set_muxconf_regs_non_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -/** - * @brief set_muxconf_regs Setting up the configuration Mux registers - * specific to the board. - */ -void set_muxconf_regs(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, - sizeof(core_padconf_array) / + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry));

- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, - sizeof(wkup_padconf_array) / + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); }

diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp4430_mux_data.h similarity index 83% rename from board/ti/sdp4430/sdp.h rename to board/ti/sdp4430/sdp4430_mux_data.h index bf41067..e6081dc 100644 --- a/board/ti/sdp4430/sdp.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -23,22 +23,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef _SDP4430_MUX_DATA_H +#define _SDP4430_MUX_DATA_H

-#ifndef _SDP_H_ -#define _SDP_H_ - -#include <asm/io.h> #include <asm/arch/mux_omap4.h>

-const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ - {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ - {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ - {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ - {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ - {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ - {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ - {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ @@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = { {GPMC_NWP, (M3)}, /* gpio_54 */ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ - {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ @@ -112,16 +100,6 @@ const struct pad_conf_entry core_padconf_array[] = { {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ - {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ - {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ - {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ @@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = { {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ {UART2_TX, (M0)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ @@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ @@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = { {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ };

-const struct pad_conf_entry wkup_padconf_array[] = { +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ @@ -252,7 +216,6 @@ const struct pad_conf_entry wkup_padconf_array[] = { {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ - {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ @@ -261,4 +224,4 @@ const struct pad_conf_entry wkup_padconf_array[] = { {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ };

-#endif +#endif /* _SDP4430_MUX_DATA_H */

Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules

This work draws upon previous work done for x-loader mainly by: Santosh Shilimkar santosh.shilimkar@ti.com Rajendra Nayak rnayak@ti.com

Signed-off-by: Aneesh V aneesh@ti.com --- V2: * Use pre-calculated M & N values instead of calculated ones * Changes due to make file changes * Some corrections * Do all clock initialization in SPL itself instead of differing some work to u-boot --- arch/arm/cpu/armv7/omap4/Makefile | 1 + arch/arm/cpu/armv7/omap4/board.c | 1 + arch/arm/cpu/armv7/omap4/clocks.c | 731 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap4/clocks_get_m_n.c | 154 ++++++ arch/arm/include/asm/arch-omap4/clocks.h | 506 ++++++++++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 6 + arch/arm/include/asm/omap_common.h | 3 + spl/board/ti/omap4.mk | 7 +- 8 files changed, 1408 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c create mode 100644 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 987dc9d..6154e86 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -30,6 +30,7 @@ SOBJS += lowlevel_init.o COBJS += board.o COBJS += mem.o COBJS += sys_info.o +COBJS += clocks.o

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 30bf801..f83b6d7 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -105,6 +105,7 @@ void s_init(void) { watchdog_init(); set_mux_conf_regs(); + prcm_init(); }

/* diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c new file mode 100644 index 0000000..802917f --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -0,0 +1,731 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * Based on previous work by: + * Santosh Shilimkar santosh.shilimkar@ti.com + * Rajendra Nayak rnayak@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/omap_common.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/utils.h> + +#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) + +static const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 13000000, /* 13 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { + {250, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {1000, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {119, 1, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {1000, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_es1_600mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ + {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1 +}; + + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const u32 clk_domains_essential[] = { + CM_L4PER_CLKSTCTRL, + CM_L3INIT_CLKSTCTRL, + CM_MEMIF_CLKSTCTRL, + CM_L4CFG_CLKSTCTRL, + 0 +}; + +static const u32 clk_domains_non_essential[] = { + CM_MPU_M3_CLKSTCTRL, + CM_IVAHD_CLKSTCTRL, + CM_DSP_CLKSTCTRL, + CM_DSS_CLKSTCTRL, + CM_SGX_CLKSTCTRL, + CM1_ABE_CLKSTCTRL, + CM_C2C_CLKSTCTRL, + CM_CAM_CLKSTCTRL, + CM_DSS_CLKSTCTRL, + CM_SDMA_CLKSTCTRL, + 0 +}; + +static const u32 clk_modules_hw_auto_essential[] = { + CM_WKUP_GPIO1_CLKCTRL, + CM_L4PER_GPIO2_CLKCTRL, + CM_L4PER_GPIO3_CLKCTRL, + CM_L4PER_GPIO4_CLKCTRL, + CM_L4PER_GPIO5_CLKCTRL, + CM_L4PER_GPIO6_CLKCTRL, + CM_MEMIF_EMIF_1_CLKCTRL, + CM_MEMIF_EMIF_2_CLKCTRL, + CM_L3INIT_HSUSBOTG_CLKCTRL, + CM_L3INIT_USBPHY_CLKCTRL, + CM_L4CFG_L4_CFG_CLKCTRL, + 0 +}; + +static const u32 clk_modules_hw_auto_non_essential[] = { + CM_MPU_M3_MPU_M3_CLKCTRL, + CM_IVAHD_IVAHD_CLKCTRL, + CM_IVAHD_SL2_CLKCTRL, + CM_DSP_DSP_CLKCTRL, + CM_L3_2_GPMC_CLKCTRL, + CM_L3INSTR_L3_3_CLKCTRL, + CM_L3INSTR_L3_INSTR_CLKCTRL, + CM_L3INSTR_INTRCONN_WP1_CLKCTRL, + CM_L3INIT_HSI_CLKCTRL, + CM_L3INIT_HSUSBTLL_CLKCTRL, + 0 +}; + +static const u32 clk_modules_explicit_en_essential[] = { + CM_L4PER_GPTIMER2_CLKCTRL, + CM_L3INIT_HSMMC1_CLKCTRL, + CM_L3INIT_HSMMC2_CLKCTRL, + CM_L4PER_MCSPI1_CLKCTRL, + CM_WKUP_GPTIMER1_CLKCTRL, + CM_L4PER_I2C1_CLKCTRL, + CM_L4PER_I2C2_CLKCTRL, + CM_L4PER_I2C3_CLKCTRL, + CM_L4PER_I2C4_CLKCTRL, + CM_WKUP_WDTIMER2_CLKCTRL, + CM_L4PER_UART3_CLKCTRL, + 0 +}; + +static const u32 clk_modules_explicit_en_non_essential[] = { + CM1_ABE_AESS_CLKCTRL, + CM1_ABE_PDM_CLKCTRL, + CM1_ABE_DMIC_CLKCTRL, + CM1_ABE_MCASP_CLKCTRL, + CM1_ABE_MCBSP1_CLKCTRL, + CM1_ABE_MCBSP2_CLKCTRL, + CM1_ABE_MCBSP3_CLKCTRL, + CM1_ABE_SLIMBUS_CLKCTRL, + CM1_ABE_TIMER5_CLKCTRL, + CM1_ABE_TIMER6_CLKCTRL, + CM1_ABE_TIMER7_CLKCTRL, + CM1_ABE_TIMER8_CLKCTRL, + CM1_ABE_WDT3_CLKCTRL, + CM_L4PER_GPTIMER9_CLKCTRL, + CM_L4PER_GPTIMER10_CLKCTRL, + CM_L4PER_GPTIMER11_CLKCTRL, + CM_L4PER_GPTIMER3_CLKCTRL, + CM_L4PER_GPTIMER4_CLKCTRL, + CM_L4PER_HDQ1W_CLKCTRL, + CM_L4PER_MCBSP4_CLKCTRL, + CM_L4PER_MCSPI2_CLKCTRL, + CM_L4PER_MCSPI3_CLKCTRL, + CM_L4PER_MCSPI4_CLKCTRL, + CM_L4PER_MMCSD3_CLKCTRL, + CM_L4PER_MMCSD4_CLKCTRL, + CM_L4PER_MMCSD5_CLKCTRL, + CM_L4PER_UART1_CLKCTRL, + CM_L4PER_UART2_CLKCTRL, + CM_L4PER_UART4_CLKCTRL, + CM_WKUP_KEYBOARD_CLKCTRL, + CM_WKUP_WDTIMER2_CLKCTRL, + CM_CAM_ISS_CLKCTRL, + CM_CAM_FDIF_CLKCTRL, + CM_DSS_DSS_CLKCTRL, + CM_SGX_SGX_CLKCTRL, + CM_L3INIT_HSUSBHOST_CLKCTRL, + CM_L3INIT_FSUSB_CLKCTRL, + 0 +}; + +static inline u32 __get_sys_clk_index(void) +{ + u32 ind; + /* + * For ES1 the ROM code calibration of sys clock is not reliable + * due to hw issue. So, use hard-coded value. If this value is not + * correct for any board over-ride this function in board file + * From ES2.0 onwards you will get this information from + * CM_SYS_CLKSEL + */ + if (omap4_revision() == OMAP4430_ES1_0) + ind = OMAP_SYS_CLK_IND_38_4_MHZ; + else { + /* SYS_CLKSEL - 1 to match the dpll param array indices */ + ind = (readl(CM_SYS_CLKSEL) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) + - 1; + } + return ind; +} + +u32 get_sys_clk_index(void) + __attribute__ ((weak, alias("__get_sys_clk_index"))); + +u32 get_sys_clk_freq(void) +{ + u8 index = get_sys_clk_index(); + return sys_clk_array[index]; +} + +static inline void do_bypass_dpll(u32 base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + modify_reg_32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_SHIFT, + CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS); +} + +static inline void wait_for_bypass(u32 base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + while (readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK) + ; +} + +static inline void do_lock_dpll(u32 base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + modify_reg_32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_SHIFT, + CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_LOCK); +} + +static inline void wait_for_lock(u32 base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + while (!(readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK)) + ; +} + +static void do_setup_dpll(u32 base, const struct dpll_params *params, u8 lock) +{ + u32 temp; + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + bypass_dpll(base); + + /* Set M & N */ + temp = readl(&dpll_regs->cm_clksel_dpll); + set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK, + params->m); + set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK, + params->n); + writel(temp, &dpll_regs->cm_clksel_dpll); + + /* Lock */ + if (lock) + do_lock_dpll(base); + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, &dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, &dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, &dpll_regs->cm_div_m6_dpll); + if (params->m7 >= 0) + writel(params->m7, &dpll_regs->cm_div_m7_dpll); + + /* Wait till the DPLL locks */ + if (lock) + wait_for_lock(base); +} + +const struct dpll_params *get_core_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + + switch (omap4_revision()) { + case OMAP4430_ES1_0: + return &core_dpll_params_es1_1524mhz[sysclk_ind]; + case OMAP4430_ES2_0: + case OMAP4430_SILICON_ID_INVALID: + /* safest */ + return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; + default: + return &core_dpll_params_1600mhz[sysclk_ind]; + } +} + +u32 omap4_ddr_clk(void) +{ + u32 ddr_clk, sys_clk_khz; + const struct dpll_params *core_dpll_params; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + core_dpll_params = get_core_dpll_params(); + + debug("sys_clk %d\n ", sys_clk_khz * 1000); + + /* Find Core DPLL locked frequency first */ + ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / + (core_dpll_params->n + 1); + /* + * DDR frequency is PHY_ROOT_CLK/2 + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + ddr_clk = ddr_clk / 4 / core_dpll_params->m2; + + ddr_clk *= 1000; /* convert to Hz */ + debug("ddr_clk %d\n ", ddr_clk); + + return ddr_clk; +} + +static void setup_dplls(void) +{ + u32 sysclk_ind, temp; + const struct dpll_params *params; + + sysclk_ind = get_sys_clk_index(); + + /* CORE dpll */ + params = get_core_dpll_params(); /* default - safest */ + /* + * Do not lock the core DPLL now. Just set it up. + * Core DPLL will be locked after setting up EMIF + * using the FREQ_UPDATE method(freq_update_core()) + */ + do_setup_dpll(CM_CLKMODE_DPLL_CORE, params, DPLL_NO_LOCK); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ + temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | + (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | + (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); + writel(temp, CM_CLKSEL_CORE); + + /* lock PER dpll */ + do_setup_dpll(CM_CLKMODE_DPLL_PER, + &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); + + /* MPU dpll */ + if (omap4_revision() == OMAP4430_ES1_0) + params = &mpu_dpll_params_es1_600mhz[sysclk_ind]; + else + params = &mpu_dpll_params_1ghz[sysclk_ind]; + do_setup_dpll(CM_CLKMODE_DPLL_MPU, params, DPLL_LOCK); +} + +static void setup_non_essential_dplls(void) +{ + u32 sys_clk_khz, temp, abe_ref_clk; + u32 sysclk_ind, sd_div, num, den; + const struct dpll_params *params; + + sysclk_ind = get_sys_clk_index(); + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* IVA */ + do_setup_dpll(CM_CLKMODE_DPLL_IVA, &iva_dpll_params_1862mhz[sysclk_ind], + DPLL_LOCK); + + /* + * USB: + * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction + * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) + * - where CLKINP is sys_clk in MHz + * Use CLKINP in KHz and adjust the denominator accordingly so + * that we have enough accuracy and at the same time no overflow + */ + params = &usb_dpll_params_1920mhz[sysclk_ind]; + num = params->m * sys_clk_khz; + den = (params->n + 1) * 250 * 1000; + num += den - 1; + sd_div = num / den; + temp = readl(CM_CLKSEL_DPLL_USB); + set_bit_field(temp, CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT, + CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div); + writel(temp, CM_CLKSEL_DPLL_USB); + + /* Now setup the dpll with the regular function */ + do_setup_dpll(CM_CLKMODE_DPLL_USB, params, DPLL_LOCK); + +#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK + params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; +#else + params = &abe_dpll_params_32k_196608khz; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; + + /* + * Enable REGM4XEN to achieve 196.608MHz from 32768 Hz + * We need an additional multiplier of 4 on the input frequency + * since the input frequency is very low + */ + writel(readl(CM_CLKMODE_DPLL_ABE) | CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK, + CM_CLKMODE_DPLL_ABE); +#endif + + /* Select the right reference clk */ + modify_reg_32(CM_ABE_PLL_REF_CLKSEL, + CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT, + CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, + abe_ref_clk); + /* Lock the dpll */ + do_setup_dpll(CM_CLKMODE_DPLL_ABE, params, DPLL_LOCK); +} + +static void do_scale_vcore(u32 vcore_reg, u32 volt) +{ + u32 temp; + + temp = SMPS_I2C_SLAVE_ADDR | + (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (volt << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + writel(temp, PRM_VC_VAL_BYPASS); + while (readl(PRM_VC_VAL_BYPASS) & PRM_VC_VAL_BYPASS_VALID_BIT) + ; +} + +static void scale_vcores(void) +{ + u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp; + u32 omap4_rev = omap4_revision(); + + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(temp, PRM_VC_CFG_I2C_CLK); + + /* Disable high speed mode and all advanced features */ + writel(0x0, PRM_VC_CFG_I2C_MODE); + + /* VCORE 1 */ + if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1)) + volt = SMPS_VOLT_1_3500_V; + else + volt = SMPS_VOLT_1_5000_V; + do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + + /* VCORE 2 */ + if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1)) + volt = SMPS_VOLT_1_1000_V; + else + volt = SMPS_VOLT_1_2000_V; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + + /* VCORE 3 */ + if (omap4_rev == OMAP4430_ES2_0) + volt = SMPS_VOLT_1_1000_V; + else if (omap4_rev == OMAP4430_ES2_1) + volt = SMPS_VOLT_1_1125_V; + else + volt = SMPS_VOLT_1_2000_V; + + do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); +} + +static void enable_clock_domain(u32 clkctrl_reg, u32 enable_mode) +{ + modify_reg_32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_SHIFT, + CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode); +} + +static inline void wait_for_clk_enable(u32 clkctrl_addr) +{ + u32 idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + idlest = readl(clkctrl_addr); + idlest = get_bit_field(idlest, MODULE_CLKCTRL_IDLEST_SHIFT, + MODULE_CLKCTRL_IDLEST_MASK); + } +} + +static void enable_clock_module(u32 clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + modify_reg_32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_SHIFT, + MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +/* + * Enable a set of clock domains and clock modules associated with them + */ +static void enable_clocks(const u32 *clock_domains, + const u32 *clock_modules_hw_auto, + const u32 *clock_modules_explicit_en, + u32 wait_for_enable) +{ + int i = 0, max = 100; + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clock_domains[i]; i++) { + enable_clock_domain(clock_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clock_modules_hw_auto[i]; i++) { + enable_clock_module(clock_modules_hw_auto[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clock_modules_explicit_en[i]; i++) { + enable_clock_module(clock_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clock_domains[i]; i++) { + enable_clock_domain(clock_domains[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } +} + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_basic_clocks(void) +{ + /* Enable optional additional functional clock for GPIO4 */ + writel(readl(CM_L4PER_GPIO4_CLKCTRL) | GPIO4_CLKCTRL_OPTFCLKEN_MASK, + CM_L4PER_GPIO4_CLKCTRL); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + writel(readl(CM_L3INIT_HSMMC1_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_MASK, + CM_L3INIT_HSMMC1_CLKCTRL); + writel(readl(CM_L3INIT_HSMMC2_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_MASK, + CM_L3INIT_HSMMC2_CLKCTRL); + + /* Select 32KHz clock as the source of GPTIMER1 */ + writel(readl(CM_WKUP_GPTIMER1_CLKCTRL) | GPTIMER1_CLKCTRL_CLKSEL_MASK, + CM_WKUP_GPTIMER1_CLKCTRL); + + /* Enable optional 48M functional clock for USB PHY */ + writel(readl(CM_L3INIT_USBPHY_CLKCTRL) | + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK, CM_L3INIT_USBPHY_CLKCTRL); + + /* Enable all essential clock domains and modules */ + enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_non_essential_clocks(void) +{ + u32 tmp; + /* Enable optional functional clock for ISS */ + writel(readl(CM_CAM_ISS_CLKCTRL) | ISS_CLKCTRL_OPTFCLKEN_MASK, + CM_CAM_ISS_CLKCTRL); + + /* Enable all optional functional clocks of DSS */ + writel(readl(CM_DSS_DSS_CLKCTRL) | DSS_CLKCTRL_OPTFCLKEN_MASK, + CM_DSS_DSS_CLKCTRL); + + /* Enable all non-essential clock domains and modules */ + enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, 0); + + /* Put camera module in no sleep mode */ + tmp = readl(CM_CAM_CLKSTCTRL); + set_bit_field(tmp, MODULE_CLKCTRL_MODULEMODE_SHIFT, + MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP); + writel(tmp, CM_CAM_CLKSTCTRL); +} + +void freq_update_core(void) +{ + u32 freq_config1 = 0; + const struct dpll_params *core_dpll_params; + + core_dpll_params = get_core_dpll_params(); + /* Put EMIF clock domain in sw wakeup mode */ + enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL); + wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL); + + freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | + SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; + + set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT, + SHADOW_FREQ_CONFIG1_DPLL_EN_MASK, DPLL_EN_LOCK); + + set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT, + SHADOW_FREQ_CONFIG1_M2_DIV_MASK, core_dpll_params->m2); + + writel(freq_config1, CM_SHADOW_FREQ_CONFIG1); + while (readl(CM_SHADOW_FREQ_CONFIG1) & + SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK) + ; + + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL); + wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL); +} + +void bypass_dpll(u32 base) +{ + do_bypass_dpll(base); + wait_for_bypass(base); +} + +void lock_dpll(u32 base) +{ + do_lock_dpll(base); + wait_for_lock(base); +} + +void prcm_init(void) +{ + switch (omap4_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_XIP_UBOOT: + case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH: + scale_vcores(); + setup_dplls(); + enable_basic_clocks(); + setup_non_essential_dplls(); + enable_non_essential_clocks(); + break; + default: + break; + } +} diff --git a/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c new file mode 100644 index 0000000..777ec11 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c @@ -0,0 +1,154 @@ +/* + * Program for finding M & N values for DPLLs + * To be run on Host PC + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <stdlib.h> +#include <stdio.h> +typedef unsigned int u32; +#define MAX_N 127 +int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, + u32 n_max_limit, u32 tolerance_khz) +{ + u32 min_freq = target_freq_khz - tolerance_khz; + u32 max_freq = target_freq_khz; + u32 freq, freq_old; + *n = 1; + while (1) { + *m = min_freq / ref_freq_khz / 2 * (*n) ; + freq_old = 0; + while (1) { + freq = ref_freq_khz * 2 * (*m) / (*n); + if (abs(target_freq_khz - freq_old) <= + abs(target_freq_khz - freq)) { + freq = freq_old; + (*m)--; + break; + } + (*m)++; + freq_old = freq; + } + if (freq >= min_freq && freq <= max_freq) + break; + (*n)++; + if ((*n) > MAX_N + 1) { + printf("ref %d m %d n %d target %d : ", + ref_freq_khz, *m, *n, target_freq_khz); + printf("can not find m & n - please consider" + " increasing tolerance\n"); + return -1; + } + } + (*n)--; + printf("ref %d m %d n %d target %d locked %d\n", + ref_freq_khz, *m, *n, target_freq_khz, freq); + if ((ref_freq_khz / (*n + 1)) < 1000) { + printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than" + " ideal, locking time will be high!\n"); + } + return 0; +} + +void main(void) +{ + u32 m, n; + printf("\nMPU - 2000000\n"); + get_m_n_optimized(2000000, 12000, &m, &n, 128, 0); + get_m_n_optimized(2000000, 13000, &m, &n, 128, 0); + get_m_n_optimized(2000000, 16800, &m, &n, 128, 800); + get_m_n_optimized(2000000, 19200, &m, &n, 128, 0); + get_m_n_optimized(2000000, 26000, &m, &n, 128, 0); + get_m_n_optimized(2000000, 27000, &m, &n, 128, 0); + get_m_n_optimized(2000000, 38400, &m, &n, 128, 0); + + printf("\nMPU - 1200000\n"); + get_m_n_optimized(1200000, 12000, &m, &n, 128, 0); + get_m_n_optimized(1200000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1200000, 16800, &m, &n, 128, 800); + get_m_n_optimized(1200000, 19200, &m, &n, 128, 0); + get_m_n_optimized(1200000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1200000, 27000, &m, &n, 128, 0); + get_m_n_optimized(1200000, 38400, &m, &n, 128, 0); + + printf("\nCore 1600000\n"); + get_m_n_optimized(1600000, 12000, &m, &n, 128, 0); + get_m_n_optimized(1600000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1600000, 16800, &m, &n, 128, 200); + get_m_n_optimized(1600000, 19200, &m, &n, 128, 0); + get_m_n_optimized(1600000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1600000, 27000, &m, &n, 128, 0); + get_m_n_optimized(1600000, 38400, &m, &n, 128, 0); + + printf("\nPER 1536000\n"); + get_m_n_optimized(1536000, 12000, &m, &n, 128, 0); + get_m_n_optimized(1536000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1536000, 16800, &m, &n, 128, 0); + get_m_n_optimized(1536000, 19200, &m, &n, 128, 0); + get_m_n_optimized(1536000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1536000, 27000, &m, &n, 128, 0); + get_m_n_optimized(1536000, 38400, &m, &n, 128, 0); + + printf("\nIVA 1862000\n"); + get_m_n_optimized(1862000, 12000, &m, &n, 128, 0); + get_m_n_optimized(1862000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1862000, 16800, &m, &n, 128, 0); + get_m_n_optimized(1862000, 19200, &m, &n, 128, 900); + get_m_n_optimized(1862000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1862000, 27000, &m, &n, 128, 0); + get_m_n_optimized(1862000, 38400, &m, &n, 128, 800); + + printf("\nABE 196608 sys clk\n"); + get_m_n_optimized(196608, 12000, &m, &n, 128, 700); + get_m_n_optimized(196608, 13000, &m, &n, 128, 200); + get_m_n_optimized(196608, 16800, &m, &n, 128, 700); + get_m_n_optimized(196608, 19200, &m, &n, 128, 400); + get_m_n_optimized(196608, 26000, &m, &n, 128, 200); + get_m_n_optimized(196608, 27000, &m, &n, 128, 900); + get_m_n_optimized(196608, 38400, &m, &n, 128, 0); + + printf("\nABE 196608 32K\n"); + get_m_n_optimized(196608000/4, 32768, &m, &n, 128, 0); + + printf("\nUSB 1920000\n"); + get_m_n_optimized(1920000, 12000, &m, &n, 128, 0); + get_m_n_optimized(1920000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1920000, 16800, &m, &n, 128, 0); + get_m_n_optimized(1920000, 19200, &m, &n, 128, 0); + get_m_n_optimized(1920000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1920000, 27000, &m, &n, 128, 0); + get_m_n_optimized(1920000, 38400, &m, &n, 128, 0); + + printf("\nCore ES1 1523712\n"); + get_m_n_optimized(1524000, 12000, &m, &n, 128, 100); + get_m_n_optimized(1524000, 13000, &m, &n, 128, 0); + get_m_n_optimized(1524000, 16800, &m, &n, 128, 0); + get_m_n_optimized(1524000, 19200, &m, &n, 128, 0); + get_m_n_optimized(1524000, 26000, &m, &n, 128, 0); + get_m_n_optimized(1524000, 27000, &m, &n, 128, 0); + + /* exact recommendation for SDPs */ + get_m_n_optimized(1523712, 38400, &m, &n, 128, 0); + +} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h new file mode 100644 index 0000000..aec1241 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -0,0 +1,506 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V aneesh@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ +#include <common.h> + +#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) +#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) +#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) +#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) + +/* PRM.CKGEN module registers */ +#define CM_ABE_PLL_REF_CLKSEL (OMAP44XX_L4_WKUP_BASE + 0x610C) +#define CM_SYS_CLKSEL (OMAP44XX_L4_WKUP_BASE + 0x6110) + +/* PRM.WKUP_CM module registers */ +#define CM_WKUP_CLKSTCTRL (OMAP44XX_L4_WKUP_BASE + 0x7800) +#define CM_WKUP_L4WKUP_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7820) +#define CM_WKUP_WDTIMER1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7828) +#define CM_WKUP_WDTIMER2_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7830) +#define CM_WKUP_GPIO1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7838) +#define CM_WKUP_GPTIMER1_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7840) +#define CM_WKUP_GPTIMER12_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7848) +#define CM_WKUP_SYNCTIMER_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7850) +#define CM_WKUP_USIM_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7858) +#define CM_WKUP_SARRAM_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7860) +#define CM_WKUP_KEYBOARD_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7878) +#define CM_WKUP_RTC_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7880) +#define CM_WKUP_BANDGAP_CLKCTRL (OMAP44XX_L4_WKUP_BASE + 0x7888) + +/* DEVICE_PRM Registers */ +#define PRM_VC_VAL_BYPASS (OMAP44XX_L4_WKUP_BASE + 0x7BA0) +#define PRM_VC_CFG_CHANNEL (OMAP44XX_L4_WKUP_BASE + 0x7BA4) +#define PRM_VC_CFG_I2C_MODE (OMAP44XX_L4_WKUP_BASE + 0x7BA8) +#define PRM_VC_CFG_I2C_CLK (OMAP44XX_L4_WKUP_BASE + 0x7BAC) + +/* CM1.CKGEN module registers */ +#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) +#define CM_CLKSEL_ABE (OMAP44XX_L4_CORE_BASE + 0x4108) +#define CM_DLL_CTRL (OMAP44XX_L4_CORE_BASE + 0x4110) +#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) +#define CM_IDLEST_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4124) +#define CM_AUTOIDLE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4128) +#define CM_CLKSEL_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x412c) +#define CM_DIV_M2_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4130) +#define CM_DIV_M3_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4134) +#define CM_DIV_M4_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4138) +#define CM_DIV_M5_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x413c) +#define CM_DIV_M6_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4140) +#define CM_DIV_M7_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4144) +#define CM_SSC_DELTAMSTEP_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4148) +#define CM_SSC_MODFREQDIV_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x414c) +#define CM_EMU_OVERRIDE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4150) +#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) +#define CM_IDLEST_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4164) +#define CM_AUTOIDLE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4168) +#define CM_CLKSEL_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x416c) +#define CM_DIV_M2_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4170) +#define CM_SSC_DELTAMSTEP_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4188) +#define CM_SSC_MODFREQDIV_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x418c) +#define CM_BYPCLK_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x419c) +#define CM_CLKMODE_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a0) +#define CM_IDLEST_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a4) +#define CM_AUTOIDLE_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41a8) +#define CM_CLKSEL_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41ac) +#define CM_DIV_M4_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41b8) +#define CM_DIV_M5_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41bc) +#define CM_SSC_DELTAMSTEP_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41c8) +#define CM_SSC_MODFREQDIV_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41cc) +#define CM_BYPCLK_DPLL_IVA (OMAP44XX_L4_CORE_BASE + 0x41dc) +#define CM_CLKMODE_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e0) +#define CM_IDLEST_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e4) +#define CM_AUTOIDLE_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41e8) +#define CM_CLKSEL_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41ec) +#define CM_DIV_M2_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41f0) +#define CM_DIV_M3_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x41f4) +#define CM_SSC_DELTAMSTEP_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x4208) +#define CM_SSC_MODFREQDIV_DPLL_ABE (OMAP44XX_L4_CORE_BASE + 0x420c) +#define CM_CLKMODE_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4220) +#define CM_IDLEST_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4224) +#define CM_AUTOIDLE_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4228) +#define CM_CLKSEL_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x422c) +#define CM_DIV_M2_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4230) +#define CM_DIV_M4_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4238) +#define CM_DIV_M5_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x423c) +#define CM_DIV_M6_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4240) +#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY (OMAP44XX_L4_CORE_BASE + 0x4248) +#define CM_SHADOW_FREQ_CONFIG1 (OMAP44XX_L4_CORE_BASE + 0x4260) + +/* CM1.ABE register offsets */ +#define CM1_ABE_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x4500) +#define CM1_ABE_L4ABE_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4520) +#define CM1_ABE_AESS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4528) +#define CM1_ABE_PDM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4530) +#define CM1_ABE_DMIC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4538) +#define CM1_ABE_MCASP_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4540) +#define CM1_ABE_MCBSP1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4548) +#define CM1_ABE_MCBSP2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4550) +#define CM1_ABE_MCBSP3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4558) +#define CM1_ABE_SLIMBUS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4560) +#define CM1_ABE_TIMER5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4568) +#define CM1_ABE_TIMER6_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4570) +#define CM1_ABE_TIMER7_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4578) +#define CM1_ABE_TIMER8_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4580) +#define CM1_ABE_WDT3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4588) + +/* CM1.DSP register offsets */ +#define CM_DSP_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x4400) +#define CM_DSP_DSP_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x4420) + +/* CM2.CKGEN module registers */ +#define CM_CLKSEL_MPU_M3_ISS_ROOT (OMAP44XX_L4_CORE_BASE + 0x8100) +#define CM_CLKSEL_USB_60MHz (OMAP44XX_L4_CORE_BASE + 0x8104) +#define CM_SCALE_FCLK (OMAP44XX_L4_CORE_BASE + 0x8108) +#define CM_CORE_DVFS_PERF1 (OMAP44XX_L4_CORE_BASE + 0x8110) +#define CM_CORE_DVFS_PERF2 (OMAP44XX_L4_CORE_BASE + 0x8114) +#define CM_CORE_DVFS_PERF3 (OMAP44XX_L4_CORE_BASE + 0x8118) +#define CM_CORE_DVFS_PERF4 (OMAP44XX_L4_CORE_BASE + 0x811c) +#define CM_CORE_DVFS_CURRENT (OMAP44XX_L4_CORE_BASE + 0x8124) +#define CM_IVA_DVFS_PERF_TESLA (OMAP44XX_L4_CORE_BASE + 0x8128) +#define CM_IVA_DVFS_PERF_IVAHD (OMAP44XX_L4_CORE_BASE + 0x812c) +#define CM_IVA_DVFS_PERF_ABE (OMAP44XX_L4_CORE_BASE + 0x8130) +#define CM_IVA_DVFS_CURRENT (OMAP44XX_L4_CORE_BASE + 0x8138) +#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) +#define CM_IDLEST_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8144) +#define CM_AUTOIDLE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8148) +#define CM_CLKSEL_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x814c) +#define CM_DIV_M2_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8150) +#define CM_DIV_M3_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8154) +#define CM_DIV_M4_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8158) +#define CM_DIV_M5_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x815c) +#define CM_DIV_M6_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8160) +#define CM_DIV_M7_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8164) +#define CM_SSC_DELTAMSTEP_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8168) +#define CM_SSC_MODFREQDIV_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x816c) +#define CM_EMU_OVERRIDE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8170) +#define CM_CLKMODE_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8180) +#define CM_IDLEST_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8184) +#define CM_AUTOIDLE_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8188) +#define CM_CLKSEL_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x818c) +#define CM_DIV_M2_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x8190) +#define CM_SSC_DELTAMSTEP_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81a8) +#define CM_SSC_MODFREQDIV_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81ac) +#define CM_CLKDCOLDO_DPLL_USB (OMAP44XX_L4_CORE_BASE + 0x81b4) +#define CM_CLKMODE_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c0) +#define CM_IDLEST_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c4) +#define CM_AUTOIDLE_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81c8) +#define CM_CLKSEL_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81cc) +#define CM_DIV_M2_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81d0) +#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81e8) +#define CM_SSC_MODFREQDIV_DPLL_UNIPRO (OMAP44XX_L4_CORE_BASE + 0x81ec) + +/* CM2.CORE module registers */ +#define CM_L3_1_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8700) +#define CM_L3_1_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8708) +#define CM_L3_1_L3_1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8720) +#define CM_L3_2_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8800) +#define CM_L3_2_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8808) +#define CM_L3_2_L3_2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8820) +#define CM_L3_2_GPMC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8828) +#define CM_L3_2_OCMC_RAM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8830) +#define CM_MPU_M3_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8900) +#define CM_MPU_M3_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8904) +#define CM_MPU_M3_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8908) +#define CM_MPU_M3_MPU_M3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8920) +#define CM_SDMA_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8a00) +#define CM_SDMA_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8a04) +#define CM_SDMA_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8a08) +#define CM_SDMA_SDMA_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8a20) +#define CM_MEMIF_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8b00) +#define CM_MEMIF_DMM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b20) +#define CM_MEMIF_EMIF_FW_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b28) +#define CM_MEMIF_EMIF_1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b30) +#define CM_MEMIF_EMIF_2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b38) +#define CM_MEMIF_DLL_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b40) +#define CM_MEMIF_EMIF_H1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b50) +#define CM_MEMIF_EMIF_H2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b58) +#define CM_MEMIF_DLL_H_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8b60) +#define CM_C2C_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8c00) +#define CM_C2C_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x8c04) +#define CM_C2C_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8c08) +#define CM_C2C_SAD2D_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c20) +#define CM_C2C_MODEM_ICR_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c28) +#define CM_C2C_SAD2D_FW_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8c30) +#define CM_L4CFG_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8d00) +#define CM_L4CFG_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x8d08) +#define CM_L4CFG_L4_CFG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d20) +#define CM_L4CFG_HW_SEM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d28) +#define CM_L4CFG_MAILBOX_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d30) +#define CM_L4CFG_SAR_ROM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8d38) +#define CM_L3INSTR_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8e00) +#define CM_L3INSTR_L3_3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e20) +#define CM_L3INSTR_L3_INSTR_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e28) +#define CM_L3INSTR_INTRCONN_WP1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8e40) + +/* CM2.L3INIT register offsets */ +#define CM_L3INIT_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9300) + +/* CM2.L4PER register offsets */ +#define CM_L4PER_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9400) +#define CM_L4PER_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x9408) +#define CM_L4PER_ADC_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9420) +#define CM_L4PER_GPTIMER10_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9428) +#define CM_L4PER_GPTIMER11_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9430) +#define CM_L4PER_GPTIMER2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9438) +#define CM_L4PER_GPTIMER3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9440) +#define CM_L4PER_GPTIMER4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9448) +#define CM_L4PER_GPTIMER9_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9450) +#define CM_L4PER_ELM_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9458) +#define CM_L4PER_GPIO2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9460) +#define CM_L4PER_GPIO3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9468) +#define CM_L4PER_GPIO4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9470) +#define CM_L4PER_GPIO5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9478) +#define CM_L4PER_GPIO6_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9480) +#define CM_L4PER_HDQ1W_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9488) +#define CM_L4PER_HECC1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9490) +#define CM_L4PER_HECC2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9498) +#define CM_L4PER_I2C1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94a0) +#define CM_L4PER_I2C2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94a8) +#define CM_L4PER_I2C3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94b0) +#define CM_L4PER_I2C4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94b8) +#define CM_L4PER_L4PER_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94c0) +#define CM_L4PER_MCASP2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94d0) +#define CM_L4PER_MCASP3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94d8) +#define CM_L4PER_MCBSP4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94e0) +#define CM_L4PER_MGATE_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94e8) +#define CM_L4PER_MCSPI1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94f0) +#define CM_L4PER_MCSPI2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x94f8) +#define CM_L4PER_MCSPI3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9500) +#define CM_L4PER_MCSPI4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9508) +#define CM_L4PER_MMCSD3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9520) +#define CM_L4PER_MMCSD4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9528) +#define CM_L4PER_MSPROHG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9530) +#define CM_L4PER_SLIMBUS2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9538) +#define CM_L4PER_UART1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9540) +#define CM_L4PER_UART2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9548) +#define CM_L4PER_UART3_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9550) +#define CM_L4PER_UART4_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9558) +#define CM_L4PER_MMCSD5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9560) +#define CM_L4PER_I2C5_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9568) +#define CM_L4SEC_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9580) +#define CM_L4SEC_STATICDEP (OMAP44XX_L4_CORE_BASE + 0x9584) +#define CM_L4SEC_DYNAMICDEP (OMAP44XX_L4_CORE_BASE + 0x9588) +#define CM_L4SEC_AES1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95a0) +#define CM_L4SEC_AES2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95a8) +#define CM_L4SEC_DES3DES_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95b0) +#define CM_L4SEC_PKAEIP29_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95b8) +#define CM_L4SEC_RNG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95c0) +#define CM_L4SEC_SHA2MD51_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95c8) +#define CM_L4SEC_CRYPTODMA_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x95d8) + +/* CM2.IVAHD */ +#define CM_IVAHD_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x8f00) +#define CM_IVAHD_IVAHD_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8f20) +#define CM_IVAHD_SL2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x8f28) + +/* CM2.L3INIT */ +#define CM_L3INIT_HSMMC1_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9328) +#define CM_L3INIT_HSMMC2_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9330) +#define CM_L3INIT_HSI_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9338) +#define CM_L3INIT_HSUSBHOST_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9358) +#define CM_L3INIT_HSUSBOTG_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9360) +#define CM_L3INIT_HSUSBTLL_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9368) +#define CM_L3INIT_P1500_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9378) +#define CM_L3INIT_FSUSB_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x93d0) +#define CM_L3INIT_USBPHY_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x93e0) + +/* CM2.CAM */ +#define CM_CAM_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9000) +#define CM_CAM_ISS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9020) +#define CM_CAM_FDIF_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9028) + +/* CM2.DSS */ +#define CM_DSS_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9100) +#define CM_DSS_DSS_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9120) + +/* CM2.SGX */ +#define CM_SGX_CLKSTCTRL (OMAP44XX_L4_CORE_BASE + 0x9200) +#define CM_SGX_SGX_CLKCTRL (OMAP44XX_L4_CORE_BASE + 0x9220) + +/* DPLL register offsets */ +#define CM_CLKMODE_DPLL 0 +#define CM_IDLEST_DPLL 0x4 +#define CM_AUTOIDLE_DPLL 0x8 +#define CM_CLKSEL_DPLL 0xC +#define CM_DIV_M2_DPLL 0x10 +#define CM_DIV_M3_DPLL 0x14 +#define CM_DIV_M4_DPLL 0x18 +#define CM_DIV_M5_DPLL 0x1C +#define CM_DIV_M6_DPLL 0x20 +#define CM_DIV_M7_DPLL 0x24 + +#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK 11 +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +#define OMAP4_DPLL_MAX_N 127 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* Clock frequencies */ +#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 +#define OMAP_32K_CLK_FREQ 32768 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define SMPS_VOLT_1_0000_V 0x21 +#define SMPS_VOLT_1_0125_V 0x22 +#define SMPS_VOLT_1_0250_V 0x23 +#define SMPS_VOLT_1_0375_V 0x24 +#define SMPS_VOLT_1_0500_V 0x25 +#define SMPS_VOLT_1_0625_V 0x26 +#define SMPS_VOLT_1_0750_V 0x27 +#define SMPS_VOLT_1_0875_V 0x28 +#define SMPS_VOLT_1_1000_V 0x29 +#define SMPS_VOLT_1_1125_V 0x2A +#define SMPS_VOLT_1_1250_V 0x2B +#define SMPS_VOLT_1_1375_V 0x2C +#define SMPS_VOLT_1_1500_V 0x2D +#define SMPS_VOLT_1_1625_V 0x2E +#define SMPS_VOLT_1_1750_V 0x2F +#define SMPS_VOLT_1_1875_V 0x30 +#define SMPS_VOLT_1_2000_V 0x31 +#define SMPS_VOLT_1_2125_V 0x32 +#define SMPS_VOLT_1_2250_V 0x33 +#define SMPS_VOLT_1_2375_V 0x34 +#define SMPS_VOLT_1_2500_V 0x35 +#define SMPS_VOLT_1_2625_V 0x36 +#define SMPS_VOLT_1_2750_V 0x37 +#define SMPS_VOLT_1_2875_V 0x38 +#define SMPS_VOLT_1_3000_V 0x39 +#define SMPS_VOLT_1_3500_V 0x3A +#define SMPS_VOLT_1_5000_V 0x3B +#define SMPS_VOLT_1_5000_V 0x3B + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#define NUM_SYS_CLKS 7 + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; + u32 cm_div_m7_dpll; +}; + +/* DPLL parameter table */ +struct dpll_params { + u32 m; + u32 n; + u8 m2; + u8 m3; + u8 m4; + u8 m5; + u8 m6; + u8 m7; +}; + +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ebd5b7a..4ba0ee0 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -38,6 +38,12 @@ void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); +void prcm_init(void); +void bypass_dpll(u32 base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); +u32 omap4_revision(void);

static inline u32 running_from_sdram(void) { diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2063c36..787dd88 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,9 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_

+/* Max value for DPLL multiplier M */ +#define OMAP_DPLL_MAX_N 127 + /* Boot device */ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk index dffb53b..0374534 100644 --- a/spl/board/ti/omap4.mk +++ b/spl/board/ti/omap4.mk @@ -73,5 +73,10 @@ $(obj)board.c:$(obj)omap4_mux_data.h @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@

+$(obj)clocks.c: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@ + + SOBJS += lowlevel_init.o -COBJS += board.o +COBJS += board.o clocks.o