[U-Boot] [UBOOT PATCH v4 3/5] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these details from DT.
Signed-off-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com --- Changes from v3: - None
Changes from v2: - None
Changes from v1: - Removed commit reference from description as per comment --- include/configs/zynq_cse.h | 3 --- 1 file changed, 3 deletions(-)
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 2f5843f..adc02f0 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -41,7 +41,4 @@ #undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN 0x1000
-#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000 - #endif /* __CONFIG_ZYNQ_CSE_H */
Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint of memory. This configuration has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com --- Changes from v3: - Rebased on latest master
Changes from v2: - None
Changes from v1: - Update memory node as per comment - Removed intc and fclk as per comment --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-cse-nand.dts | 80 +++++++++++++++++++++++++++++++++++++++++ configs/zynq_cse_nand_defconfig | 50 ++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 arch/arm/dts/zynq-cse-nand.dts create mode 100644 configs/zynq_cse_nand_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9460230..834a19b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-cse-nand.dtb \ zynq-cse-qspi-single.dtb \ zynq-microzed.dtb \ zynq-minized.dtb \ diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts new file mode 100644 index 0000000..9b1dd19 --- /dev/null +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE NAND board DTS + * + * Copyright (C) 2018 Xilinx, Inc. + */ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Zynq CSE NAND Board"; + compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000"; + + aliases { + serial0 = &dcc; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x400000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + slcr: slcr@f8000000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + clock-output-names = "armpll", "ddrpll", + "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", + "gem1", "fclk0", "fclk1", + "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", + "uart0", "uart1", "spi0", + "spi1", "dma", "usb0_aper", + "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", + "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", + "can1_aper", "i2c0_aper", + "i2c1_aper", "uart0_aper", + "uart1_aper", "gpio_aper", + "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + }; + +}; + +&dcc { + status = "okay"; +}; diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig new file mode 100644 index 0000000..7c7e143 --- /dev/null +++ b/configs/zynq_cse_nand_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x100000 +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_SPL is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_CLK is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_PARTITIONS is not set +CONFIG_OF_EMBED=y +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_MMC is not set +CONFIG_NAND=y +CONFIG_NAND_ZYNQ=y +# CONFIG_EFI_LOADER is not set
Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint OCM memory. This configuration only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com --- Changes from v3: - None, rebased on latest master
Changes from v2: - None
Changes from v1: - None --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-cse-nor.dts | 88 ++++++++++++++++++++++++++++++++++++++++++ configs/zynq_cse_nor_defconfig | 50 ++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 arch/arm/dts/zynq-cse-nor.dts create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 834a19b..6785fef 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ zynq-cse-nand.dtb \ + zynq-cse-nor.dtb \ zynq-cse-qspi-single.dtb \ zynq-microzed.dtb \ zynq-minized.dtb \ diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts new file mode 100644 index 0000000..ba6f9a1 --- /dev/null +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE NOR board DTS + * + * Copyright (C) 2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Zynq CSE NOR Board"; + compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000"; + + aliases { + serial0 = &dcc; + }; + + memory@fffc0000 { + device_type = "memory"; + reg = <0xFFFC0000 0x40000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + clock-output-names = "armpll", "ddrpll", + "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", + "gem1", "fclk0", "fclk1", + "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", + "uart0", "uart1", "spi0", + "spi1", "dma", "usb0_aper", + "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", + "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", + "can1_aper", "i2c0_aper", + "i2c1_aper", "uart0_aper", + "uart1_aper", "gpio_aper", + "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + }; + +}; + +&dcc { + status = "okay"; +}; diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig new file mode 100644 index 0000000..842d520 --- /dev/null +++ b/configs/zynq_cse_nor_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_cse" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0xFFFC0000 +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_SYS_MALLOC_LEN=0x1000 +CONFIG_ZYNQ_M29EW_WB_HACK=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" +CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_SPL is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_CLK is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_PARTITIONS is not set +CONFIG_OF_EMBED=y +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +# CONFIG_EFI_LOADER is not set
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Siva Durga Prasad Paladugu