[U-Boot] [PATCH 1/2] net: phy: micrel: add documentation for Micrel KSZ90x1 binding
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the DTS documentation for the Micrel KSZ90x1 binding.
The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel]
This takes the original document and adds a clarification on how the skew values are represented in the code.
References:
Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 165 ++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 doc/device-tree-bindings/net/micrel-ksz90x1.txt
diff --git a/doc/device-tree-bindings/net/micrel-ksz90x1.txt b/doc/device-tree-bindings/net/micrel-ksz90x1.txt new file mode 100644 index 0000000..307f53f --- /dev/null +++ b/doc/device-tree-bindings/net/micrel-ksz90x1.txt @@ -0,0 +1,165 @@ +Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY + +Some boards require special tuning values, particularly when it comes to +clock delays. You can specify clock delay values by adding +micrel-specific properties to an Ethernet OF device node. + +Note that these settings are applied after any phy-specific fixup from +phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), +and therefore may overwrite them. + +KSZ9021: + + All skew control options are specified in picoseconds. The minimum + value is 0, the maximum value is 1800, and it is incremented by 120ps + steps. + + Optional properties: + + - rxc-skew-ps : Skew control of RXC pad + - rxdv-skew-ps : Skew control of RX CTL pad + - txc-skew-ps : Skew control of TXC pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +KSZ9031: + + All skew control options are specified in picoseconds. The minimum + value is 0, and the maximum is property-dependent. The increment + step is 60ps. + + The KSZ9031 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0_0000 -900ps 0 + 0_0001 -840ps 60 + 0_0010 -780ps 120 + 0_0011 -720ps 180 + 0_0100 -660ps 240 + 0_0101 -600ps 300 + 0_0110 -540ps 360 + 0_0111 -480ps 420 + 0_1000 -420ps 480 + 0_1001 -360ps 540 + 0_1010 -300ps 600 + 0_1011 -240ps 660 + 0_1100 -180ps 720 + 0_1101 -120ps 780 + 0_1110 -60ps 840 + 0_1111 0ps 900 + 1_0000 60ps 960 + 1_0001 120ps 1020 + 1_0010 180ps 1080 + 1_0011 240ps 1140 + 1_0100 300ps 1200 + 1_0101 360ps 1260 + 1_0110 420ps 1320 + 1_0111 480ps 1380 + 1_1000 540ps 1440 + 1_1001 600ps 1500 + 1_1010 660ps 1560 + 1_1011 720ps 1620 + 1_1100 780ps 1680 + 1_1101 840ps 1740 + 1_1110 900ps 1800 + 1_1111 960ps 1860 + + The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps + data pads, and the rxdv-skew-ps, txen-skew-ps control pads. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -420ps 0 + 0001 -360ps 60 + 0010 -300ps 120 + 0011 -240ps 180 + 0100 -180ps 240 + 0101 -120ps 300 + 0110 -60ps 360 + 0111 0ps 420 + 1000 60ps 480 + 1001 120ps 540 + 1010 180ps 600 + 1011 240ps 660 + 1100 300ps 720 + 1101 360ps 780 + 1110 420ps 840 + 1111 480ps 900 + + Optional properties: + + Maximum value of 1860: + + - rxc-skew-ps : Skew control of RX clock pad + - txc-skew-ps : Skew control of TX clock pad + + Maximum value of 900: + + - rxdv-skew-ps : Skew control of RX CTL pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +Examples: + + /* Attach to an Ethernet device with autodetected PHY */ + &enet { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + status = "okay"; + }; + + /* Attach to an explicitly-specified PHY */ + mdio { + phy0: ethernet-phy@0 { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + reg = <0>; + }; + }; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + +References + + Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf + + Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf + +Notes: + + Note that a previous version of the Micrel ksz9021rl/rn Data Sheet + was missing extended register 106 (transmit data pad skews), and + incorrectly specified the ps per step as 200ps/step instead of + 120ps/step. The latest update to this document reflects the latest + revision of the Micrel specification even though usage in the kernel + still reflects that incorrect document.
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- drivers/net/phy/micrel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 19b6bc7..2530a5b 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -211,7 +211,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv; - const int ps_to_regval = 200; + const int ps_to_regval = 60; int val[4]; int i, changed = 0, offset, max; u16 regval = 0;
On Wednesday, January 27, 2016 at 10:46:00 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
This is fine, thanks for spotting it.
Acked-by: Marek Vasut marex@denx.de
Joe, will you pick these two and push for 2016.03 or shall I pick them ?
Best regards, Marek Vasut
Hi Marek,
On Wed, Jan 27, 2016 at 4:07 PM, Marek Vasut marex@denx.de wrote:
On Wednesday, January 27, 2016 at 10:46:00 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
This is fine, thanks for spotting it.
Acked-by: Marek Vasut marex@denx.de
Joe, will you pick these two and push for 2016.03 or shall I pick them ?
I'll get them.
-Joe
On Wednesday, January 27, 2016 at 11:53:29 PM, Joe Hershberger wrote:
Hi Marek,
On Wed, Jan 27, 2016 at 4:07 PM, Marek Vasut marex@denx.de wrote:
On Wednesday, January 27, 2016 at 10:46:00 PM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
This is fine, thanks for spotting it.
Acked-by: Marek Vasut marex@denx.de
Joe, will you pick these two and push for 2016.03 or shall I pick them ?
I'll get them.
Roger, thanks!
Best regards, Marek Vasut
On Wed, Jan 27, 2016 at 3:46 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
dinguyen@opensource.altera.com writes:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
Is this expected to make any difference on the Altera socdk? Both with and without the patch, it takes a very long time (sometimes minutes) to negotiate a link, but once it does it works fine.
References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
drivers/net/phy/micrel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 19b6bc7..2530a5b 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -211,7 +211,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv;
- const int ps_to_regval = 200;
- const int ps_to_regval = 60; int val[4]; int i, changed = 0, offset, max; u16 regval = 0;
-- 2.6.2
On 01/27/2016 07:26 PM, Måns Rullgård wrote:
dinguyen@opensource.altera.com writes:
From: Dinh Nguyen dinguyen@opensource.altera.com
The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet.
Is this expected to make any difference on the Altera socdk? Both with and without the patch, it takes a very long time (sometimes minutes) to negotiate a link, but once it does it works fine.
The Altera socdk uses a different PHY, KSZ9021, so no, this patch will not affect that hardware.
I'll check out your link issues on the socdk when I get a chance.
Dinh
On Wed, Jan 27, 2016 at 3:45 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the DTS documentation for the Micrel KSZ90x1 binding.
The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel]
This takes the original document and adds a clarification on how the skew values are represented in the code.
References:
Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
participants (6)
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dinguyen＠opensource.altera.com -
Dinh Nguyen -
Joe Hershberger -
Joe Hershberger -
Marek Vasut -
Måns Rullgård