On 27.04.21 11:48, Stefan Roese wrote:

Because of the incorrectly supported SGMII_2500 mode, this patch disables eth2 for now until this issue will be fixed in mainline.

Also fix an incorrect comment.

Signed-off-by: Stefan Roese sr@denx.de Cc: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Chulski stefanc@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Marek Behun marek.behun@nic.cz

---

This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and PHY patches to resolve the ongoing discussion of the incorrect usage of SGMII_2500 for now.

arch/arm/dts/cn9130-crb.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)

Applied to u-boot-marvell/master

Thanks, Stefan

diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi index 657a934764ae..78b43b449b3e 100644 --- a/arch/arm/dts/cn9130-crb.dtsi +++ b/arch/arm/dts/cn9130-crb.dtsi @@ -232,7 +232,6 @@ };

&cp0_eth0 {

• /* Disable it for now, as mainline does not support this IF yet */ status = "okay"; phy-mode = "sfi"; };

@@ -247,7 +246,6 @@

&cp0_eth2 { /* Disable it for now, as mainline does not support this IF yet */

• status = "okay";

• status = "disabled"; phy = <&nbaset_phy0>;

• phy-mode = "sgmii-2500"; };

Viele Grüße, Stefan

On Tue, Apr 27, 2021 at 12:49 PM Stefan Roese sr@denx.de wrote:

As was discussed on the list, PHY_INTERFACE_MODE_SGMII_2500 is used incorrectly in the Marvell mvpp2 network driver and the Marvell PHY code. This patch removes the references to this macro in the Marvell PHY driver for now.

The correct support shall be implemented at a later time.

Signed-off-by: Stefan Roese sr@denx.de Cc: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Chulski stefanc@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Marek Behun marek.behun@nic.cz

---

This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and PHY patches to resolve the ongoing discussion of the incorrect usage of SGMII_2500 for now.

drivers/net/phy/marvell.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 3bcb0033b391..8850b604ef47 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -634,8 +634,7 @@ static int m88e2110_config(struct phy_device *phydev) /* Disabled 10G advertisement */ phy_write(phydev, 7, 0x20, 0x1e1); } else {

•           if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500 ||
  

•               phydev->interface == PHY_INTERFACE_MODE_2500BASEX) {
  

•           if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) {
                    /* Disabled 10G/5G advertisements */
                    phy_write(phydev, 7, 0x20, 0xa1);
            } else {
  

-- 2.31.1

Reviewed-by: Ramon Fried rfried.dev@gmail.com

On Tue, Apr 27, 2021 at 12:49 PM Stefan Roese sr@denx.de wrote:

As was discussed on the list, PHY_INTERFACE_MODE_SGMII_2500 is used incorrectly in the Marvell mvpp2 network driver and the Marvell PHY code. This patch removes the references to this macro in the mvpp2 network driver for now.

The correct support shall be implemented at a later time.

Signed-off-by: Stefan Roese sr@denx.de Cc: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Chulski stefanc@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Marek Behun marek.behun@nic.cz

---

This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and PHY patches to resolve the ongoing discussion of the incorrect usage of SGMII_2500 for now.

drivers/net/mvpp2.c | 53 --------------------------------------------- 1 file changed, 53 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 4c0a7b0a9f5c..b0287f561e2e 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2873,7 +2873,6 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)

    switch (port->phy_interface) {
    case PHY_INTERFACE_MODE_SGMII:

•   case PHY_INTERFACE_MODE_SGMII_2500:
            val |= MVPP2_GMAC_INBAND_AN_MASK;
            break;
    case PHY_INTERFACE_MODE_1000BASEX:
  

@@ -2941,7 +2940,6 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;

    if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||

•       port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
        port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
        port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
            val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  

@@ -3029,48 +3027,6 @@ static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) return 0; }

-static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) -{

•   u32 val, thresh;
  

•   /*
  

•    * Configure minimal level of the Tx FIFO before the lower part
  

•    * starts to read a packet
  

•    */
  

•   thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  

•   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  

•   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  

•   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  

•   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  

•   /* Disable bypass of sync module */
  

•   val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  

•   val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  

•   /* configure DP clock select according to mode */
  

•   val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  

•   /* configure QSGMII bypass according to mode */
  

•   val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  

•   writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  

•   val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  

•   /*
  

•    * Configure GIG MAC to SGMII mode connected to a fiber
  

•    * transceiver
  

•    */
  

•   val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  

•   writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  

•   /* configure AN 0x9268 */
  

•   val = MVPP2_GMAC_EN_PCS_AN |
  

•           MVPP2_GMAC_AN_BYPASS_EN |
  

•           MVPP2_GMAC_CONFIG_MII_SPEED  |
  

•           MVPP2_GMAC_CONFIG_GMII_SPEED     |
  

•           MVPP2_GMAC_FC_ADV_EN    |
  

•           MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  

•           MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  

•   writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  

-}

static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) { u32 val, thresh; @@ -3241,9 +3197,6 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) case PHY_INTERFACE_MODE_SGMII: gop_gmac_sgmii_cfg(port); break;

•   case PHY_INTERFACE_MODE_SGMII_2500:
  

•           gop_gmac_sgmii2_5_cfg(port);
  

•           break;
    case PHY_INTERFACE_MODE_1000BASEX:
            gop_gmac_1000basex_cfg(port);
            break;
  

@@ -3424,7 +3377,6 @@ static int gop_port_init(struct mvpp2_port *port) break;

    case PHY_INTERFACE_MODE_SGMII:

•   case PHY_INTERFACE_MODE_SGMII_2500:
    case PHY_INTERFACE_MODE_1000BASEX:
    case PHY_INTERFACE_MODE_2500BASEX:
            /* configure PCS */
  

@@ -3484,7 +3436,6 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:

•   case PHY_INTERFACE_MODE_SGMII_2500:
    case PHY_INTERFACE_MODE_1000BASEX:
    case PHY_INTERFACE_MODE_2500BASEX:
            if (enable)
  

@@ -3521,7 +3472,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)

    if (gop_id == 2) {
            if (phy_type == PHY_INTERFACE_MODE_SGMII ||

•               phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
                phy_type == PHY_INTERFACE_MODE_1000BASEX ||
                phy_type == PHY_INTERFACE_MODE_2500BASEX)
                    val |= MV_NETC_GE_MAC2_SGMII;
  

@@ -3532,7 +3482,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)

    if (gop_id == 3) {
            if (phy_type == PHY_INTERFACE_MODE_SGMII ||

•               phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
                phy_type == PHY_INTERFACE_MODE_1000BASEX ||
                phy_type == PHY_INTERFACE_MODE_2500BASEX)
                    val |= MV_NETC_GE_MAC3_SGMII;
  

@@ -4531,7 +4480,6 @@ static void mvpp2_start_dev(struct mvpp2_port *port) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:

•   case PHY_INTERFACE_MODE_SGMII_2500:
    case PHY_INTERFACE_MODE_1000BASEX:
    case PHY_INTERFACE_MODE_2500BASEX:
            mvpp2_gmac_max_rx_size_set(port);
  

@@ -5270,7 +5218,6 @@ static int mvpp2_start(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_SGMII:

•   case PHY_INTERFACE_MODE_SGMII_2500:
    case PHY_INTERFACE_MODE_1000BASEX:
    case PHY_INTERFACE_MODE_2500BASEX:
            mvpp2_port_power_up(port);
  

-- 2.31.1

Reviewed-by: Ramon Fried rfried.dev@gmail.com

Hi Jakov,

On 27.04.21 14:57, Jakov Petrina wrote:

Hi Stefan,

On 27/04/2021 11:48, Stefan Roese wrote:

...

With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version.

thanks, great to hear that the "2500base-x" PHY mode is now supported in U-Boot.

I see just now, that I somehow forgot to send the corresponding changes to the mvpp2 driver, which include this addition of "2500base-x" to phy_interfaces.h. I'll send those patches shortly.

Thanks, Stefan

...

Signed-off-by: Stefan Roese sr@denx.de Cc: Jakov Petrina jakov.petrina@sartura.hr Cc: Vladimir Vid vladimir.vid@sartura.hr Cc: Luka Perkov luka.perkov@sartura.hr

---

Jakov, Vladimir: This is completely untested. Could you please review and let me know, if this works for you?

Unfortunately, I don't have the required hardware with me so I am not able to test the change.

Regards,

Jakov

...

Thanks, Stefan

arch/arm/dts/armada-3720-uDPU.dts | 4 ++--   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 4b30f3cea8c7..4bf6d2eac798 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -126,14 +126,14 @@   &eth0 {       pinctrl-0 = <&pcie_pins>;       status = "okay"; -    phy-mode = "sgmii-2500"; +    phy-mode = "2500base-x";       managed = "in-band-status";       phy = <&ethphy0>;   };   &eth1 {       status = "okay"; -    phy-mode = "sgmii-2500"; +    phy-mode = "2500base-x";       managed = "in-band-status";       phy = <&ethphy1>;   };

Viele Grüße, Stefan