From: Matt Porter mporter@ti.com

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter mporter@ti.com Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/spi/Makefile | 1 + drivers/spi/ti_qspi.c | 262 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/ti_qspi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..f51033d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o

COBJS := $(COBJS-y) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c new file mode 100644 index 0000000..1973b85 --- /dev/null +++ b/drivers/spi/ti_qspi.c @@ -0,0 +1,262 @@ +/* + * TI QSPI driver + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/omap.h> +#include <malloc.h> +#include <spi.h> + +struct qspi_slave { + struct spi_slave slave; + unsigned int mode; + u32 cmd; + u32 dc; +}; + +#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave) + +struct qspi_regs { + u32 pid; + u32 pad0[3]; + u32 sysconfig; + u32 pad1[3]; + u32 intr_status_raw_set; + u32 intr_status_enabled_clear; + u32 intr_enable_set; + u32 intr_enable_clear; + u32 intc_eoi; + u32 pad2[3]; + u32 spi_clock_cntrl; + u32 spi_dc; + u32 spi_cmd; + u32 spi_status; + u32 spi_data; + u32 spi_setup0; + u32 spi_setup1; + u32 spi_setup2; + u32 spi_setup3; + u32 spi_switch; + u32 spi_data1; + u32 spi_data2; + u32 spi_data3; +}; + +static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; + +#define QSPI_TIMEOUT 2000000 + +#define QSPI_FCLK 192000000 + +/* Clock Control */ +#define QSPI_CLK_EN (1 << 31) +#define QSPI_CLK_DIV_MAX 0xffff + +/* Command */ +#define QSPI_EN_CS(n) (n << 28) +#define QSPI_WLEN(n) ((n-1) << 19) +#define QSPI_3_PIN (1 << 18) +#define QSPI_RD_SNGL (1 << 16) +#define QSPI_WR_SNGL (2 << 16) +#define QSPI_INVAL (4 << 16) + +/* Device Control */ +#define QSPI_DD(m, n) (m << (3 + n*8)) +#define QSPI_CKPHA(n) (1 << (2 + n*8)) +#define QSPI_CSPOL(n) (1 << (1 + n*8)) +#define QSPI_CKPOL(n) (1 << (n*8)) + +/* Status */ +#define QSPI_WC (1 << 1) +#define QSPI_BUSY (1 << 0) +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) +#define QSPI_XFER_DONE QSPI_WC + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_init(void) +{ + /* nothing to do */ +} + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + uint clk_div; + + if (!hz) + clk_div = 0; + else + clk_div = (QSPI_FCLK / hz) - 1; + + debug("%s: hz: %d, clock divider %d\n", __func__, hz, clk_div); + + /* disable SCLK */ + writel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN, &qspi->spi_clock_cntrl); + + if (clk_div < 0) { + debug("%s: clock divider < 0, using /1 divider\n", __func__); + clk_div = 0; + } + + if (clk_div > QSPI_CLK_DIV_MAX) { + debug("%s: clock divider >%d , using /%d divider\n", + __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); + clk_div = QSPI_CLK_DIV_MAX; + } + + /* enable SCLK */ + writel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl); + debug("%s: spi_clock_cntrl %08x\n", __func__, readl(&qspi->spi_clock_cntrl)); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct qspi_slave *qslave; + + qslave = spi_alloc_slave(struct qspi_slave, bus, cs); + if (!qslave) + return NULL; + + spi_set_speed(&qslave->slave, max_hz); + qslave->mode = mode; + debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode); + + return &qslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct qspi_slave *qslave = to_qspi_slave(slave); + free(qslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + writel(0, &qspi->spi_dc); + writel(0, &qspi->spi_cmd); + writel(0, &qspi->spi_data); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + writel(0, &qspi->spi_dc); + writel(0, &qspi->spi_cmd); + writel(0, &qspi->spi_data); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct qspi_slave *qslave = to_qspi_slave(slave); + uint words = bitlen >> 3; /* fixed 8-bit word length */ + const uchar *txp = dout; + uchar *rxp = din; + uint status; + int timeout; + + debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, words, flags); + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + return -1; + } + + /* setup command reg */ + qslave->cmd = 0; + qslave->cmd |= QSPI_WLEN(8); + qslave->cmd |= QSPI_EN_CS(slave->cs); + if (flags & SPI_3WIRE) + qslave->cmd |= QSPI_3_PIN; + qslave->cmd |= 0xfff; + + /* setup device control reg */ + qslave->dc = 0; + if (qslave->mode & SPI_CPHA) + qslave->dc |= QSPI_CKPHA(slave->cs); + if (qslave->mode & SPI_CPOL) + qslave->dc |= QSPI_CKPOL(slave->cs); + if (qslave->mode & SPI_CS_HIGH) + qslave->dc |= QSPI_CSPOL(slave->cs); + + while (words--) { + if (txp) { + debug("tx cmd %08x dc %08x data %02x\n", + qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); + writel(*txp++, &qspi->spi_data); + writel(qslave->dc, &qspi->spi_dc); + writel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd); + status = readl(&qspi->spi_status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("QSPI tx timed out\n"); + return -1; + } + status = readl(&qspi->spi_status); + } + debug("tx done, status %08x\n", status); + } + if (rxp) { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_SNGL, qslave->dc); + writel(qslave->dc, &qspi->spi_dc); + writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd); + status = readl(&qspi->spi_status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("QSPI rx timed out\n"); + return -1; + } + status = readl(&qspi->spi_status); + } + *rxp++ = readl(&qspi->spi_data); + debug("rx done, status %08x, read %02x\n", + status, *(rxp-1)); + } + } + + /* Terminate frame */ + if (flags & SPI_XFER_END) + writel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd); + + return 0; +}

From: Ravikumar Kattekola rk@ti.com

Add Quad read mode (6 pin interface) support to spi flash and ti qspi driver.

Quad mode (0x6bh on spansion) uses two extra pins (D2 and D3) for data transfer apart from the usual D0 and D1 pins thus transfering 4 bits per cycle.

Signed-off-by: Ravikumar Kattekola rk@ti.com Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/mtd/spi/spi_flash.c | 110 +++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi_flash_internal.h | 2 + drivers/spi/ti_qspi.c | 18 ++++-- include/configs/dra7xx_evm.h | 1 + include/spi.h | 2 + 5 files changed, 127 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5cc5669..f3094a2 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -42,7 +42,12 @@ static int spi_flash_read_write(struct spi_slave *spi, debug("SF: Failed to send command (%zu bytes): %d\n", cmd_len, ret); } else if (data_len != 0) { - ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); + if (spi->quad_enable) + flags = SPI_6WIRE; + else + flags = 0; + + ret = spi_xfer(spi, data_len * 8, data_out, data_in, flags | SPI_XFER_END); if (ret) debug("SF: Failed to transfer %zu bytes of data: %d\n", data_len, ret); @@ -198,6 +203,51 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, #endif }

+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + + unsigned long page_addr, byte_addr, page_size; + size_t chunk_len, actual; + int ret = 0; + u8 cmd[5]; + + spi->quad_enable = 1; + /* Handle memory-mapped SPI */ + if (flash->memory_map) + memcpy(data, flash->memory_map + offset, len); + + page_size = flash->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = CMD_READ_ARRAY_QUAD; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + cmd[4] = 0x0; + + ret = spi_flash_read_common(flash, cmd, sizeof(cmd), + data + actual, chunk_len); + if (ret < 0) { + debug("SF: read failed"); + break; + } + + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } + } + + return ret; +} + int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { @@ -320,6 +370,56 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; }

+int spi_flash_en_quad_mode(struct spi_flash *flash) +{ + u8 stat, con, cd; + u16 cr; + int ret; + cd = CMD_WRITE_STATUS; + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + goto out; + } + ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1); + ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1); + if (ret < 0) { + debug("%s: SF: read CR failed\n", __func__); + goto out; + } + /* Byte 1 - status reg, Byte 2 - config reg */ + cr = ((con | 0x1 << 1) << 8) | (stat << 0); + + ret = spi_flash_cmd_write(flash->spi, &cd, 1, &cr, 2); + if (ret) { + debug("SF: fail to write conf register\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write conf register timed out\n"); + goto out; + } + + ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1); + ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1); + if (ret < 0) { + debug("%s: SF: read CR failed\n", __func__); + goto out; + } + debug("%s: *** CR = %x\n", __func__, con); + + ret = spi_flash_cmd_write_disable(flash); + if (ret < 0) { + debug("SF: disabling write failed\n"); + goto out; + } +out: + return ret; +} + #ifdef CONFIG_OF_CONTROL int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) { @@ -464,6 +564,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; }

+#ifdef CONFIG_SF_QUAD_RD + spi_flash_en_quad_mode(flash); +#endif + #ifdef CONFIG_OF_CONTROL if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { debug("SF: FDT decode error\n"); @@ -507,7 +611,11 @@ void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, flash->spi = spi; flash->name = name;

+#ifdef CONFIG_SF_QUAD_RD + flash->read = spi_flash_cmd_read_quad; +#else flash->read = spi_flash_cmd_read_fast; +#endif flash->write = spi_flash_cmd_write_multi; flash->erase = spi_flash_cmd_erase;

diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 141cfa8..6dc2d6d 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -17,11 +17,13 @@

#define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_ARRAY_QUAD 0x6b

#define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_READ_CONFIG 0x35 #define CMD_WRITE_ENABLE 0x06 #define CMD_ERASE_4K 0x20 #define CMD_ERASE_32K 0x52 diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 1973b85..12bba11 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -72,6 +72,7 @@ static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; #define QSPI_RD_SNGL (1 << 16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) +#define QSPI_RD_QUAD (7 << 16)

/* Device Control */ #define QSPI_DD(m, n) (m << (3 + n*8)) @@ -235,10 +236,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, debug("tx done, status %08x\n", status); } if (rxp) { - debug("rx cmd %08x dc %08x\n", - qslave->cmd | QSPI_RD_SNGL, qslave->dc); - writel(qslave->dc, &qspi->spi_dc); - writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd); + if (flags & SPI_6WIRE) { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_QUAD, qslave->dc); + writel(qslave->cmd | QSPI_RD_QUAD, + &qspi->spi_cmd); + } else { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_SNGL, qslave->dc); + writel(qslave->cmd | QSPI_RD_SNGL, + &qspi->spi_cmd); + } status = readl(&qspi->spi_status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { @@ -250,7 +258,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } *rxp++ = readl(&qspi->spi_data); debug("rx done, status %08x, read %02x\n", - status, *(rxp-1)); + status, *(rxp-1)); } }

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 0583858..f16920b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -57,6 +57,7 @@ #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_CMD_SPI +#define CONFIG_SF_QUAD_RD #define CONFIG_SF_DEFAULT_SPEED 12000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3

diff --git a/include/spi.h b/include/spi.h index 3fe2e1e..13280dc 100644 --- a/include/spi.h +++ b/include/spi.h @@ -37,6 +37,7 @@ #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ #define SPI_3WIRE 0x10 /* SI/SO signals shared */ #define SPI_LOOP 0x20 /* loopback mode */ +#define SPI_6WIRE 0x10 /* SI/SO signals shared */

/* SPI transfer flags */ #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ @@ -56,6 +57,7 @@ struct spi_slave { unsigned int bus; unsigned int cs; unsigned int max_write_size; + bool quad_enable; };

/*-----------------------------------------------------------------------

Contains documentation and testing details for qspi flash interface.

Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- doc/README.ti_qspi_dra_test | 38 ++++++++++++++++++++++++++++++++++ doc/README.ti_qspi_flash | 47 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash

diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test new file mode 100644 index 0000000..8910ff1 --- /dev/null +++ b/doc/README.ti_qspi_dra_test @@ -0,0 +1,38 @@ +------------------------------------------------- + Simple steps used to test the QSPI at U-Boot +------------------------------------------------- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +---------------------------------- +Boot from another medium like MMC +---------------------------------- + +DRA752 EVM # mmc dev 0 +DRA752 EVM # fatload mmc 0 0x82000000 MLO +DRA752 EVM # fatload mmc 0 0x82000000 u-boot.img + +-------------------------------------------------- +Commands to erase/write u-boot/mlo to flash device +-------------------------------------------------- + +DRA752 EVM # sf probe 0 +[should detect the S25FL256S serial flash device] + +DRA752 EVM # sf erase 0 10000 +DRA752 EVM # sf erase 10000 10000 +DRA752 EVM # sf erase 20000 10000 +DRA752 EVM # sf erase 30000 10000 +DRA752 EVM # sf erase 40000 10000 +DRA752 EVM # sf erase 50000 10000 +DRA752 EVM # sf erase 60000 10000 + +DRA752 EVM # sf write 82000000 0 10000 +DRA752 EVM # sf write 83000000 20000 80000 + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x20000 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash new file mode 100644 index 0000000..f6be13b --- /dev/null +++ b/doc/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +------------------ + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase1 +------- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +------- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +----------------------- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +------ +drivers/qspi/ti_qspi.c + - Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +------- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level.