[U-Boot] [PATCH v3 00/30] musb: sunxi: Add OTG-Peripheral support for Allwineer H3/H5/A64

This is rework of previous A64 musb[1] and H3 musb series with OTG Peripheral support for Allwineer H3/H5/A64. Will submit another series on host support since A64 need AXP PMIC.
Series start with Jun Nie H3 musb changes followed by H5 and A64 musb changes.
All changes available at u-boot-sunxi/otg-peripheral branch.
[1] https://patchwork.ozlabs.org/cover/847375/
thanks! Jagan.
Chen-Yu Tsai (2): sunxi: Fix USB PHY index for H3/H5/A64 sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64
Jagan Teki (23): sunxi: usb_phy: Clear PHYCTL register before writing ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from Linux configs: bananapi-m2-plus: Enable USB OTG peripheral mode configs: sun50i: Drop CONFIG_USB_MAX_CONTROLLER_COUNT msub: sunxi: Update proper fifo config for H5 configs: sun50i: Set proper USB PHY count for H5 sunxi: usb_phy: Fix phy_config to handle all SOC's musb: sunxi: Add phy0 dual route support arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabetic sunxi: arm64: Increase u-boot size on MMC environment sunxi: Add uENV partition on gpt partition table arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from Linux configs: orangepi-pc2: Enable USB OTG peripheral mode arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from Linux configs: orangepi-prime: Enable USB OTG peripheral mode sunxi: clock: Fix clock gating for A64 configs: sun50i: Set proper USB PHY count for A64 musb: sunxi: Add support for A64 sunxi: usb_phy: Clear SIDDP for A64 arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux configs: bananapi-m64: Enable USB OTG peripheral mode arm64: allwinner: a64: olinuxino: Sync usb_otg from Linux configs: a64-olinuxino: Enable USB OTG peripheral mode
Jun Nie (5): sunxi: h3: Sync OTG and HCI nodes from Linux DT sunxi: musb: Add fifo config for H3 sunxi: musb: Hack dynamic fifo support for H3 OTG sunxi: musb: Enable OTG device clock for H3 sunxi: H3: set different otg base address per mode
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 10 ++++ arch/arm/dts/sun50i-a64-olinuxino.dts | 5 ++ arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 54 +++++++++++++-------- arch/arm/dts/sun50i-h5-orangepi-prime.dts | 13 +++++ arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +++++ arch/arm/dts/sun8i-h3.dtsi | 32 +++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 37 ++++++++------- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 ++ arch/arm/include/asm/arch-sunxi/usb_phy.h | 1 + arch/arm/mach-sunxi/usb_phy.c | 68 ++++++++++++++++++--------- configs/Sinovoip_BPI_M2_Plus_defconfig | 1 + configs/a64-olinuxino_defconfig | 1 + configs/bananapi_m64_defconfig | 1 + configs/orangepi_pc2_defconfig | 1 + configs/orangepi_prime_defconfig | 1 + drivers/usb/host/ehci-sunxi.c | 9 +++- drivers/usb/host/ohci-sunxi.c | 9 +++- drivers/usb/musb-new/musb_regs.h | 3 +- drivers/usb/musb-new/sunxi.c | 47 ++++++++++++++++++ env/Kconfig | 3 +- include/configs/sun50i.h | 7 ++- include/configs/sunxi-common.h | 3 +- 22 files changed, 258 insertions(+), 65 deletions(-)

From: Jun Nie jun.nie@linaro.org
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: removed 1/8] from commit message] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa6079..d9728a7 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -218,6 +218,19 @@ #size-cells = <0>; };
+ usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, @@ -250,6 +263,25 @@ #phy-cells = <1>; };
+ ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + ehci1: usb@01c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>;

From: Jun Nie jun.nie@linaro.org
Add fifo config for H3 as H3 differ with other SoC on ep number.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: fixed num_eps for H3] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de --- drivers/usb/musb-new/sunxi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index aedc24b..46c8bd2 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -290,10 +290,42 @@ static const struct musb_platform_ops sunxi_musb_ops = { .disable = sunxi_musb_disable, };
+#if defined(CONFIG_MACH_SUN8I_H3) +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = { + { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +}; +#else +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = { + { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +}; +#endif + static struct musb_hdrc_config musb_config = { + .fifo_cfg = sunxi_musb_fifo_config, + .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_fifo_config), .multipoint = 1, .dyn_fifo = 1, +#if defined(CONFIG_MACH_SUN8I_H3) + .num_eps = 5, +#else .num_eps = 6, +#endif .ram_bits = 11, };

On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Jun Nie jun.nie@linaro.org
Add fifo config for H3 as H3 differ with other SoC on ep number.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: fixed num_eps for H3] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de
drivers/usb/musb-new/sunxi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index aedc24b..46c8bd2 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -290,10 +290,42 @@ static const struct musb_platform_ops sunxi_musb_ops = { .disable = sunxi_musb_disable, };
+#if defined(CONFIG_MACH_SUN8I_H3) +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
- { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
+}; +#else +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
- { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
- { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
- { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
+};
Ugh, each and every two entries are the same except for style being either RX/TX . And each tuple differs only in hw_ep_num . Generate that with some sane macro ...
Moreover, the driver is DT capable, use that to discern different SoCs and DO NOT ADD MORE IFDEFs .
+#endif
static struct musb_hdrc_config musb_config = {
- .fifo_cfg = sunxi_musb_fifo_config,
- .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_fifo_config), .multipoint = 1, .dyn_fifo = 1,
+#if defined(CONFIG_MACH_SUN8I_H3)
- .num_eps = 5,
+#else .num_eps = 6, +#endif .ram_bits = 11, };

From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
Signed-off-by: Chen-Yu Tsai wens@csie.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: remove 3/8] from commit header] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +++++++++++++-------------- drivers/usb/host/ehci-sunxi.c | 9 +++++++- drivers/usb/host/ohci-sunxi.c | 9 +++++++- 3 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d328df9..2c82d0a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -270,17 +270,18 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */ +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 -#define AHB_GATE_OFFSET_USB_EHCI0 25 -#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif @@ -339,13 +340,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 6ecb7c4..f40228e 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev) #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have EHCI with OTG */ +#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 133774f..4b8a403 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; priv->usb_gate_mask <<= priv->phy_index; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have OHCI with OTG */ +#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask);

On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Signed-off-by: Chen-Yu Tsai wens@csie.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: remove 3/8] from commit header] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +++++++++++++-------------- drivers/usb/host/ehci-sunxi.c | 9 +++++++- drivers/usb/host/ohci-sunxi.c | 9 +++++++- 3 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d328df9..2c82d0a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -270,17 +270,18 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */ +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/*
- These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
- them 0 - 2 like they were called on older SoCs.
- */
-#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 -#define AHB_GATE_OFFSET_USB_EHCI0 25 -#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif @@ -339,13 +340,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/*
- These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 6ecb7c4..f40228e 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev) #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
- /* Newer chips have a EHCI/OHCI host pair for OTG host mode */
- priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
- priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
- priv->phy_index++; /* older chips do not have EHCI with OTG */
+#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 133774f..4b8a403 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
- /* Newer chips have a EHCI/OHCI host pair for OTG host mode */
- priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; priv->usb_gate_mask <<= priv->phy_index;
- priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
- priv->phy_index++; /* older chips do not have OHCI with OTG */
+#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask);

On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.

On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
You can associate data with each DT compatible in the struct udevice_id, so this should be rather trivial change _without_ adding any ifdefs.

On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.

On 01/28/2018 07:29 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.
I only see if (platform is foo or bar) set phy_index to something else set it to something else, therefore I think the comment about 'phy, reset, clock' is irrelevant.
You can very well add ie. { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO },
And then do
if (dev_get_driver_data(...) == TYPE_FOO) priv->phy_index = bar; else priv->.......;
If you think this is not possible, please do explain why in detail.

On 01/28/2018 07:40 PM, Marek Vasut wrote:
On 01/28/2018 07:29 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.
I only see if (platform is foo or bar) set phy_index to something else set it to something else, therefore I think the comment about 'phy, reset, clock' is irrelevant.
You can very well add ie. { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO },
And then do
if (dev_get_driver_data(...) == TYPE_FOO) priv->phy_index = bar; else priv->.......;
If you think this is not possible, please do explain why in detail.
Can I expect a new patchset using DT properly ?

On Mon, Jan 29, 2018 at 10:04 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:40 PM, Marek Vasut wrote:
On 01/28/2018 07:29 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 05:19 PM, Jagan Teki wrote: > From: Chen-Yu Tsai wens@csie.org > > On the new chips such as H3, H5, and A64, the USB OTG controller is > paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, > the USB PHY index count has to be reworked to start from this pair. > > This patch reworks the USB clock gate and reset indices, and how the > USB host is mapped to a USB phy, for the newer chips.
The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.
I only see if (platform is foo or bar) set phy_index to something else set it to something else, therefore I think the comment about 'phy, reset, clock' is irrelevant.
You can very well add ie. { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO },
And then do
if (dev_get_driver_data(...) == TYPE_FOO) priv->phy_index = bar; else priv->.......;
If you think this is not possible, please do explain why in detail.
Can I expect a new patchset using DT properly ?
Yes Marek, I'm working on infact I'm trying to get these SOC's specs out from musb and writing phy driver for that matter.

On 01/29/2018 05:56 PM, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 10:04 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:40 PM, Marek Vasut wrote:
On 01/28/2018 07:29 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut marex@denx.de wrote:
On 01/28/2018 07:20 PM, Jagan Teki wrote:
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut marex@denx.de wrote: > On 01/28/2018 05:19 PM, Jagan Teki wrote: >> From: Chen-Yu Tsai wens@csie.org >> >> On the new chips such as H3, H5, and A64, the USB OTG controller is >> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >> the USB PHY index count has to be reworked to start from this pair. >> >> This patch reworks the USB clock gate and reset indices, and how the >> USB host is mapped to a USB phy, for the newer chips. > > The ifdeffery is awful. The driver is DT capable, do why don't you > detect the block type / soc type from DT and handle this dynamically > instead of adding ifdefs ?
Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this:
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif
if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.
I only see if (platform is foo or bar) set phy_index to something else set it to something else, therefore I think the comment about 'phy, reset, clock' is irrelevant.
You can very well add ie. { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO },
And then do
if (dev_get_driver_data(...) == TYPE_FOO) priv->phy_index = bar; else priv->.......;
If you think this is not possible, please do explain why in detail.
Can I expect a new patchset using DT properly ?
Yes Marek, I'm working on infact I'm trying to get these SOC's specs out from musb and writing phy driver for that matter.
Good!

From: Jun Nie jun.nie@linaro.org
Like other Allwinner SoC, the H3 is missing the config register from the musb hardware block. Use a known working value for it like other SoC.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: remove 4/8] from commit header] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/usb/musb-new/musb_regs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index a3cc38e..8a357ed 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -432,7 +432,8 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
static inline u8 musb_read_configdata(void __iomem *mbase) { -#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T +#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T) || \ + defined(CONFIG_MACH_SUNXI_H3_H5) /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde; #else

From: Jun Nie jun.nie@linaro.org
Enable OTG clock and deassert reset
Signed-off-by: Jun Nie jun.nie@linaro.org [jagan: fixed AHB_GATE_OFFSET_OTG_DEVICE to use H3/H5/A64] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Jagan Teki jagan@openedev.com Cc: Marek Vasut marex@denx.de --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + drivers/usb/musb-new/sunxi.c | 8 ++++++++ 2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 2c82d0a..624d624 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -279,6 +279,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI2 26 #define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 46c8bd2..c3b8fa4 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -266,6 +266,11 @@ static int sunxi_musb_init(struct musb *musb) #ifdef CONFIG_SUNXI_GEN_SUN6I setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_OTG_DEVICE)); + setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_OTG_DEVICE)); +#endif + sunxi_usb_phy_init(0);
USBC_ConfigFIFO_Base(); @@ -380,6 +385,9 @@ static int musb_usb_remove(struct udevice *dev) #ifdef CONFIG_SUNXI_GEN_SUN6I clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_OTG_DEVICE); +#endif clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
free(host->host);

On 01/28/2018 05:19 PM, Jagan Teki wrote:
From: Jun Nie jun.nie@linaro.org
Enable OTG clock and deassert reset
Signed-off-by: Jun Nie jun.nie@linaro.org [jagan: fixed AHB_GATE_OFFSET_OTG_DEVICE to use H3/H5/A64] Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Jagan Teki jagan@openedev.com Cc: Marek Vasut marex@denx.de
Same concern about DT and ifdefs here ...
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + drivers/usb/musb-new/sunxi.c | 8 ++++++++ 2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 2c82d0a..624d624 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -279,6 +279,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI2 26 #define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 46c8bd2..c3b8fa4 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -266,6 +266,11 @@ static int sunxi_musb_init(struct musb *musb) #ifdef CONFIG_SUNXI_GEN_SUN6I setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
- setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_OTG_DEVICE));
- setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_OTG_DEVICE));
+#endif
sunxi_usb_phy_init(0);
USBC_ConfigFIFO_Base();
@@ -380,6 +385,9 @@ static int musb_usb_remove(struct udevice *dev) #ifdef CONFIG_SUNXI_GEN_SUN6I clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
- clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_OTG_DEVICE);
+#endif clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
free(host->host);

From: Chen-Yu Tsai wens@csie.org
On newer chips, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY.
Signed-off-by: Chen-Yu Tsai wens@csie.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: remove 7/8] from commit header] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/usb_phy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..9a0a1b9 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -239,7 +239,12 @@ void sunxi_usb_phy_init(int index)
sunxi_usb_phy_config(phy);
- if (phy->id != 0) + /* + * Later SoCs such as the H3, H5, A64 have proper hosts for OTG. + * As such the passby settings need to be set for them as well. + */ + if (phy->id != 0 || IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5) || + IS_ENABLED(CONFIG_MACH_SUN50I)) sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
#ifdef CONFIG_MACH_SUN8I_A83T

From: Jun Nie jun.nie@linaro.org
Set different base address per host mode or peripheral mode. Phy configuration also depends on this address.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com [jagan: remove 8/8] from commit header] Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 2419062..f45f53a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -64,7 +64,11 @@ #ifdef CONFIG_SUNXI_GEN_SUN6I #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 +#ifdef CONFIG_USB_MUSB_GADGET +#define SUNXI_USB0_BASE 0x01c19000 +#else #define SUNXI_USB0_BASE 0x01c1a000 +#endif #define SUNXI_USB1_BASE 0x01c1b000 #define SUNXI_USB2_BASE 0x01c1c000 #define SUNXI_USB3_BASE 0x01c1d000

PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Jun Nie jun.nie@linaro.org --- arch/arm/mach-sunxi/usb_phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 9a0a1b9..32ee0d4 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -126,7 +126,8 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, int j = 0, usbc_bit = 0; void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
-#ifdef CONFIG_MACH_SUN8I_A33 +#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ + defined(CONFIG_MACH_SUN50I) /* CSR needs to be explicitly initialized to 0 on A33 */ writel(0, dest); #endif

Hi,
On Sun, Jan 28, 2018 at 09:49:29PM +0530, Jagan Teki wrote:
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Jun Nie jun.nie@linaro.org
Those signed-off-by don't make much sense. Either Jun made that patch and should be the author, or you made that patch, and Jun Signed-off shouldn't be there.
Maxime

On Mon, Jan 29, 2018 at 1:29 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
Hi,
On Sun, Jan 28, 2018 at 09:49:29PM +0530, Jagan Teki wrote:
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Jun Nie jun.nie@linaro.org
Those signed-off-by don't make much sense. Either Jun made that patch and should be the author, or you made that patch, and Jun Signed-off shouldn't be there.
Don't understand what doesn't make sense, more Signed-off-by implies group of people worked on the particular change and author who usually made this. This is what I usually follow all my patches if the change/patch work together.

On Mon, Jan 29, 2018 at 01:44:53PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:29 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
Hi,
On Sun, Jan 28, 2018 at 09:49:29PM +0530, Jagan Teki wrote:
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Jun Nie jun.nie@linaro.org
Those signed-off-by don't make much sense. Either Jun made that patch and should be the author, or you made that patch, and Jun Signed-off shouldn't be there.
Don't understand what doesn't make sense, more Signed-off-by implies group of people worked on the particular change and author who usually made this. This is what I usually follow all my patches if the change/patch work together.
Jun's Signed-off implies that he merged and carried this patch, ie Jun was acting as a maintainer, or was sending a patch on behalf of you. This isn't the case.
Maxime

Bananapi-m2-plus has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts index f3b1d5f..e766aa3 100644 --- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts @@ -93,6 +93,10 @@ }; };
+&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -146,6 +150,10 @@ status = "okay"; };
+&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -189,6 +197,11 @@ status = "okay"; };
+&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { /* USB VBUS is on as long as VCC-IO is on */ status = "okay";

Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/Sinovoip_BPI_M2_Plus_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig index 3338b64..36f8094 100644 --- a/configs/Sinovoip_BPI_M2_Plus_defconfig +++ b/configs/Sinovoip_BPI_M2_Plus_defconfig @@ -16,4 +16,5 @@ CONFIG_SPL=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Now, DM_USB enabled and controller info exctracted from DT so drop explicit count.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/configs/sun50i.h | 1 - 1 file changed, 1 deletion(-)
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index b7b67a1..870cab8 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -13,7 +13,6 @@
#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif
#define CONFIG_SUNXI_USB_PHYS 1

Like H3, H5 has similar fifo config with fifo count 5, so update same H3 config to H5 as well.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/usb/musb-new/sunxi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index c3b8fa4..d02e083 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -295,7 +295,7 @@ static const struct musb_platform_ops sunxi_musb_ops = { .disable = sunxi_musb_disable, };
-#if defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUNXI_H3_H5) static struct musb_fifo_cfg sunxi_musb_fifo_config[] = { { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, @@ -326,7 +326,7 @@ static struct musb_hdrc_config musb_config = { .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_fifo_config), .multipoint = 1, .dyn_fifo = 1, -#if defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUNXI_H3_H5) .num_eps = 5, #else .num_eps = 6,

Like Allwinner H3 even H5 as integrates with 4 USB PHYs which are connected as: PHY#0: shared between USB-OTG_DEVICE and USB_OTG_EHCI0/OHCI0 PHY#1: USB-HCI1(EHCI1/OHCI1) PHY#2: USB-HCI2(EHCI2/OHCI2) PHY#3: USB-HCI3(EHCI3/OHCI3)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/configs/sun50i.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 870cab8..c9dd5f7 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -15,7 +15,11 @@ #define CONFIG_USB_EHCI_SUNXI #endif
-#define CONFIG_SUNXI_USB_PHYS 1 +#ifdef CONFIG_MACH_SUNXI_H3_H5 +# define CONFIG_SUNXI_USB_PHYS 4 +#else +# define CONFIG_SUNXI_USB_PHYS 1 +#endif
#define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000

- enable_pmu_unk1 for V3S/H3/H5/A64 - enable usb 45 Ohm calibration for all non A83T SOC's - adjust PHY's magnitude for all non A83T SOC's
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/usb_phy.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 32ee0d4..a81425d 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -153,41 +153,32 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, } }
-#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#ifndef CONFIG_MACH_SUN8I_A83T static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5 if (phy->id == 0) clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); #endif + +# if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) || \ + defined(CONFIG_MACH_SUN8I_V3S) clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); -} -#elif defined CONFIG_MACH_SUN8I_A83T -static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) -{ -} -#else -static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) -{ - /* The following comments are machine - * translated from Chinese, you have been warned! - */ +# endif
- /* Regulation 45 ohms */ + /* Enable USB 45 Ohm resistor calibration */ if (phy->id == 0) usb_phy_write(phy, 0x0c, 0x01, 1);
- /* adjust PHY's magnitude and rate */ + /* Adjust PHY's magnitude and rate */ usb_phy_write(phy, 0x20, 0x14, 5);
- /* threshold adjustment disconnect */ -#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I + /* Disconnect threshold adjustment */ +# if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I usb_phy_write(phy, 0x2a, 2, 2); -#else +# else usb_phy_write(phy, 0x2a, 3, 2); -#endif - - return; +# endif } #endif

Allwinner V3/H3/H5/A64 have PHY0 dual_route, where routing happens through EHCI/OHCI or through MUSB based id_det. id_det can be 0 and 1 for Host and Peripheral dr_modes and it can be gpio value for OTG.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de --- arch/arm/include/asm/arch-sunxi/usb_phy.h | 1 + arch/arm/mach-sunxi/usb_phy.c | 20 ++++++++++++++++++++ drivers/usb/musb-new/sunxi.c | 7 +++++++ 3 files changed, 28 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h index 5a9cacb..e546e03 100644 --- a/arch/arm/include/asm/arch-sunxi/usb_phy.h +++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h @@ -19,3 +19,4 @@ void sunxi_usb_phy_power_off(int index); int sunxi_usb_phy_vbus_detect(int index); int sunxi_usb_phy_id_detect(int index); void sunxi_usb_phy_enable_squelch_detect(int index, int enable); +void sunxi_usb_phy0_reroute(int id_det); diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index a81425d..93340c7 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -28,6 +28,8 @@ #else #define SUNXI_USB_CSR 0x410 #endif +#define REG_PHY_OTGCTL 0x420 +#define OTGCTL_ROUTE_MUSB BIT(0)
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 #define SUNXI_USB_PASSBY_EN 1 @@ -332,6 +334,24 @@ int sunxi_usb_phy_id_detect(int index) return gpio_get_value(phy->gpio_id_det); }
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) || \ + defined(CONFIG_MACH_SUN8I_V3S) +void sunxi_usb_phy0_reroute(int id_det) +{ + u32 regval; + + regval = readl(SUNXI_USB0_BASE + REG_PHY_OTGCTL); + if (id_det == 0) { + /* Host mode. Route phy0 to EHCI/OHCI */ + regval &= ~OTGCTL_ROUTE_MUSB; + } else { + /* Peripheral mode. Route phy0 to MUSB */ + regval |= OTGCTL_ROUTE_MUSB; + } + writel(regval, SUNXI_USB0_BASE + REG_PHY_OTGCTL); +} +#endif + int sunxi_usb_phy_probe(void) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index d02e083..c64c551 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -272,6 +272,13 @@ static int sunxi_musb_init(struct musb *musb) #endif
sunxi_usb_phy_init(0); +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) || \ + defined(CONFIG_MACH_SUN8I_V3S) + if (is_host_enabled(musb)) + sunxi_usb_phy0_reroute(0); + else + sunxi_usb_phy0_reroute(1); +#endif
USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs);

On 01/28/2018 05:19 PM, Jagan Teki wrote:
Allwinner V3/H3/H5/A64 have PHY0 dual_route, where routing happens through EHCI/OHCI or through MUSB based id_det. id_det can be 0 and 1 for Host and Peripheral dr_modes and it can be gpio value for OTG.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Cc: Marek Vasut marex@denx.de
arch/arm/include/asm/arch-sunxi/usb_phy.h | 1 + arch/arm/mach-sunxi/usb_phy.c | 20 ++++++++++++++++++++ drivers/usb/musb-new/sunxi.c | 7 +++++++ 3 files changed, 28 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h index 5a9cacb..e546e03 100644 --- a/arch/arm/include/asm/arch-sunxi/usb_phy.h +++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h @@ -19,3 +19,4 @@ void sunxi_usb_phy_power_off(int index); int sunxi_usb_phy_vbus_detect(int index); int sunxi_usb_phy_id_detect(int index); void sunxi_usb_phy_enable_squelch_detect(int index, int enable); +void sunxi_usb_phy0_reroute(int id_det); diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index a81425d..93340c7 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -28,6 +28,8 @@ #else #define SUNXI_USB_CSR 0x410 #endif +#define REG_PHY_OTGCTL 0x420 +#define OTGCTL_ROUTE_MUSB BIT(0)
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 #define SUNXI_USB_PASSBY_EN 1 @@ -332,6 +334,24 @@ int sunxi_usb_phy_id_detect(int index) return gpio_get_value(phy->gpio_id_det); }
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) || \
defined(CONFIG_MACH_SUN8I_V3S)
+void sunxi_usb_phy0_reroute(int id_det)
Is this supposed to be bool mode ?
Also, ifdefs ... use DT.
+{
- u32 regval;
- regval = readl(SUNXI_USB0_BASE + REG_PHY_OTGCTL);
- if (id_det == 0) {
/* Host mode. Route phy0 to EHCI/OHCI */
regval &= ~OTGCTL_ROUTE_MUSB;
- } else {
/* Peripheral mode. Route phy0 to MUSB */
regval |= OTGCTL_ROUTE_MUSB;
- }
- writel(regval, SUNXI_USB0_BASE + REG_PHY_OTGCTL);
+} +#endif
int sunxi_usb_phy_probe(void) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index d02e083..c64c551 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -272,6 +272,13 @@ static int sunxi_musb_init(struct musb *musb) #endif
sunxi_usb_phy_init(0); +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) || \
defined(CONFIG_MACH_SUN8I_V3S)
- if (is_host_enabled(musb))
sunxi_usb_phy0_reroute(0);
- else
sunxi_usb_phy0_reroute(1);
+#endif
USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs);

Order sun50i-h5-orangepi-pc2.dts nodes in alphabetic
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 49 +++++++++++++++++---------------- 1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 780d59a..4f05340 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -50,6 +50,11 @@ model = "OrangePi PC 2"; compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
+ aliases { + serial0 = &uart0; + ethernet0 = &emac; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -58,11 +63,6 @@ reg = <0x40000000 0x40000000>; };
- aliases { - serial0 = &uart0; - ethernet0 = &emac; - }; - soc { reg_vcc3v3: vcc3v3 { compatible = "regulator-fixed"; @@ -73,6 +73,22 @@ }; };
+&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ehci1 { + status = "okay"; +}; + &mmc0 { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc", @@ -86,6 +102,10 @@ status = "okay"; };
+&ohci1 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -96,22 +116,3 @@ status = "okay"; };
-&ohci1 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-mode = "rgmii"; - phy = <&phy1>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -};

U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated): =================== part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE - default 0x88000 if ARCH_SUNXI + default 0x88000 if ARCH_SUNXI && !ARM64 + default 0x100000 if ARCH_SUNXI && ARM64 help Offset from the start of the device (or partition)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 6236e12..687c7a3 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -154,7 +154,7 @@ * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used * directly in a makefile, without the preprocessor expansion. */ -#define CONFIG_BOARD_SIZE_LIMIT 0x7e000 +#define CONFIG_BOARD_SIZE_LIMIT 0xf6000 #endif
#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1

On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
- default 0x88000 if ARCH_SUNXI
- default 0x88000 if ARCH_SUNXI && !ARM64
- default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Why do you think we went into so great troubles recently?
Maxime

On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..

On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Maxime

On Tue, Jan 30, 2018 at 1:54 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
True, but we can't control this adding new stuff ultimately increasing size. either we can stop working new features or increasing partition size, do you have any other suggestions?
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Sorry, can't understand please explain it little bit.

On Tue, Jan 30, 2018 at 02:29:27PM +0530, Jagan Teki wrote:
On Tue, Jan 30, 2018 at 1:54 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
True, but we can't control this adding new stuff ultimately increasing size. either we can stop working new features or increasing partition size, do you have any other suggestions?
https://lists.denx.de/pipermail/u-boot/2017-December/314940.html
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Sorry, can't understand please explain it little bit.
We've had: https://patchwork.ozlabs.org/cover/828100/ https://patchwork.ozlabs.org/cover/851904/ https://patchwork.ozlabs.org/cover/864994/
That were doing everything we could to *not* move the location of the environment in order to address the issue. Why do you think we did that?
Maxime

On Wed, Jan 31, 2018 at 9:25 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Tue, Jan 30, 2018 at 02:29:27PM +0530, Jagan Teki wrote:
On Tue, Jan 30, 2018 at 1:54 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
True, but we can't control this adding new stuff ultimately increasing size. either we can stop working new features or increasing partition size, do you have any other suggestions?
https://lists.denx.de/pipermail/u-boot/2017-December/314940.html
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Sorry, can't understand please explain it little bit.
We've had: https://patchwork.ozlabs.org/cover/828100/ https://patchwork.ozlabs.org/cover/851904/ https://patchwork.ozlabs.org/cover/864994/
That were doing everything we could to *not* move the location of the environment in order to address the issue. Why do you think we did that?
Maxime
-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com

On Wed, Jan 31, 2018 at 9:25 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Tue, Jan 30, 2018 at 02:29:27PM +0530, Jagan Teki wrote:
On Tue, Jan 30, 2018 at 1:54 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote:
U-Boot size is crossing MMC environment offset due to adding new features on arm64 boards. So update the ENV_OFFSET to 0x100000 so the u-boot size limit increased to 0xf6000
MMC layout(updated):
part: sector: size unused: 0: 8KiB SPL: 16: 32KiB U-Boot: 80: 984KiB uENV: 2048: 128KiB
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
env/Kconfig | 3 ++- include/configs/sunxi-common.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig index 692f863..e2b32c2 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -441,7 +441,8 @@ config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE
default 0x88000 if ARCH_SUNXI
default 0x88000 if ARCH_SUNXI && !ARM64
default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
True, but we can't control this adding new stuff ultimately increasing size. either we can stop working new features or increasing partition size, do you have any other suggestions?
https://lists.denx.de/pipermail/u-boot/2017-December/314940.html
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Sorry, can't understand please explain it little bit.
We've had: https://patchwork.ozlabs.org/cover/828100/ https://patchwork.ozlabs.org/cover/851904/ https://patchwork.ozlabs.org/cover/864994/
Now we have transition IN, and we can able to change the SIZE check right?

On Tue, Feb 06, 2018 at 03:49:28PM +0530, Jagan Teki wrote:
On Wed, Jan 31, 2018 at 9:25 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Tue, Jan 30, 2018 at 02:29:27PM +0530, Jagan Teki wrote:
On Tue, Jan 30, 2018 at 1:54 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Mon, Jan 29, 2018 at 01:49:14PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:32 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:38PM +0530, Jagan Teki wrote: > U-Boot size is crossing MMC environment offset due to adding > new features on arm64 boards. So update the ENV_OFFSET to > 0x100000 so the u-boot size limit increased to 0xf6000 > > MMC layout(updated): > =================== > part: sector: size > unused: 0: 8KiB > SPL: 16: 32KiB > U-Boot: 80: 984KiB > uENV: 2048: 128KiB > > Signed-off-by: Jagan Teki jagan@amarulasolutions.com > --- > env/Kconfig | 3 ++- > include/configs/sunxi-common.h | 2 +- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/env/Kconfig b/env/Kconfig > index 692f863..e2b32c2 100644 > --- a/env/Kconfig > +++ b/env/Kconfig > @@ -441,7 +441,8 @@ config ENV_OFFSET > hex "Environment Offset" > depends on !ENV_IS_IN_UBI > depends on !ENV_IS_NOWHERE > - default 0x88000 if ARCH_SUNXI > + default 0x88000 if ARCH_SUNXI && !ARM64 > + default 0x100000 if ARCH_SUNXI && ARM64
This breaks all existing platforms. NAK.
Can you elaborate, what it breaks. 32 bit sunxi start with 0x88000 and 64-sun start with 0x100000 this is what I expecting here.
If you have an environment already flashed, flashing the new u-boot will overwrite it, and might break any partition layout you have set.
True, but we can't control this adding new stuff ultimately increasing size. either we can stop working new features or increasing partition size, do you have any other suggestions?
https://lists.denx.de/pipermail/u-boot/2017-December/314940.html
Why do you think we went into so great troubles recently?
Certainly yes, MUSB_GADGET increasing u-boot.itb 548K
u-boot.itb exceeds file size limit: limit: 516096 bytes actual: 560088 bytes excess: 43992 bytes make: *** [u-boot.itb] Error 1 make: *** Waiting for unfinished jobs..
That's not my question. Why do you think we had some many discussions, debates and patches if we could have done so from the beginning?
Sorry, can't understand please explain it little bit.
We've had: https://patchwork.ozlabs.org/cover/828100/ https://patchwork.ozlabs.org/cover/851904/ https://patchwork.ozlabs.org/cover/864994/
Now we have transition IN, and we can able to change the SIZE check right?
Not until the transition is over.
Maxime

Insert 128KiB uENV partition after loader2 on gpt partition table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/configs/sunxi-common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 687c7a3..4f3170d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -505,6 +505,7 @@ extern int soft_i2c_gpio_scl; #define PARTS_DEFAULT \ "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ + "name=uEnv,size=128K,uuid=${uuid_gpt_uenv};" \ "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ "name=system,size=-,uuid=${uuid_gpt_system};"

On Sun, Jan 28, 2018 at 09:49:39PM +0530, Jagan Teki wrote:
Insert 128KiB uENV partition after loader2 on gpt partition table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
What is the point of this partition?
If it is to store the environment, it was discussed to add it into the esp partition.
Maxime

On Mon, Jan 29, 2018 at 1:33 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:39PM +0530, Jagan Teki wrote:
Insert 128KiB uENV partition after loader2 on gpt partition table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
What is the point of this partition?
Yes for u-boot environment.
If it is to store the environment, it was discussed to add it into the esp partition.
If it is part of esp are we sure env part from esp is always unchanged expect u-boot saveenv?, I would prefer env has separate partition because, there could be chance of formatting esp from host and copy Linux images instead of fastboot write or any other media write.

On Mon, Jan 29, 2018 at 02:01:49PM +0530, Jagan Teki wrote:
On Mon, Jan 29, 2018 at 1:33 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Jan 28, 2018 at 09:49:39PM +0530, Jagan Teki wrote:
Insert 128KiB uENV partition after loader2 on gpt partition table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
What is the point of this partition?
Yes for u-boot environment.
If it is to store the environment, it was discussed to add it into the esp partition.
If it is part of esp are we sure env part from esp is always unchanged expect u-boot saveenv?, I would prefer env has separate partition because, there could be chance of formatting esp from host and copy Linux images instead of fastboot write or any other media write.
Please look at the discussion we had at the time. The esp partition is under the firmware control, so it's safe to put our environment there.
Maxime

orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 4f05340..8d2f73a 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -85,6 +85,10 @@ }; };
+&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -102,6 +106,10 @@ status = "okay"; };
+&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -112,6 +120,11 @@ status = "okay"; };
+&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { status = "okay"; };

Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/orangepi_pc2_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index e5fea42..9db7655 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -15,4 +15,5 @@ CONFIG_SPL=y CONFIG_SPL_SPI_SUNXI=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

orangepi-prime has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun50i-h5-orangepi-prime.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts index d4577df..131d805 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts @@ -72,6 +72,10 @@ }; };
+&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -89,6 +93,10 @@ status = "okay"; };
+&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -99,6 +107,11 @@ status = "okay"; };
+&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { status = "okay"; };

Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/orangepi_prime_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 3d87374..a2e8f2e 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -13,4 +13,5 @@ CONFIG_SPL=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

clock gating bits on a64 are different than H3_H5, so fix them on clock_sun6i.h
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 624d624..30f75f7 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -270,7 +270,7 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */ -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#ifdef CONFIG_MACH_SUNXI_H3_H5 #define AHB_GATE_OFFSET_USB_OHCI3 31 #define AHB_GATE_OFFSET_USB_OHCI2 30 #define AHB_GATE_OFFSET_USB_OHCI1 29 @@ -280,13 +280,19 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 #define AHB_GATE_OFFSET_OTG_DEVICE 23 +#elif defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI0 25 +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif -#ifndef CONFIG_MACH_SUN8I_R40 +#ifdef CONFIG_MACH_SUN50I +#define AHB_GATE_OFFSET_USB0 23 +#elif !defined(CONFIG_MACH_SUN8I_R40) #define AHB_GATE_OFFSET_USB0 24 #else #define AHB_GATE_OFFSET_USB0 25

There are two USB PHY's on A64 which are connected as: PHY#0: shared between USB-OTG_DEVICE and USB-OTG-HCI PHY#1: USB-HCI0(EHCI0/OHCI0)
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/configs/sun50i.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index c9dd5f7..1a12ed5 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -18,7 +18,7 @@ #ifdef CONFIG_MACH_SUNXI_H3_H5 # define CONFIG_SUNXI_USB_PHYS 4 #else -# define CONFIG_SUNXI_USB_PHYS 1 +# define CONFIG_SUNXI_USB_PHYS 2 #endif
#define GICD_BASE 0x1c81000

Like other Allwinner SoC, the A64 is missing the config register from the musb hardware block. Use a known working value for it like other SoC.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/usb/musb-new/musb_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 8a357ed..7a4a151 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -433,7 +433,7 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) static inline u8 musb_read_configdata(void __iomem *mbase) { #if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T) || \ - defined(CONFIG_MACH_SUNXI_H3_H5) + defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde; #else

Allwinner a64 needs to clear the SIDDP bit from PHYCTL register once the phy_init done.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- arch/arm/mach-sunxi/usb_phy.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 93340c7..b9542f8 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -45,6 +45,7 @@ /* A83T specific control bits for PHY0 */ #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) #define SUNXI_PHY_CTL_SIDDQ BIT(3) +#define SUNXI_PHY_CTL_SIDDP BIT(1)
/* A83T HSIC specific bits */ #define SUNXI_EHCI_HS_FORCE BIT(20) @@ -249,6 +250,12 @@ void sunxi_usb_phy_init(int index) SUNXI_PHY_CTL_SIDDQ); } #endif + +#ifdef CONFIG_MACH_SUN50I + if (phy->id == 0) + clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDP); +#endif }
void sunxi_usb_phy_exit(int index)

Sync bananapi-m64 usb_otg node from Linux.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun50i-a64-bananapi-m64.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index 02db114..80405e5 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -119,3 +119,13 @@ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + status = "okay"; +};

Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/bananapi_m64_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 461567f..11397ae 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -14,4 +14,5 @@ CONFIG_SPL=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Sync a64-olinuxino usb_otg node from Linux.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/sun50i-a64-olinuxino.dts | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index 7bd4730..1c9788b 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -82,3 +82,8 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +};

Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/a64-olinuxino_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 02da392..fb29454 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -13,4 +13,5 @@ CONFIG_SPL=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
participants (4)
-
Jagan Teki
-
Marek Vasut
-
Maxime Ripard
-
Maxime Ripard