[U-Boot] [PATCH 2/8] APM82xxx: Add Common register definitions
From: Tirumala Marri tmarri@apm.com
This patch adds APM82XXX specific definitions, which include clock and boot strap.
Signed-off-by: Tirumala R Marri tmarri@apm.com --- include/ppc440.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++- include/ppc4xx.h | 7 +++-- 2 files changed, 59 insertions(+), 5 deletions(-)
diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..3bd8e98 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,6 +58,25 @@ | Clocking Controller +----------------------------------------------------------------------------*/ /* values for clkcfga register - indirect addressing of these regs */ +#if defined(CONFIG_APM82XXX) +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 +#else #define CPR0_PLLC 0x0040 #define CPR0_PLLD 0x0060 #define CPR0_PRIMAD0 0x0080 @@ -67,6 +86,7 @@ #define CPR0_MALD 0x0100 #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +#endif /*if defined(CONFIG_APM82XXX) */
/* 440EPX boot strap options */ #define BOOT_STRAP_OPTION_A 0x00000000 @@ -1275,7 +1295,36 @@ #define SDR0_AHB_CFG 0x370 #define SDR0_USB2HOST_CFG 0x371 #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_APM82XXX) + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
+#define SDR_SDSTP1_RL_DECODE(x) ((x & 0x000C0000) >> 18) +#define SDR_SDSTP1_RL_EBC 0x0 +#define SDR_SDSTP1_RL_NDFC 0x2 + +/* ECID */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370 + +/* DDR SDRAM Controller clock (CPR register)*/ +#define SDR0_DDRCE 0x00E0 /* SDR register */ +#define CPR0_DDR2D 0x0100 /* CPR register */ +#define CPR0_DDR2D_DDR2DV_ENCODE(n) ((((unsigned long)(n))&0x03)<<25) +#define CPR0_DDR2D_DDR2DV_DECODE(n) ((((unsigned long)(n))>>25)&0x03) + +#endif #define SDR0_SDCS_SDD (0x80000000 >> 31)
#if defined(CONFIG_440GP) @@ -1517,7 +1566,8 @@ #define SDR0_EBC0 0x00000100 #define SDR0_SDSTP2 0x00004001 #define SDR0_SDSTP3 0x00004001 -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) ||\ + defined(CONFIG_APM82XXX)
#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ @@ -1909,9 +1959,12 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) +#if !defined(CONFIG_APM82XXX) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) +#endif
#define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ee30a4c..3224d5f 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -44,14 +44,15 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define CONFIG_NAND_NDFC #endif
@@ -61,7 +62,7 @@ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
#define PLB_ARBITER_BASE 0x80
Hi Marri,
On Thursday 26 August 2010 23:05:49 tmarri@apm.com wrote:
From: Tirumala Marri tmarri@apm.com
This patch adds APM82XXX specific definitions, which include clock and boot strap.
Please find some comments below.
Signed-off-by: Tirumala R Marri tmarri@apm.com
include/ppc440.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++- include/ppc4xx.h | 7 +++-- 2 files changed, 59 insertions(+), 5 deletions(-)
diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..3bd8e98 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,6 +58,25 @@
| Clocking Controller
+------------------------------------------------------------------------- ---*/ /* values for clkcfga register - indirect addressing of these regs */ +#if defined(CONFIG_APM82XXX) +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 +#else #define CPR0_PLLC 0x0040 #define CPR0_PLLD 0x0060 #define CPR0_PRIMAD0 0x0080 @@ -67,6 +86,7 @@ #define CPR0_MALD 0x0100 #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +#endif /*if defined(CONFIG_APM82XXX) */
/* 440EPX boot strap options */ #define BOOT_STRAP_OPTION_A 0x00000000 @@ -1275,7 +1295,36 @@ #define SDR0_AHB_CFG 0x370 #define SDR0_USB2HOST_CFG 0x371 #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_APM82XXX)
+#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
Add spaces around the operators. I suggest to replace "unsigned int" with "u32" to reduce the line-size resulting in this:
#define SDR0_DDR0_DDRM_ENCODE(n) ((((u32)(n)) & 0x03) << 29) #define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) #define SDR0_DDR0_TUNE_ENCODE(n) ((((u32)(n)) & 0x2FF) << 0) #define SDR0_DDR0_TUNE_DECODE(n) ((((u32)(n)) >> 0) & 0x2FF)
BTW: I couldn't find any reference to this SDR0_DDR0 register (0xe1) in the APM8xxx users manual. You might want to add this description there.
+#define SDR_SDSTP1_RL_DECODE(x) ((x & 0x000C0000) >> 18)
Missing braces around "x".
+#define SDR_SDSTP1_RL_EBC 0x0 +#define SDR_SDSTP1_RL_NDFC 0x2
+/* ECID */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083
+/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370
+/* DDR SDRAM Controller clock (CPR register)*/ +#define SDR0_DDRCE 0x00E0 /* SDR register */ +#define CPR0_DDR2D 0x0100 /* CPR register */ +#define CPR0_DDR2D_DDR2DV_ENCODE(n) ((((unsigned long)(n))&0x03)<<25) +#define CPR0_DDR2D_DDR2DV_DECODE(n) ((((unsigned long)(n))>>25)&0x03)
Again, please add spaces and change to u32.
Please change and resubmit. Thanks.
Cheers, Stefan
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Dear tmarri@apm.com,
In message 1282856749-24425-1-git-send-email-tmarri@apm.com you wrote:
From: Tirumala Marri tmarri@apm.com
This patch adds APM82XXX specific definitions, which include clock and boot strap.
Signed-off-by: Tirumala R Marri tmarri@apm.com
include/ppc440.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++- include/ppc4xx.h | 7 +++-- 2 files changed, 59 insertions(+), 5 deletions(-)
It makes no sense to split this into a spearate patch. Please squash into the commit where these defines are first referenced.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Sunday, August 29, 2010 1:57 AM To: tmarri@apm.com Cc: u-boot@lists.denx.de; open-source-review@apm.com Subject: Re: [U-Boot] [PATCH 2/8] APM82xxx: Add Common register definitions
Dear tmarri@apm.com,
In message 1282856749-24425-1-git-send-email-tmarri@apm.com you wrote:
From: Tirumala Marri tmarri@apm.com
This patch adds APM82XXX specific definitions, which include clock and boot strap.
Signed-off-by: Tirumala R Marri tmarri@apm.com
include/ppc440.h | 57
++++++++++++++++++++++++++++++++++++++++++++++++++++-
include/ppc4xx.h | 7 +++-- 2 files changed, 59 insertions(+), 5 deletions(-)
It makes no sense to split this into a spearate patch. Please squash into the commit where these defines are first referenced.
Mr Wolfgang, Sure will fix it. Regards, Marri
participants (4)
-
Stefan Roese -
Tirumala Marri -
tmarriļ¼ apm.com
-
Wolfgang Denk