[U-Boot-Users] [PATCH] [ads5121] Set ips dividor to 1/4 of csb clock.
Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.
Signed-off-by: Grzegorz Bernacki gjb@semihalf.com
diff --git a/include/mpc512x.h b/include/mpc512x.h index a06b5c6..d1c6fb2 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -185,7 +185,7 @@
/* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV 0x4 #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23
Grzegorz,
Sorry I got an update from the hw people today and the recommended freq for the ips is 66MHz so we need to change the divider to 0x3. I'm pretty sure this is final.
John
Grzegorz Bernacki wrote:
Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.
Signed-off-by: Grzegorz Bernacki gjb@semihalf.com
diff --git a/include/mpc512x.h b/include/mpc512x.h index a06b5c6..d1c6fb2 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -185,7 +185,7 @@
/* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV 0x4 #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23
participants (2)
-
Grzegorz Bernacki -
John Rigby